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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck %s3 4define void @callbr_inline_asm(ptr %src, ptr %dst1, ptr %dst2, i32 %c) {5; CHECK-LABEL: callbr_inline_asm:6; CHECK: ; %bb.0:7; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8; CHECK-NEXT: flat_load_dword v0, v[0:1]9; CHECK-NEXT: ;;#ASMSTART10; CHECK-NEXT: v_cmp_gt_i32 vcc v6, 42; s_cbranch_vccnz .LBB0_211; CHECK-NEXT: ;;#ASMEND12; CHECK-NEXT: ; %bb.1: ; %fallthrough13; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)14; CHECK-NEXT: flat_store_dword v[2:3], v015; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)16; CHECK-NEXT: s_setpc_b64 s[30:31]17; CHECK-NEXT: .LBB0_2: ; Inline asm indirect target18; CHECK-NEXT: ; %indirect19; CHECK-NEXT: ; Label of block must be emitted20; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)21; CHECK-NEXT: flat_store_dword v[4:5], v022; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)23; CHECK-NEXT: s_setpc_b64 s[30:31]24 %a = load i32, ptr %src, align 425 callbr void asm "v_cmp_gt_i32 vcc $0, 42; s_cbranch_vccnz ${1:l}", "r,!i"(i32 %c) to label %fallthrough [label %indirect]26fallthrough:27 store i32 %a, ptr %dst1, align 428 br label %ret29indirect:30 store i32 %a, ptr %dst2, align 431 br label %ret32ret:33 ret void34}35 36define void @callbr_self_loop(i1 %c) {37; CHECK-LABEL: callbr_self_loop:38; CHECK: ; %bb.0:39; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)40; CHECK-NEXT: .LBB1_1: ; %callbr41; CHECK-NEXT: ; =>This Inner Loop Header: Depth=142; CHECK-NEXT: ;;#ASMSTART43; CHECK-NEXT: ;;#ASMEND44; CHECK-NEXT: s_branch .LBB1_145; CHECK-NEXT: .LBB1_2: ; Inline asm indirect target46; CHECK-NEXT: ; %callbr.target.ret47; CHECK-NEXT: ; Label of block must be emitted48; CHECK-NEXT: s_setpc_b64 s[30:31]49 br label %callbr50callbr:51 callbr void asm "", "!i"() to label %callbr [label %ret]52ret:53 ret void54}55