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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11,GFX11-TRUE16 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11,GFX11-FAKE16 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-TRUE16 %s7; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-FAKE16 %s8 9; Make sure we don't crash or assert on spir_kernel calling convention.10 11define spir_kernel void @kernel(ptr addrspace(1) %out) {12; SI-LABEL: kernel:13; SI: ; %bb.0: ; %entry14; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x915; SI-NEXT: s_mov_b32 s3, 0xf00016; SI-NEXT: s_mov_b32 s2, -117; SI-NEXT: v_mov_b32_e32 v0, 018; SI-NEXT: s_waitcnt lgkmcnt(0)19; SI-NEXT: buffer_store_dword v0, off, s[0:3], 020; SI-NEXT: s_endpgm21;22; VI-LABEL: kernel:23; VI: ; %bb.0: ; %entry24; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2425; VI-NEXT: v_mov_b32_e32 v2, 026; VI-NEXT: s_waitcnt lgkmcnt(0)27; VI-NEXT: v_mov_b32_e32 v0, s028; VI-NEXT: v_mov_b32_e32 v1, s129; VI-NEXT: flat_store_dword v[0:1], v230; VI-NEXT: s_endpgm31;32; GFX11-LABEL: kernel:33; GFX11: ; %bb.0: ; %entry34; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x2435; GFX11-NEXT: v_mov_b32_e32 v0, 036; GFX11-NEXT: s_waitcnt lgkmcnt(0)37; GFX11-NEXT: global_store_b32 v0, v0, s[0:1]38; GFX11-NEXT: s_endpgm39;40; GFX1250-LABEL: kernel:41; GFX1250: ; %bb.0: ; %entry42; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 143; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x2444; GFX1250-NEXT: v_mov_b32_e32 v0, 045; GFX1250-NEXT: s_wait_kmcnt 0x046; GFX1250-NEXT: global_store_b32 v0, v0, s[0:1]47; GFX1250-NEXT: s_endpgm48entry:49 store i32 0, ptr addrspace(1) %out50 ret void51}52 53; FIXME: This is treated like a kernel54; XGCN-LABEL: {{^}}func:55; XGCN: s_endpgm56; define spir_func void @func(ptr addrspace(1) %out) {57; entry:58; store i32 0, ptr addrspace(1) %out59; ret void60; }61 62define amdgpu_ps half @ps_ret_cc_f16(half %arg0) {63; SI-LABEL: ps_ret_cc_f16:64; SI: ; %bb.0:65; SI-NEXT: v_cvt_f16_f32_e32 v0, v066; SI-NEXT: v_cvt_f32_f16_e32 v0, v067; SI-NEXT: v_add_f32_e32 v0, 1.0, v068; SI-NEXT: ; return to shader part epilog69;70; VI-LABEL: ps_ret_cc_f16:71; VI: ; %bb.0:72; VI-NEXT: v_add_f16_e32 v0, 1.0, v073; VI-NEXT: ; return to shader part epilog74;75; GFX11-TRUE16-LABEL: ps_ret_cc_f16:76; GFX11-TRUE16: ; %bb.0:77; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l78; GFX11-TRUE16-NEXT: ; return to shader part epilog79;80; GFX11-FAKE16-LABEL: ps_ret_cc_f16:81; GFX11-FAKE16: ; %bb.0:82; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v083; GFX11-FAKE16-NEXT: ; return to shader part epilog84;85; GFX1250-TRUE16-LABEL: ps_ret_cc_f16:86; GFX1250-TRUE16: ; %bb.0:87; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 188; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 089; GFX1250-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l90; GFX1250-TRUE16-NEXT: ; return to shader part epilog91;92; GFX1250-FAKE16-LABEL: ps_ret_cc_f16:93; GFX1250-FAKE16: ; %bb.0:94; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 195; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 096; GFX1250-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v097; GFX1250-FAKE16-NEXT: ; return to shader part epilog98 %add = fadd half %arg0, 1.099 ret half %add100}101 102define amdgpu_ps half @ps_ret_cc_inreg_f16(half inreg %arg0) {103; SI-LABEL: ps_ret_cc_inreg_f16:104; SI: ; %bb.0:105; SI-NEXT: v_cvt_f16_f32_e32 v0, s0106; SI-NEXT: v_cvt_f32_f16_e32 v0, v0107; SI-NEXT: v_add_f32_e32 v0, 1.0, v0108; SI-NEXT: ; return to shader part epilog109;110; VI-LABEL: ps_ret_cc_inreg_f16:111; VI: ; %bb.0:112; VI-NEXT: v_add_f16_e64 v0, s0, 1.0113; VI-NEXT: ; return to shader part epilog114;115; GFX11-TRUE16-LABEL: ps_ret_cc_inreg_f16:116; GFX11-TRUE16: ; %bb.0:117; GFX11-TRUE16-NEXT: v_add_f16_e64 v0.l, s0, 1.0118; GFX11-TRUE16-NEXT: ; return to shader part epilog119;120; GFX11-FAKE16-LABEL: ps_ret_cc_inreg_f16:121; GFX11-FAKE16: ; %bb.0:122; GFX11-FAKE16-NEXT: v_add_f16_e64 v0, s0, 1.0123; GFX11-FAKE16-NEXT: ; return to shader part epilog124;125; GFX1250-LABEL: ps_ret_cc_inreg_f16:126; GFX1250: ; %bb.0:127; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1128; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0129; GFX1250-NEXT: s_add_f16 s0, s0, 1.0130; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_3)131; GFX1250-NEXT: v_mov_b32_e32 v0, s0132; GFX1250-NEXT: ; return to shader part epilog133 %add = fadd half %arg0, 1.0134 ret half %add135}136 137define fastcc float @fastcc(float %arg0) #0 {138; SI-LABEL: fastcc:139; SI: ; %bb.0:140; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)141; SI-NEXT: v_add_f32_e32 v0, 4.0, v0142; SI-NEXT: s_setpc_b64 s[30:31]143;144; VI-LABEL: fastcc:145; VI: ; %bb.0:146; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)147; VI-NEXT: v_add_f32_e32 v0, 4.0, v0148; VI-NEXT: s_setpc_b64 s[30:31]149;150; GFX11-LABEL: fastcc:151; GFX11: ; %bb.0:152; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)153; GFX11-NEXT: v_add_f32_e32 v0, 4.0, v0154; GFX11-NEXT: s_setpc_b64 s[30:31]155;156; GFX1250-LABEL: fastcc:157; GFX1250: ; %bb.0:158; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0159; GFX1250-NEXT: s_wait_kmcnt 0x0160; GFX1250-NEXT: v_add_f32_e32 v0, 4.0, v0161; GFX1250-NEXT: s_set_pc_i64 s[30:31]162 %add = fadd float %arg0, 4.0163 ret float %add164}165 166define coldcc float @coldcc(float %arg0) #0 {167; SI-LABEL: coldcc:168; SI: ; %bb.0:169; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)170; SI-NEXT: v_add_f32_e32 v0, 4.0, v0171; SI-NEXT: s_setpc_b64 s[30:31]172;173; VI-LABEL: coldcc:174; VI: ; %bb.0:175; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)176; VI-NEXT: v_add_f32_e32 v0, 4.0, v0177; VI-NEXT: s_setpc_b64 s[30:31]178;179; GFX11-LABEL: coldcc:180; GFX11: ; %bb.0:181; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)182; GFX11-NEXT: v_add_f32_e32 v0, 4.0, v0183; GFX11-NEXT: s_setpc_b64 s[30:31]184;185; GFX1250-LABEL: coldcc:186; GFX1250: ; %bb.0:187; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0188; GFX1250-NEXT: s_wait_kmcnt 0x0189; GFX1250-NEXT: v_add_f32_e32 v0, 4.0, v0190; GFX1250-NEXT: s_set_pc_i64 s[30:31]191 %add = fadd float %arg0, 4.0192 ret float %add193}194 195define amdgpu_kernel void @call_coldcc() #0 {196; SI-LABEL: call_coldcc:197; SI: ; %bb.0:198; SI-NEXT: s_mov_b32 s32, 0199; SI-NEXT: s_mov_b32 s20, SCRATCH_RSRC_DWORD0200; SI-NEXT: s_mov_b32 s21, SCRATCH_RSRC_DWORD1201; SI-NEXT: s_mov_b32 s22, -1202; SI-NEXT: s_mov_b32 s23, 0xe8f000203; SI-NEXT: s_add_u32 s20, s20, s11204; SI-NEXT: s_addc_u32 s21, s21, 0205; SI-NEXT: s_mov_b32 s14, s10206; SI-NEXT: s_mov_b32 s13, s9207; SI-NEXT: s_mov_b32 s12, s8208; SI-NEXT: s_mov_b64 s[10:11], s[6:7]209; SI-NEXT: s_add_u32 s8, s4, 36210; SI-NEXT: v_lshlrev_b32_e32 v2, 20, v2211; SI-NEXT: s_addc_u32 s9, s5, 0212; SI-NEXT: s_getpc_b64 s[4:5]213; SI-NEXT: s_add_u32 s4, s4, coldcc@gotpcrel32@lo+4214; SI-NEXT: s_addc_u32 s5, s5, coldcc@gotpcrel32@hi+12215; SI-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0216; SI-NEXT: v_lshlrev_b32_e32 v1, 10, v1217; SI-NEXT: v_or_b32_e32 v0, v0, v1218; SI-NEXT: v_or_b32_e32 v31, v0, v2219; SI-NEXT: v_mov_b32_e32 v0, 1.0220; SI-NEXT: s_mov_b64 s[4:5], s[0:1]221; SI-NEXT: s_mov_b64 s[6:7], s[2:3]222; SI-NEXT: s_mov_b64 s[0:1], s[20:21]223; SI-NEXT: s_mov_b64 s[2:3], s[22:23]224; SI-NEXT: s_waitcnt lgkmcnt(0)225; SI-NEXT: s_swappc_b64 s[30:31], s[16:17]226; SI-NEXT: s_mov_b32 s3, 0xf000227; SI-NEXT: s_mov_b32 s2, -1228; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0229; SI-NEXT: s_endpgm230;231; VI-LABEL: call_coldcc:232; VI: ; %bb.0:233; VI-NEXT: s_mov_b32 s88, SCRATCH_RSRC_DWORD0234; VI-NEXT: s_mov_b32 s89, SCRATCH_RSRC_DWORD1235; VI-NEXT: s_mov_b32 s90, -1236; VI-NEXT: s_mov_b32 s91, 0xe80000237; VI-NEXT: s_add_u32 s88, s88, s11238; VI-NEXT: s_addc_u32 s89, s89, 0239; VI-NEXT: s_mov_b32 s12, s8240; VI-NEXT: s_add_u32 s8, s4, 36241; VI-NEXT: s_mov_b32 s13, s9242; VI-NEXT: s_addc_u32 s9, s5, 0243; VI-NEXT: s_getpc_b64 s[4:5]244; VI-NEXT: s_add_u32 s4, s4, coldcc@gotpcrel32@lo+4245; VI-NEXT: s_addc_u32 s5, s5, coldcc@gotpcrel32@hi+12246; VI-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0247; VI-NEXT: v_lshlrev_b32_e32 v1, 10, v1248; VI-NEXT: s_mov_b32 s14, s10249; VI-NEXT: s_mov_b64 s[10:11], s[6:7]250; VI-NEXT: v_lshlrev_b32_e32 v2, 20, v2251; VI-NEXT: v_or_b32_e32 v0, v0, v1252; VI-NEXT: s_mov_b64 s[4:5], s[0:1]253; VI-NEXT: s_mov_b64 s[6:7], s[2:3]254; VI-NEXT: s_mov_b64 s[0:1], s[88:89]255; VI-NEXT: v_or_b32_e32 v31, v0, v2256; VI-NEXT: s_mov_b64 s[2:3], s[90:91]257; VI-NEXT: v_mov_b32_e32 v0, 1.0258; VI-NEXT: s_mov_b32 s32, 0259; VI-NEXT: s_waitcnt lgkmcnt(0)260; VI-NEXT: s_swappc_b64 s[30:31], s[16:17]261; VI-NEXT: flat_store_dword v[0:1], v0262; VI-NEXT: s_endpgm263;264; GFX11-LABEL: call_coldcc:265; GFX11: ; %bb.0:266; GFX11-NEXT: s_add_u32 s8, s4, 36267; GFX11-NEXT: s_addc_u32 s9, s5, 0268; GFX11-NEXT: s_getpc_b64 s[4:5]269; GFX11-NEXT: s_add_u32 s4, s4, coldcc@gotpcrel32@lo+4270; GFX11-NEXT: s_addc_u32 s5, s5, coldcc@gotpcrel32@hi+12271; GFX11-NEXT: v_dual_mov_b32 v31, v0 :: v_dual_mov_b32 v0, 1.0272; GFX11-NEXT: s_load_b64 s[16:17], s[4:5], 0x0273; GFX11-NEXT: s_mov_b32 s12, s13274; GFX11-NEXT: s_mov_b64 s[10:11], s[6:7]275; GFX11-NEXT: s_mov_b64 s[4:5], s[0:1]276; GFX11-NEXT: s_mov_b64 s[6:7], s[2:3]277; GFX11-NEXT: s_mov_b32 s13, s14278; GFX11-NEXT: s_mov_b32 s14, s15279; GFX11-NEXT: s_mov_b32 s32, 0280; GFX11-NEXT: s_waitcnt lgkmcnt(0)281; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17]282; GFX11-NEXT: global_store_b32 v[0:1], v0, off283; GFX11-NEXT: s_endpgm284;285; GFX1250-LABEL: call_coldcc:286; GFX1250: ; %bb.0:287; GFX1250-NEXT: s_mov_b32 s32, 0288; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1289; GFX1250-NEXT: s_mov_b64 s[10:11], s[6:7]290; GFX1250-NEXT: s_get_pc_i64 s[6:7]291; GFX1250-NEXT: s_add_nc_u64 s[6:7], s[6:7], coldcc@gotpcrel+4292; GFX1250-NEXT: v_dual_mov_b32 v31, v0 :: v_dual_mov_b32 v0, 1.0293; GFX1250-NEXT: s_load_b64 s[12:13], s[6:7], 0x0294; GFX1250-NEXT: s_add_nc_u64 s[8:9], s[4:5], 36295; GFX1250-NEXT: s_mov_b64 s[4:5], s[0:1]296; GFX1250-NEXT: s_wait_xcnt 0x0297; GFX1250-NEXT: s_mov_b64 s[6:7], s[2:3]298; GFX1250-NEXT: s_wait_kmcnt 0x0299; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[12:13]300; GFX1250-NEXT: global_store_b32 v[0:1], v0, off301; GFX1250-NEXT: s_endpgm302 %val = call coldcc float @coldcc(float 1.0)303 store float %val, ptr addrspace(1) poison304 ret void305}306 307define amdgpu_kernel void @call_fastcc() #0 {308; SI-LABEL: call_fastcc:309; SI: ; %bb.0:310; SI-NEXT: s_mov_b32 s32, 0311; SI-NEXT: s_mov_b32 s20, SCRATCH_RSRC_DWORD0312; SI-NEXT: s_mov_b32 s21, SCRATCH_RSRC_DWORD1313; SI-NEXT: s_mov_b32 s22, -1314; SI-NEXT: s_mov_b32 s23, 0xe8f000315; SI-NEXT: s_add_u32 s20, s20, s11316; SI-NEXT: s_addc_u32 s21, s21, 0317; SI-NEXT: s_mov_b32 s14, s10318; SI-NEXT: s_mov_b32 s13, s9319; SI-NEXT: s_mov_b32 s12, s8320; SI-NEXT: s_mov_b64 s[10:11], s[6:7]321; SI-NEXT: s_add_u32 s8, s4, 36322; SI-NEXT: v_lshlrev_b32_e32 v2, 20, v2323; SI-NEXT: s_addc_u32 s9, s5, 0324; SI-NEXT: s_getpc_b64 s[4:5]325; SI-NEXT: s_add_u32 s4, s4, fastcc@gotpcrel32@lo+4326; SI-NEXT: s_addc_u32 s5, s5, fastcc@gotpcrel32@hi+12327; SI-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0328; SI-NEXT: v_lshlrev_b32_e32 v1, 10, v1329; SI-NEXT: v_or_b32_e32 v0, v0, v1330; SI-NEXT: v_or_b32_e32 v31, v0, v2331; SI-NEXT: v_mov_b32_e32 v0, 1.0332; SI-NEXT: s_mov_b64 s[4:5], s[0:1]333; SI-NEXT: s_mov_b64 s[6:7], s[2:3]334; SI-NEXT: s_mov_b64 s[0:1], s[20:21]335; SI-NEXT: s_mov_b64 s[2:3], s[22:23]336; SI-NEXT: s_waitcnt lgkmcnt(0)337; SI-NEXT: s_swappc_b64 s[30:31], s[16:17]338; SI-NEXT: s_mov_b32 s3, 0xf000339; SI-NEXT: s_mov_b32 s2, -1340; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0341; SI-NEXT: s_endpgm342;343; VI-LABEL: call_fastcc:344; VI: ; %bb.0:345; VI-NEXT: s_mov_b32 s88, SCRATCH_RSRC_DWORD0346; VI-NEXT: s_mov_b32 s89, SCRATCH_RSRC_DWORD1347; VI-NEXT: s_mov_b32 s90, -1348; VI-NEXT: s_mov_b32 s91, 0xe80000349; VI-NEXT: s_add_u32 s88, s88, s11350; VI-NEXT: s_addc_u32 s89, s89, 0351; VI-NEXT: s_mov_b32 s12, s8352; VI-NEXT: s_add_u32 s8, s4, 36353; VI-NEXT: s_mov_b32 s13, s9354; VI-NEXT: s_addc_u32 s9, s5, 0355; VI-NEXT: s_getpc_b64 s[4:5]356; VI-NEXT: s_add_u32 s4, s4, fastcc@gotpcrel32@lo+4357; VI-NEXT: s_addc_u32 s5, s5, fastcc@gotpcrel32@hi+12358; VI-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0359; VI-NEXT: v_lshlrev_b32_e32 v1, 10, v1360; VI-NEXT: s_mov_b32 s14, s10361; VI-NEXT: s_mov_b64 s[10:11], s[6:7]362; VI-NEXT: v_lshlrev_b32_e32 v2, 20, v2363; VI-NEXT: v_or_b32_e32 v0, v0, v1364; VI-NEXT: s_mov_b64 s[4:5], s[0:1]365; VI-NEXT: s_mov_b64 s[6:7], s[2:3]366; VI-NEXT: s_mov_b64 s[0:1], s[88:89]367; VI-NEXT: v_or_b32_e32 v31, v0, v2368; VI-NEXT: s_mov_b64 s[2:3], s[90:91]369; VI-NEXT: v_mov_b32_e32 v0, 1.0370; VI-NEXT: s_mov_b32 s32, 0371; VI-NEXT: s_waitcnt lgkmcnt(0)372; VI-NEXT: s_swappc_b64 s[30:31], s[16:17]373; VI-NEXT: flat_store_dword v[0:1], v0374; VI-NEXT: s_endpgm375;376; GFX11-LABEL: call_fastcc:377; GFX11: ; %bb.0:378; GFX11-NEXT: s_add_u32 s8, s4, 36379; GFX11-NEXT: s_addc_u32 s9, s5, 0380; GFX11-NEXT: s_getpc_b64 s[4:5]381; GFX11-NEXT: s_add_u32 s4, s4, fastcc@gotpcrel32@lo+4382; GFX11-NEXT: s_addc_u32 s5, s5, fastcc@gotpcrel32@hi+12383; GFX11-NEXT: v_dual_mov_b32 v31, v0 :: v_dual_mov_b32 v0, 1.0384; GFX11-NEXT: s_load_b64 s[16:17], s[4:5], 0x0385; GFX11-NEXT: s_mov_b32 s12, s13386; GFX11-NEXT: s_mov_b64 s[10:11], s[6:7]387; GFX11-NEXT: s_mov_b64 s[4:5], s[0:1]388; GFX11-NEXT: s_mov_b64 s[6:7], s[2:3]389; GFX11-NEXT: s_mov_b32 s13, s14390; GFX11-NEXT: s_mov_b32 s14, s15391; GFX11-NEXT: s_mov_b32 s32, 0392; GFX11-NEXT: s_waitcnt lgkmcnt(0)393; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17]394; GFX11-NEXT: global_store_b32 v[0:1], v0, off395; GFX11-NEXT: s_endpgm396;397; GFX1250-LABEL: call_fastcc:398; GFX1250: ; %bb.0:399; GFX1250-NEXT: s_mov_b32 s32, 0400; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1401; GFX1250-NEXT: s_mov_b64 s[10:11], s[6:7]402; GFX1250-NEXT: s_get_pc_i64 s[6:7]403; GFX1250-NEXT: s_add_nc_u64 s[6:7], s[6:7], fastcc@gotpcrel+4404; GFX1250-NEXT: v_dual_mov_b32 v31, v0 :: v_dual_mov_b32 v0, 1.0405; GFX1250-NEXT: s_load_b64 s[12:13], s[6:7], 0x0406; GFX1250-NEXT: s_add_nc_u64 s[8:9], s[4:5], 36407; GFX1250-NEXT: s_mov_b64 s[4:5], s[0:1]408; GFX1250-NEXT: s_wait_xcnt 0x0409; GFX1250-NEXT: s_mov_b64 s[6:7], s[2:3]410; GFX1250-NEXT: s_wait_kmcnt 0x0411; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[12:13]412; GFX1250-NEXT: global_store_b32 v[0:1], v0, off413; GFX1250-NEXT: s_endpgm414 %val = call fastcc float @fastcc(float 1.0)415 store float %val, ptr addrspace(1) poison416 ret void417}418 419; Mesa compute shader: check for 47176 (COMPUTE_PGM_RSRC1) in .AMDGPU.config420define amdgpu_cs half @cs_mesa(half %arg0) {421; SI-LABEL: cs_mesa:422; SI: ; %bb.0:423; SI-NEXT: v_cvt_f16_f32_e32 v0, v0424; SI-NEXT: v_cvt_f32_f16_e32 v0, v0425; SI-NEXT: v_add_f32_e32 v0, 1.0, v0426; SI-NEXT: ; return to shader part epilog427;428; VI-LABEL: cs_mesa:429; VI: ; %bb.0:430; VI-NEXT: v_add_f16_e32 v0, 1.0, v0431; VI-NEXT: ; return to shader part epilog432;433; GFX11-TRUE16-LABEL: cs_mesa:434; GFX11-TRUE16: ; %bb.0:435; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l436; GFX11-TRUE16-NEXT: ; return to shader part epilog437;438; GFX11-FAKE16-LABEL: cs_mesa:439; GFX11-FAKE16: ; %bb.0:440; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0441; GFX11-FAKE16-NEXT: ; return to shader part epilog442;443; GFX1250-TRUE16-LABEL: cs_mesa:444; GFX1250-TRUE16: ; %bb.0:445; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1446; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0447; GFX1250-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l448; GFX1250-TRUE16-NEXT: ; return to shader part epilog449;450; GFX1250-FAKE16-LABEL: cs_mesa:451; GFX1250-FAKE16: ; %bb.0:452; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1453; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0454; GFX1250-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0455; GFX1250-FAKE16-NEXT: ; return to shader part epilog456 %add = fadd half %arg0, 1.0457 ret half %add458}459 460; Mesa pixel shader: check for 45096 (SPI_SHADER_PGM_RSRC1_PS) in .AMDGPU.config461define amdgpu_ps half @ps_mesa_f16(half %arg0) {462; SI-LABEL: ps_mesa_f16:463; SI: ; %bb.0:464; SI-NEXT: v_cvt_f16_f32_e32 v0, v0465; SI-NEXT: v_cvt_f32_f16_e32 v0, v0466; SI-NEXT: v_add_f32_e32 v0, 1.0, v0467; SI-NEXT: ; return to shader part epilog468;469; VI-LABEL: ps_mesa_f16:470; VI: ; %bb.0:471; VI-NEXT: v_add_f16_e32 v0, 1.0, v0472; VI-NEXT: ; return to shader part epilog473;474; GFX11-TRUE16-LABEL: ps_mesa_f16:475; GFX11-TRUE16: ; %bb.0:476; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l477; GFX11-TRUE16-NEXT: ; return to shader part epilog478;479; GFX11-FAKE16-LABEL: ps_mesa_f16:480; GFX11-FAKE16: ; %bb.0:481; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0482; GFX11-FAKE16-NEXT: ; return to shader part epilog483;484; GFX1250-TRUE16-LABEL: ps_mesa_f16:485; GFX1250-TRUE16: ; %bb.0:486; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1487; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0488; GFX1250-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l489; GFX1250-TRUE16-NEXT: ; return to shader part epilog490;491; GFX1250-FAKE16-LABEL: ps_mesa_f16:492; GFX1250-FAKE16: ; %bb.0:493; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1494; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0495; GFX1250-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0496; GFX1250-FAKE16-NEXT: ; return to shader part epilog497 %add = fadd half %arg0, 1.0498 ret half %add499}500 501; Mesa vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in .AMDGPU.config502define amdgpu_vs half @vs_mesa(half %arg0) {503; SI-LABEL: vs_mesa:504; SI: ; %bb.0:505; SI-NEXT: v_cvt_f16_f32_e32 v0, v0506; SI-NEXT: v_cvt_f32_f16_e32 v0, v0507; SI-NEXT: v_add_f32_e32 v0, 1.0, v0508; SI-NEXT: ; return to shader part epilog509;510; VI-LABEL: vs_mesa:511; VI: ; %bb.0:512; VI-NEXT: v_add_f16_e32 v0, 1.0, v0513; VI-NEXT: ; return to shader part epilog514;515; GFX11-TRUE16-LABEL: vs_mesa:516; GFX11-TRUE16: ; %bb.0:517; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l518; GFX11-TRUE16-NEXT: ; return to shader part epilog519;520; GFX11-FAKE16-LABEL: vs_mesa:521; GFX11-FAKE16: ; %bb.0:522; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0523; GFX11-FAKE16-NEXT: ; return to shader part epilog524;525; GFX1250-TRUE16-LABEL: vs_mesa:526; GFX1250-TRUE16: ; %bb.0:527; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1528; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0529; GFX1250-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l530; GFX1250-TRUE16-NEXT: ; return to shader part epilog531;532; GFX1250-FAKE16-LABEL: vs_mesa:533; GFX1250-FAKE16: ; %bb.0:534; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1535; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0536; GFX1250-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0537; GFX1250-FAKE16-NEXT: ; return to shader part epilog538 %add = fadd half %arg0, 1.0539 ret half %add540}541 542; Mesa geometry shader: check for 45608 (SPI_SHADER_PGM_RSRC1_GS) in .AMDGPU.config543define amdgpu_gs half @gs_mesa(half %arg0) {544; SI-LABEL: gs_mesa:545; SI: ; %bb.0:546; SI-NEXT: v_cvt_f16_f32_e32 v0, v0547; SI-NEXT: v_cvt_f32_f16_e32 v0, v0548; SI-NEXT: v_add_f32_e32 v0, 1.0, v0549; SI-NEXT: ; return to shader part epilog550;551; VI-LABEL: gs_mesa:552; VI: ; %bb.0:553; VI-NEXT: v_add_f16_e32 v0, 1.0, v0554; VI-NEXT: ; return to shader part epilog555;556; GFX11-TRUE16-LABEL: gs_mesa:557; GFX11-TRUE16: ; %bb.0:558; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l559; GFX11-TRUE16-NEXT: ; return to shader part epilog560;561; GFX11-FAKE16-LABEL: gs_mesa:562; GFX11-FAKE16: ; %bb.0:563; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0564; GFX11-FAKE16-NEXT: ; return to shader part epilog565;566; GFX1250-TRUE16-LABEL: gs_mesa:567; GFX1250-TRUE16: ; %bb.0:568; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1569; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0570; GFX1250-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l571; GFX1250-TRUE16-NEXT: ; return to shader part epilog572;573; GFX1250-FAKE16-LABEL: gs_mesa:574; GFX1250-FAKE16: ; %bb.0:575; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1576; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0577; GFX1250-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0578; GFX1250-FAKE16-NEXT: ; return to shader part epilog579 %add = fadd half %arg0, 1.0580 ret half %add581}582 583; Mesa hull shader: check for 46120 (SPI_SHADER_PGM_RSRC1_HS) in .AMDGPU.config584define amdgpu_hs half @hs_mesa(half %arg0) {585; SI-LABEL: hs_mesa:586; SI: ; %bb.0:587; SI-NEXT: v_cvt_f16_f32_e32 v0, v0588; SI-NEXT: v_cvt_f32_f16_e32 v0, v0589; SI-NEXT: v_add_f32_e32 v0, 1.0, v0590; SI-NEXT: ; return to shader part epilog591;592; VI-LABEL: hs_mesa:593; VI: ; %bb.0:594; VI-NEXT: v_add_f16_e32 v0, 1.0, v0595; VI-NEXT: ; return to shader part epilog596;597; GFX11-TRUE16-LABEL: hs_mesa:598; GFX11-TRUE16: ; %bb.0:599; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l600; GFX11-TRUE16-NEXT: ; return to shader part epilog601;602; GFX11-FAKE16-LABEL: hs_mesa:603; GFX11-FAKE16: ; %bb.0:604; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0605; GFX11-FAKE16-NEXT: ; return to shader part epilog606;607; GFX1250-TRUE16-LABEL: hs_mesa:608; GFX1250-TRUE16: ; %bb.0:609; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1610; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0611; GFX1250-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l612; GFX1250-TRUE16-NEXT: ; return to shader part epilog613;614; GFX1250-FAKE16-LABEL: hs_mesa:615; GFX1250-FAKE16: ; %bb.0:616; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1617; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0618; GFX1250-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0619; GFX1250-FAKE16-NEXT: ; return to shader part epilog620 %add = fadd half %arg0, 1.0621 ret half %add622}623 624; FIXME: Inconsistent ABI between targets625 626define amdgpu_ps <2 x half> @ps_mesa_v2f16(<2 x half> %arg0) {627; SI-LABEL: ps_mesa_v2f16:628; SI: ; %bb.0:629; SI-NEXT: v_cvt_f16_f32_e32 v1, v1630; SI-NEXT: v_cvt_f16_f32_e32 v0, v0631; SI-NEXT: v_cvt_f32_f16_e32 v1, v1632; SI-NEXT: v_cvt_f32_f16_e32 v0, v0633; SI-NEXT: v_add_f32_e32 v0, 1.0, v0634; SI-NEXT: v_add_f32_e32 v1, 1.0, v1635; SI-NEXT: ; return to shader part epilog636;637; VI-LABEL: ps_mesa_v2f16:638; VI: ; %bb.0:639; VI-NEXT: v_mov_b32_e32 v1, 0x3c00640; VI-NEXT: v_add_f16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD641; VI-NEXT: v_add_f16_e32 v0, 1.0, v0642; VI-NEXT: v_or_b32_e32 v0, v0, v1643; VI-NEXT: ; return to shader part epilog644;645; GFX11-LABEL: ps_mesa_v2f16:646; GFX11: ; %bb.0:647; GFX11-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]648; GFX11-NEXT: ; return to shader part epilog649;650; GFX1250-LABEL: ps_mesa_v2f16:651; GFX1250: ; %bb.0:652; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1653; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0654; GFX1250-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]655; GFX1250-NEXT: ; return to shader part epilog656 %add = fadd <2 x half> %arg0, <half 1.0, half 1.0>657 ret <2 x half> %add658}659 660define amdgpu_ps <2 x half> @ps_mesa_inreg_v2f16(<2 x half> inreg %arg0) {661; SI-LABEL: ps_mesa_inreg_v2f16:662; SI: ; %bb.0:663; SI-NEXT: v_cvt_f16_f32_e32 v0, s1664; SI-NEXT: v_cvt_f16_f32_e32 v1, s0665; SI-NEXT: v_cvt_f32_f16_e32 v2, v0666; SI-NEXT: v_cvt_f32_f16_e32 v0, v1667; SI-NEXT: v_add_f32_e32 v0, 1.0, v0668; SI-NEXT: v_add_f32_e32 v1, 1.0, v2669; SI-NEXT: ; return to shader part epilog670;671; VI-LABEL: ps_mesa_inreg_v2f16:672; VI: ; %bb.0:673; VI-NEXT: s_lshr_b32 s1, s0, 16674; VI-NEXT: v_mov_b32_e32 v0, s1675; VI-NEXT: v_mov_b32_e32 v1, 0x3c00676; VI-NEXT: v_add_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD677; VI-NEXT: v_add_f16_e64 v1, s0, 1.0678; VI-NEXT: v_or_b32_e32 v0, v1, v0679; VI-NEXT: ; return to shader part epilog680;681; GFX11-LABEL: ps_mesa_inreg_v2f16:682; GFX11: ; %bb.0:683; GFX11-NEXT: v_pk_add_f16 v0, s0, 1.0 op_sel_hi:[1,0]684; GFX11-NEXT: ; return to shader part epilog685;686; GFX1250-LABEL: ps_mesa_inreg_v2f16:687; GFX1250: ; %bb.0:688; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1689; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0690; GFX1250-NEXT: v_pk_add_f16 v0, s0, 1.0 op_sel_hi:[1,0]691; GFX1250-NEXT: ; return to shader part epilog692 %add = fadd <2 x half> %arg0, <half 1.0, half 1.0>693 ret <2 x half> %add694}695 696define amdgpu_ps void @ps_mesa_v2i16(<2 x i16> %arg0) {697; SI-LABEL: ps_mesa_v2i16:698; SI: ; %bb.0:699; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1700; SI-NEXT: v_add_i32_e32 v0, vcc, 1, v0701; SI-NEXT: s_mov_b32 s3, 0xf000702; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0703; SI-NEXT: v_or_b32_e32 v0, v1, v0704; SI-NEXT: v_add_i32_e32 v0, vcc, 0x10000, v0705; SI-NEXT: s_mov_b32 s2, -1706; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0707; SI-NEXT: s_endpgm708;709; VI-LABEL: ps_mesa_v2i16:710; VI: ; %bb.0:711; VI-NEXT: v_mov_b32_e32 v2, 1712; VI-NEXT: v_add_u16_e32 v1, 1, v0713; VI-NEXT: v_add_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD714; VI-NEXT: v_or_b32_e32 v0, v1, v0715; VI-NEXT: flat_store_dword v[0:1], v0716; VI-NEXT: s_endpgm717;718; GFX11-LABEL: ps_mesa_v2i16:719; GFX11: ; %bb.0:720; GFX11-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0]721; GFX11-NEXT: global_store_b32 v[0:1], v0, off722; GFX11-NEXT: s_endpgm723;724; GFX1250-LABEL: ps_mesa_v2i16:725; GFX1250: ; %bb.0:726; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1727; GFX1250-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0]728; GFX1250-NEXT: global_store_b32 v[0:1], v0, off729; GFX1250-NEXT: s_endpgm730 %add = add <2 x i16> %arg0, <i16 1, i16 1>731 store <2 x i16> %add, ptr addrspace(1) poison732 ret void733}734 735define amdgpu_ps void @ps_mesa_inreg_v2i16(<2 x i16> inreg %arg0) {736; SI-LABEL: ps_mesa_inreg_v2i16:737; SI: ; %bb.0:738; SI-NEXT: s_lshl_b32 s1, s1, 16739; SI-NEXT: s_add_i32 s0, s0, 1740; SI-NEXT: s_mov_b32 s3, 0xf000741; SI-NEXT: s_and_b32 s0, s0, 0xffff742; SI-NEXT: s_or_b32 s0, s1, s0743; SI-NEXT: s_add_i32 s0, s0, 0x10000744; SI-NEXT: s_mov_b32 s2, -1745; SI-NEXT: v_mov_b32_e32 v0, s0746; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0747; SI-NEXT: s_endpgm748;749; VI-LABEL: ps_mesa_inreg_v2i16:750; VI: ; %bb.0:751; VI-NEXT: s_and_b32 s1, s0, 0xffff0000752; VI-NEXT: s_add_i32 s0, s0, 1753; VI-NEXT: s_and_b32 s0, s0, 0xffff754; VI-NEXT: s_or_b32 s0, s1, s0755; VI-NEXT: s_add_i32 s0, s0, 0x10000756; VI-NEXT: v_mov_b32_e32 v0, s0757; VI-NEXT: flat_store_dword v[0:1], v0758; VI-NEXT: s_endpgm759;760; GFX11-LABEL: ps_mesa_inreg_v2i16:761; GFX11: ; %bb.0:762; GFX11-NEXT: v_pk_add_u16 v0, s0, 1 op_sel_hi:[1,0]763; GFX11-NEXT: global_store_b32 v[0:1], v0, off764; GFX11-NEXT: s_endpgm765;766; GFX1250-LABEL: ps_mesa_inreg_v2i16:767; GFX1250: ; %bb.0:768; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1769; GFX1250-NEXT: v_pk_add_u16 v0, s0, 1 op_sel_hi:[1,0]770; GFX1250-NEXT: global_store_b32 v[0:1], v0, off771; GFX1250-NEXT: s_endpgm772 %add = add <2 x i16> %arg0, <i16 1, i16 1>773 store <2 x i16> %add, ptr addrspace(1) poison774 ret void775}776 777; FIXME: Differenet ABI for VI+778 779define amdgpu_ps <4 x half> @ps_mesa_v4f16(<4 x half> %arg0) {780; SI-LABEL: ps_mesa_v4f16:781; SI: ; %bb.0:782; SI-NEXT: v_cvt_f16_f32_e32 v3, v3783; SI-NEXT: v_cvt_f16_f32_e32 v2, v2784; SI-NEXT: v_cvt_f16_f32_e32 v1, v1785; SI-NEXT: v_cvt_f16_f32_e32 v0, v0786; SI-NEXT: v_cvt_f32_f16_e32 v3, v3787; SI-NEXT: v_cvt_f32_f16_e32 v2, v2788; SI-NEXT: v_cvt_f32_f16_e32 v1, v1789; SI-NEXT: v_cvt_f32_f16_e32 v0, v0790; SI-NEXT: v_add_f32_e32 v0, 1.0, v0791; SI-NEXT: v_add_f32_e32 v1, 1.0, v1792; SI-NEXT: v_add_f32_e32 v2, 1.0, v2793; SI-NEXT: v_add_f32_e32 v3, 1.0, v3794; SI-NEXT: ; return to shader part epilog795;796; VI-LABEL: ps_mesa_v4f16:797; VI: ; %bb.0:798; VI-NEXT: v_mov_b32_e32 v3, 0x3c00799; VI-NEXT: v_add_f16_e32 v2, 1.0, v1800; VI-NEXT: v_add_f16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD801; VI-NEXT: v_add_f16_e32 v4, 1.0, v0802; VI-NEXT: v_add_f16_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD803; VI-NEXT: v_or_b32_e32 v0, v4, v0804; VI-NEXT: v_or_b32_e32 v1, v2, v1805; VI-NEXT: ; return to shader part epilog806;807; GFX11-LABEL: ps_mesa_v4f16:808; GFX11: ; %bb.0:809; GFX11-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]810; GFX11-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0]811; GFX11-NEXT: ; return to shader part epilog812;813; GFX1250-LABEL: ps_mesa_v4f16:814; GFX1250: ; %bb.0:815; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1816; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0817; GFX1250-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]818; GFX1250-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0]819; GFX1250-NEXT: ; return to shader part epilog820 %add = fadd <4 x half> %arg0, <half 1.0, half 1.0, half 1.0, half 1.0>821 ret <4 x half> %add822}823 824define amdgpu_ps <4 x half> @ps_mesa_inreg_v4f16(<4 x half> inreg %arg0) {825; SI-LABEL: ps_mesa_inreg_v4f16:826; SI: ; %bb.0:827; SI-NEXT: v_cvt_f16_f32_e32 v0, s3828; SI-NEXT: v_cvt_f16_f32_e32 v1, s2829; SI-NEXT: v_cvt_f16_f32_e32 v2, s1830; SI-NEXT: v_cvt_f16_f32_e32 v3, s0831; SI-NEXT: v_cvt_f32_f16_e32 v4, v0832; SI-NEXT: v_cvt_f32_f16_e32 v5, v1833; SI-NEXT: v_cvt_f32_f16_e32 v1, v2834; SI-NEXT: v_cvt_f32_f16_e32 v0, v3835; SI-NEXT: v_add_f32_e32 v0, 1.0, v0836; SI-NEXT: v_add_f32_e32 v1, 1.0, v1837; SI-NEXT: v_add_f32_e32 v2, 1.0, v5838; SI-NEXT: v_add_f32_e32 v3, 1.0, v4839; SI-NEXT: ; return to shader part epilog840;841; VI-LABEL: ps_mesa_inreg_v4f16:842; VI: ; %bb.0:843; VI-NEXT: v_add_f16_e64 v1, s1, 1.0844; VI-NEXT: s_lshr_b32 s1, s1, 16845; VI-NEXT: v_mov_b32_e32 v0, s1846; VI-NEXT: v_mov_b32_e32 v2, 0x3c00847; VI-NEXT: v_add_f16_sdwa v3, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD848; VI-NEXT: v_add_f16_e64 v0, s0, 1.0849; VI-NEXT: s_lshr_b32 s0, s0, 16850; VI-NEXT: v_mov_b32_e32 v4, s0851; VI-NEXT: v_add_f16_sdwa v2, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD852; VI-NEXT: v_or_b32_e32 v0, v0, v2853; VI-NEXT: v_or_b32_e32 v1, v1, v3854; VI-NEXT: ; return to shader part epilog855;856; GFX11-LABEL: ps_mesa_inreg_v4f16:857; GFX11: ; %bb.0:858; GFX11-NEXT: v_pk_add_f16 v0, s0, 1.0 op_sel_hi:[1,0]859; GFX11-NEXT: v_pk_add_f16 v1, s1, 1.0 op_sel_hi:[1,0]860; GFX11-NEXT: ; return to shader part epilog861;862; GFX1250-LABEL: ps_mesa_inreg_v4f16:863; GFX1250: ; %bb.0:864; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1865; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0866; GFX1250-NEXT: v_pk_add_f16 v0, s0, 1.0 op_sel_hi:[1,0]867; GFX1250-NEXT: v_pk_add_f16 v1, s1, 1.0 op_sel_hi:[1,0]868; GFX1250-NEXT: ; return to shader part epilog869 %add = fadd <4 x half> %arg0, <half 1.0, half 1.0, half 1.0, half 1.0>870 ret <4 x half> %add871}872 873define amdgpu_ps void @ps_mesa_inreg_v3i32(<3 x i32> inreg %arg0) {874; SI-LABEL: ps_mesa_inreg_v3i32:875; SI: ; %bb.0:876; SI-NEXT: s_add_i32 s1, s1, 2877; SI-NEXT: s_add_i32 s0, s0, 1878; SI-NEXT: s_add_i32 s4, s2, 3879; SI-NEXT: s_mov_b32 s3, 0xf000880; SI-NEXT: s_mov_b32 s2, -1881; SI-NEXT: v_mov_b32_e32 v0, s4882; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0883; SI-NEXT: s_waitcnt expcnt(0)884; SI-NEXT: v_mov_b32_e32 v0, s0885; SI-NEXT: v_mov_b32_e32 v1, s1886; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0887; SI-NEXT: s_endpgm888;889; VI-LABEL: ps_mesa_inreg_v3i32:890; VI: ; %bb.0:891; VI-NEXT: s_add_i32 s2, s2, 3892; VI-NEXT: s_add_i32 s1, s1, 2893; VI-NEXT: s_add_i32 s0, s0, 1894; VI-NEXT: v_mov_b32_e32 v0, s0895; VI-NEXT: v_mov_b32_e32 v1, s1896; VI-NEXT: v_mov_b32_e32 v2, s2897; VI-NEXT: flat_store_dwordx3 v[0:1], v[0:2]898; VI-NEXT: s_endpgm899;900; GFX11-LABEL: ps_mesa_inreg_v3i32:901; GFX11: ; %bb.0:902; GFX11-NEXT: s_add_i32 s2, s2, 3903; GFX11-NEXT: s_add_i32 s0, s0, 1904; GFX11-NEXT: s_add_i32 s1, s1, 2905; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)906; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1907; GFX11-NEXT: v_mov_b32_e32 v2, s2908; GFX11-NEXT: global_store_b96 v[0:1], v[0:2], off909; GFX11-NEXT: s_endpgm910;911; GFX1250-LABEL: ps_mesa_inreg_v3i32:912; GFX1250: ; %bb.0:913; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1914; GFX1250-NEXT: s_add_co_i32 s2, s2, 3915; GFX1250-NEXT: s_add_co_i32 s0, s0, 1916; GFX1250-NEXT: s_add_co_i32 s1, s1, 2917; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)918; GFX1250-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1919; GFX1250-NEXT: v_mov_b32_e32 v2, s2920; GFX1250-NEXT: global_store_b96 v[0:1], v[0:2], off921; GFX1250-NEXT: s_endpgm922 %add = add <3 x i32> %arg0, <i32 1, i32 2, i32 3>923 store <3 x i32> %add, ptr addrspace(1) poison924 ret void925}926 927define amdgpu_ps void @ps_mesa_inreg_v3f32(<3 x float> inreg %arg0) {928; SI-LABEL: ps_mesa_inreg_v3f32:929; SI: ; %bb.0:930; SI-NEXT: v_add_f32_e64 v1, s1, 2.0931; SI-NEXT: v_add_f32_e64 v0, s0, 1.0932; SI-NEXT: v_add_f32_e64 v2, s2, 4.0933; SI-NEXT: s_mov_b32 s3, 0xf000934; SI-NEXT: s_mov_b32 s2, -1935; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0936; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0937; SI-NEXT: s_endpgm938;939; VI-LABEL: ps_mesa_inreg_v3f32:940; VI: ; %bb.0:941; VI-NEXT: v_add_f32_e64 v2, s2, 4.0942; VI-NEXT: v_add_f32_e64 v1, s1, 2.0943; VI-NEXT: v_add_f32_e64 v0, s0, 1.0944; VI-NEXT: flat_store_dwordx3 v[0:1], v[0:2]945; VI-NEXT: s_endpgm946;947; GFX11-LABEL: ps_mesa_inreg_v3f32:948; GFX11: ; %bb.0:949; GFX11-NEXT: v_add_f32_e64 v2, s2, 4.0950; GFX11-NEXT: v_add_f32_e64 v1, s1, 2.0951; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.0952; GFX11-NEXT: global_store_b96 v[0:1], v[0:2], off953; GFX11-NEXT: s_endpgm954;955; GFX1250-LABEL: ps_mesa_inreg_v3f32:956; GFX1250: ; %bb.0:957; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1958; GFX1250-NEXT: s_add_f32 s0, s0, 1.0959; GFX1250-NEXT: s_add_f32 s1, s1, 2.0960; GFX1250-NEXT: s_add_f32 s2, s2, 4.0961; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(NEXT) | instid1(SALU_CYCLE_2)962; GFX1250-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1963; GFX1250-NEXT: v_mov_b32_e32 v2, s2964; GFX1250-NEXT: global_store_b96 v[0:1], v[0:2], off965; GFX1250-NEXT: s_endpgm966 %add = fadd <3 x float> %arg0, <float 1.0, float 2.0, float 4.0>967 store <3 x float> %add, ptr addrspace(1) poison968 ret void969}970 971define amdgpu_ps void @ps_mesa_inreg_v5i32(<5 x i32> inreg %arg0) {972; SI-LABEL: ps_mesa_inreg_v5i32:973; SI: ; %bb.0:974; SI-NEXT: s_add_i32 s5, s3, 4975; SI-NEXT: s_add_i32 s6, s2, 3976; SI-NEXT: s_add_i32 s1, s1, 2977; SI-NEXT: s_add_i32 s0, s0, 1978; SI-NEXT: s_add_i32 s4, s4, 5979; SI-NEXT: s_mov_b32 s3, 0xf000980; SI-NEXT: s_mov_b32 s2, -1981; SI-NEXT: v_mov_b32_e32 v0, s4982; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0983; SI-NEXT: s_waitcnt expcnt(0)984; SI-NEXT: v_mov_b32_e32 v0, s0985; SI-NEXT: v_mov_b32_e32 v1, s1986; SI-NEXT: v_mov_b32_e32 v2, s6987; SI-NEXT: v_mov_b32_e32 v3, s5988; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0989; SI-NEXT: s_endpgm990;991; VI-LABEL: ps_mesa_inreg_v5i32:992; VI: ; %bb.0:993; VI-NEXT: s_add_i32 s4, s4, 5994; VI-NEXT: s_add_i32 s3, s3, 4995; VI-NEXT: s_add_i32 s2, s2, 3996; VI-NEXT: s_add_i32 s1, s1, 2997; VI-NEXT: s_add_i32 s0, s0, 1998; VI-NEXT: v_mov_b32_e32 v0, s4999; VI-NEXT: flat_store_dword v[0:1], v01000; VI-NEXT: v_mov_b32_e32 v0, s01001; VI-NEXT: v_mov_b32_e32 v1, s11002; VI-NEXT: v_mov_b32_e32 v2, s21003; VI-NEXT: v_mov_b32_e32 v3, s31004; VI-NEXT: flat_store_dwordx4 v[0:1], v[0:3]1005; VI-NEXT: s_endpgm1006;1007; GFX11-LABEL: ps_mesa_inreg_v5i32:1008; GFX11: ; %bb.0:1009; GFX11-NEXT: s_add_i32 s3, s3, 41010; GFX11-NEXT: s_add_i32 s2, s2, 31011; GFX11-NEXT: s_add_i32 s1, s1, 21012; GFX11-NEXT: s_add_i32 s4, s4, 51013; GFX11-NEXT: s_add_i32 s0, s0, 11014; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v1, s11015; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s31016; GFX11-NEXT: v_mov_b32_e32 v2, s21017; GFX11-NEXT: s_clause 0x11018; GFX11-NEXT: global_store_b32 v[0:1], v4, off1019; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off1020; GFX11-NEXT: s_endpgm1021;1022; GFX1250-LABEL: ps_mesa_inreg_v5i32:1023; GFX1250: ; %bb.0:1024; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11025; GFX1250-NEXT: s_add_co_i32 s3, s3, 41026; GFX1250-NEXT: s_add_co_i32 s2, s2, 31027; GFX1250-NEXT: s_add_co_i32 s1, s1, 21028; GFX1250-NEXT: s_add_co_i32 s4, s4, 51029; GFX1250-NEXT: s_add_co_i32 s0, s0, 11030; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1031; GFX1250-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v0, s01032; GFX1250-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s21033; GFX1250-NEXT: v_mov_b32_e32 v3, s31034; GFX1250-NEXT: s_clause 0x11035; GFX1250-NEXT: global_store_b32 v[0:1], v4, off1036; GFX1250-NEXT: global_store_b128 v[0:1], v[0:3], off1037; GFX1250-NEXT: s_endpgm1038 %add = add <5 x i32> %arg0, <i32 1, i32 2, i32 3, i32 4, i32 5>1039 store <5 x i32> %add, ptr addrspace(1) poison1040 ret void1041}1042 1043define amdgpu_ps void @ps_mesa_inreg_v5f32(<5 x float> inreg %arg0) {1044; SI-LABEL: ps_mesa_inreg_v5f32:1045; SI: ; %bb.0:1046; SI-NEXT: v_add_f32_e64 v3, s3, -1.01047; SI-NEXT: v_add_f32_e64 v2, s2, 4.01048; SI-NEXT: v_add_f32_e64 v1, s1, 2.01049; SI-NEXT: v_add_f32_e64 v0, s0, 1.01050; SI-NEXT: v_add_f32_e64 v4, s4, 0.51051; SI-NEXT: s_mov_b32 s3, 0xf0001052; SI-NEXT: s_mov_b32 s2, -11053; SI-NEXT: buffer_store_dword v4, off, s[0:3], 01054; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 01055; SI-NEXT: s_endpgm1056;1057; VI-LABEL: ps_mesa_inreg_v5f32:1058; VI: ; %bb.0:1059; VI-NEXT: v_add_f32_e64 v3, s3, -1.01060; VI-NEXT: v_add_f32_e64 v2, s2, 4.01061; VI-NEXT: v_add_f32_e64 v1, s1, 2.01062; VI-NEXT: v_add_f32_e64 v0, s0, 1.01063; VI-NEXT: v_add_f32_e64 v4, s4, 0.51064; VI-NEXT: flat_store_dword v[0:1], v41065; VI-NEXT: flat_store_dwordx4 v[0:1], v[0:3]1066; VI-NEXT: s_endpgm1067;1068; GFX11-LABEL: ps_mesa_inreg_v5f32:1069; GFX11: ; %bb.0:1070; GFX11-NEXT: v_add_f32_e64 v3, s3, -1.01071; GFX11-NEXT: v_add_f32_e64 v2, s2, 4.01072; GFX11-NEXT: v_add_f32_e64 v1, s1, 2.01073; GFX11-NEXT: v_add_f32_e64 v4, s4, 0.51074; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.01075; GFX11-NEXT: s_clause 0x11076; GFX11-NEXT: global_store_b32 v[0:1], v4, off1077; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off1078; GFX11-NEXT: s_endpgm1079;1080; GFX1250-LABEL: ps_mesa_inreg_v5f32:1081; GFX1250: ; %bb.0:1082; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11083; GFX1250-NEXT: s_add_f32 s3, s3, -1.01084; GFX1250-NEXT: s_add_f32 s4, s4, 0.51085; GFX1250-NEXT: s_add_f32 s0, s0, 1.01086; GFX1250-NEXT: s_add_f32 s1, s1, 2.01087; GFX1250-NEXT: s_add_f32 s2, s2, 4.01088; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_2)1089; GFX1250-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v0, s01090; GFX1250-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s21091; GFX1250-NEXT: v_mov_b32_e32 v3, s31092; GFX1250-NEXT: s_clause 0x11093; GFX1250-NEXT: global_store_b32 v[0:1], v4, off1094; GFX1250-NEXT: global_store_b128 v[0:1], v[0:3], off1095; GFX1250-NEXT: s_endpgm1096 %add = fadd <5 x float> %arg0, <float 1.0, float 2.0, float 4.0, float -1.0, float 0.5>1097 store <5 x float> %add, ptr addrspace(1) poison1098 ret void1099}1100 1101define amdgpu_ps void @ps_mesa_v3i32(<3 x i32> %arg0) {1102; SI-LABEL: ps_mesa_v3i32:1103; SI: ; %bb.0:1104; SI-NEXT: v_add_i32_e32 v1, vcc, 2, v11105; SI-NEXT: v_add_i32_e32 v0, vcc, 1, v01106; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v21107; SI-NEXT: s_mov_b32 s3, 0xf0001108; SI-NEXT: s_mov_b32 s2, -11109; SI-NEXT: buffer_store_dword v2, off, s[0:3], 01110; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01111; SI-NEXT: s_endpgm1112;1113; VI-LABEL: ps_mesa_v3i32:1114; VI: ; %bb.0:1115; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v21116; VI-NEXT: v_add_u32_e32 v1, vcc, 2, v11117; VI-NEXT: v_add_u32_e32 v0, vcc, 1, v01118; VI-NEXT: flat_store_dwordx3 v[0:1], v[0:2]1119; VI-NEXT: s_endpgm1120;1121; GFX11-LABEL: ps_mesa_v3i32:1122; GFX11: ; %bb.0:1123; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v21124; GFX11-NEXT: v_add_nc_u32_e32 v1, 2, v11125; GFX11-NEXT: v_add_nc_u32_e32 v0, 1, v01126; GFX11-NEXT: global_store_b96 v[0:1], v[0:2], off1127; GFX11-NEXT: s_endpgm1128;1129; GFX1250-LABEL: ps_mesa_v3i32:1130; GFX1250: ; %bb.0:1131; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11132; GFX1250-NEXT: v_dual_add_nc_u32 v2, 3, v2 :: v_dual_add_nc_u32 v1, 2, v11133; GFX1250-NEXT: v_add_nc_u32_e32 v0, 1, v01134; GFX1250-NEXT: global_store_b96 v[0:1], v[0:2], off1135; GFX1250-NEXT: s_endpgm1136 %add = add <3 x i32> %arg0, <i32 1, i32 2, i32 3>1137 store <3 x i32> %add, ptr addrspace(1) poison1138 ret void1139}1140 1141define amdgpu_ps void @ps_mesa_v3f32(<3 x float> %arg0) {1142; SI-LABEL: ps_mesa_v3f32:1143; SI: ; %bb.0:1144; SI-NEXT: v_add_f32_e32 v1, 2.0, v11145; SI-NEXT: v_add_f32_e32 v0, 1.0, v01146; SI-NEXT: v_add_f32_e32 v2, 4.0, v21147; SI-NEXT: s_mov_b32 s3, 0xf0001148; SI-NEXT: s_mov_b32 s2, -11149; SI-NEXT: buffer_store_dword v2, off, s[0:3], 01150; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01151; SI-NEXT: s_endpgm1152;1153; VI-LABEL: ps_mesa_v3f32:1154; VI: ; %bb.0:1155; VI-NEXT: v_add_f32_e32 v2, 4.0, v21156; VI-NEXT: v_add_f32_e32 v1, 2.0, v11157; VI-NEXT: v_add_f32_e32 v0, 1.0, v01158; VI-NEXT: flat_store_dwordx3 v[0:1], v[0:2]1159; VI-NEXT: s_endpgm1160;1161; GFX11-LABEL: ps_mesa_v3f32:1162; GFX11: ; %bb.0:1163; GFX11-NEXT: v_dual_add_f32 v2, 4.0, v2 :: v_dual_add_f32 v1, 2.0, v11164; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v01165; GFX11-NEXT: global_store_b96 v[0:1], v[0:2], off1166; GFX11-NEXT: s_endpgm1167;1168; GFX1250-LABEL: ps_mesa_v3f32:1169; GFX1250: ; %bb.0:1170; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11171; GFX1250-NEXT: v_dual_add_f32 v2, 4.0, v2 :: v_dual_add_f32 v1, 2.0, v11172; GFX1250-NEXT: v_add_f32_e32 v0, 1.0, v01173; GFX1250-NEXT: global_store_b96 v[0:1], v[0:2], off1174; GFX1250-NEXT: s_endpgm1175 %add = fadd <3 x float> %arg0, <float 1.0, float 2.0, float 4.0>1176 store <3 x float> %add, ptr addrspace(1) poison1177 ret void1178}1179 1180define amdgpu_ps void @ps_mesa_v5i32(<5 x i32> %arg0) {1181; SI-LABEL: ps_mesa_v5i32:1182; SI: ; %bb.0:1183; SI-NEXT: v_add_i32_e32 v3, vcc, 4, v31184; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v21185; SI-NEXT: v_add_i32_e32 v1, vcc, 2, v11186; SI-NEXT: v_add_i32_e32 v0, vcc, 1, v01187; SI-NEXT: v_add_i32_e32 v4, vcc, 5, v41188; SI-NEXT: s_mov_b32 s3, 0xf0001189; SI-NEXT: s_mov_b32 s2, -11190; SI-NEXT: buffer_store_dword v4, off, s[0:3], 01191; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 01192; SI-NEXT: s_endpgm1193;1194; VI-LABEL: ps_mesa_v5i32:1195; VI: ; %bb.0:1196; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v31197; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v21198; VI-NEXT: v_add_u32_e32 v1, vcc, 2, v11199; VI-NEXT: v_add_u32_e32 v0, vcc, 1, v01200; VI-NEXT: v_add_u32_e32 v4, vcc, 5, v41201; VI-NEXT: flat_store_dword v[0:1], v41202; VI-NEXT: flat_store_dwordx4 v[0:1], v[0:3]1203; VI-NEXT: s_endpgm1204;1205; GFX11-LABEL: ps_mesa_v5i32:1206; GFX11: ; %bb.0:1207; GFX11-NEXT: v_add_nc_u32_e32 v3, 4, v31208; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v21209; GFX11-NEXT: v_add_nc_u32_e32 v1, 2, v11210; GFX11-NEXT: v_add_nc_u32_e32 v4, 5, v41211; GFX11-NEXT: v_add_nc_u32_e32 v0, 1, v01212; GFX11-NEXT: s_clause 0x11213; GFX11-NEXT: global_store_b32 v[0:1], v4, off1214; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off1215; GFX11-NEXT: s_endpgm1216;1217; GFX1250-LABEL: ps_mesa_v5i32:1218; GFX1250: ; %bb.0:1219; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11220; GFX1250-NEXT: v_dual_add_nc_u32 v3, 4, v3 :: v_dual_add_nc_u32 v2, 3, v21221; GFX1250-NEXT: v_dual_add_nc_u32 v1, 2, v1 :: v_dual_add_nc_u32 v4, 5, v41222; GFX1250-NEXT: v_add_nc_u32_e32 v0, 1, v01223; GFX1250-NEXT: s_clause 0x11224; GFX1250-NEXT: global_store_b32 v[0:1], v4, off1225; GFX1250-NEXT: global_store_b128 v[0:1], v[0:3], off1226; GFX1250-NEXT: s_endpgm1227 %add = add <5 x i32> %arg0, <i32 1, i32 2, i32 3, i32 4, i32 5>1228 store <5 x i32> %add, ptr addrspace(1) poison1229 ret void1230}1231 1232define amdgpu_ps void @ps_mesa_v5f32(<5 x float> %arg0) {1233; SI-LABEL: ps_mesa_v5f32:1234; SI: ; %bb.0:1235; SI-NEXT: v_add_f32_e32 v3, -1.0, v31236; SI-NEXT: v_add_f32_e32 v2, 4.0, v21237; SI-NEXT: v_add_f32_e32 v1, 2.0, v11238; SI-NEXT: v_add_f32_e32 v0, 1.0, v01239; SI-NEXT: v_add_f32_e32 v4, 0.5, v41240; SI-NEXT: s_mov_b32 s3, 0xf0001241; SI-NEXT: s_mov_b32 s2, -11242; SI-NEXT: buffer_store_dword v4, off, s[0:3], 01243; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 01244; SI-NEXT: s_endpgm1245;1246; VI-LABEL: ps_mesa_v5f32:1247; VI: ; %bb.0:1248; VI-NEXT: v_add_f32_e32 v3, -1.0, v31249; VI-NEXT: v_add_f32_e32 v2, 4.0, v21250; VI-NEXT: v_add_f32_e32 v1, 2.0, v11251; VI-NEXT: v_add_f32_e32 v0, 1.0, v01252; VI-NEXT: v_add_f32_e32 v4, 0.5, v41253; VI-NEXT: flat_store_dword v[0:1], v41254; VI-NEXT: flat_store_dwordx4 v[0:1], v[0:3]1255; VI-NEXT: s_endpgm1256;1257; GFX11-LABEL: ps_mesa_v5f32:1258; GFX11: ; %bb.0:1259; GFX11-NEXT: v_dual_add_f32 v3, -1.0, v3 :: v_dual_add_f32 v2, 4.0, v21260; GFX11-NEXT: v_dual_add_f32 v1, 2.0, v1 :: v_dual_add_f32 v4, 0.5, v41261; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v01262; GFX11-NEXT: s_clause 0x11263; GFX11-NEXT: global_store_b32 v[0:1], v4, off1264; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off1265; GFX11-NEXT: s_endpgm1266;1267; GFX1250-LABEL: ps_mesa_v5f32:1268; GFX1250: ; %bb.0:1269; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11270; GFX1250-NEXT: v_dual_add_f32 v3, -1.0, v3 :: v_dual_add_f32 v2, 4.0, v21271; GFX1250-NEXT: v_dual_add_f32 v1, 2.0, v1 :: v_dual_add_f32 v4, 0.5, v41272; GFX1250-NEXT: v_add_f32_e32 v0, 1.0, v01273; GFX1250-NEXT: s_clause 0x11274; GFX1250-NEXT: global_store_b32 v[0:1], v4, off1275; GFX1250-NEXT: global_store_b128 v[0:1], v[0:3], off1276; GFX1250-NEXT: s_endpgm1277 %add = fadd <5 x float> %arg0, <float 1.0, float 2.0, float 4.0, float -1.0, float 0.5>1278 store <5 x float> %add, ptr addrspace(1) poison1279 ret void1280}1281 1282define amdgpu_ps void @ps_mesa_i16(i16 %arg0) {1283; SI-LABEL: ps_mesa_i16:1284; SI: ; %bb.0:1285; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v01286; SI-NEXT: s_mov_b32 s3, 0xf0001287; SI-NEXT: s_mov_b32 s2, -11288; SI-NEXT: buffer_store_short v0, off, s[0:3], 01289; SI-NEXT: s_endpgm1290;1291; VI-LABEL: ps_mesa_i16:1292; VI: ; %bb.0:1293; VI-NEXT: v_add_u16_e32 v0, v0, v01294; VI-NEXT: flat_store_short v[0:1], v01295; VI-NEXT: s_endpgm1296;1297; GFX11-TRUE16-LABEL: ps_mesa_i16:1298; GFX11-TRUE16: ; %bb.0:1299; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.l1300; GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v0, off1301; GFX11-TRUE16-NEXT: s_endpgm1302;1303; GFX11-FAKE16-LABEL: ps_mesa_i16:1304; GFX11-FAKE16: ; %bb.0:1305; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v0, v01306; GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v0, off1307; GFX11-FAKE16-NEXT: s_endpgm1308;1309; GFX1250-TRUE16-LABEL: ps_mesa_i16:1310; GFX1250-TRUE16: ; %bb.0:1311; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11312; GFX1250-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.l1313; GFX1250-TRUE16-NEXT: global_store_b16 v[0:1], v0, off1314; GFX1250-TRUE16-NEXT: s_endpgm1315;1316; GFX1250-FAKE16-LABEL: ps_mesa_i16:1317; GFX1250-FAKE16: ; %bb.0:1318; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11319; GFX1250-FAKE16-NEXT: v_add_nc_u16 v0, v0, v01320; GFX1250-FAKE16-NEXT: global_store_b16 v[0:1], v0, off1321; GFX1250-FAKE16-NEXT: s_endpgm1322 %add = add i16 %arg0, %arg01323 store i16 %add, ptr addrspace(1) poison1324 ret void1325}1326 1327define amdgpu_ps void @ps_mesa_inreg_i16(i16 inreg %arg0) {1328; SI-LABEL: ps_mesa_inreg_i16:1329; SI: ; %bb.0:1330; SI-NEXT: s_add_i32 s0, s0, s01331; SI-NEXT: s_mov_b32 s3, 0xf0001332; SI-NEXT: s_mov_b32 s2, -11333; SI-NEXT: v_mov_b32_e32 v0, s01334; SI-NEXT: buffer_store_short v0, off, s[0:3], 01335; SI-NEXT: s_endpgm1336;1337; VI-LABEL: ps_mesa_inreg_i16:1338; VI: ; %bb.0:1339; VI-NEXT: s_add_i32 s0, s0, s01340; VI-NEXT: v_mov_b32_e32 v0, s01341; VI-NEXT: flat_store_short v[0:1], v01342; VI-NEXT: s_endpgm1343;1344; GFX11-LABEL: ps_mesa_inreg_i16:1345; GFX11: ; %bb.0:1346; GFX11-NEXT: s_add_i32 s0, s0, s01347; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1348; GFX11-NEXT: v_mov_b32_e32 v0, s01349; GFX11-NEXT: global_store_b16 v[0:1], v0, off1350; GFX11-NEXT: s_endpgm1351;1352; GFX1250-LABEL: ps_mesa_inreg_i16:1353; GFX1250: ; %bb.0:1354; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11355; GFX1250-NEXT: s_add_co_i32 s0, s0, s01356; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1357; GFX1250-NEXT: v_mov_b32_e32 v0, s01358; GFX1250-NEXT: global_store_b16 v[0:1], v0, off1359; GFX1250-NEXT: s_endpgm1360 %add = add i16 %arg0, %arg01361 store i16 %add, ptr addrspace(1) poison1362 ret void1363}1364 1365define amdgpu_ps i16 @ret_ps_mesa_i16() {1366; SI-LABEL: ret_ps_mesa_i16:1367; SI: ; %bb.0:1368; SI-NEXT: s_movk_i32 s0, 0x7b1369; SI-NEXT: ; return to shader part epilog1370;1371; VI-LABEL: ret_ps_mesa_i16:1372; VI: ; %bb.0:1373; VI-NEXT: s_movk_i32 s0, 0x7b1374; VI-NEXT: ; return to shader part epilog1375;1376; GFX11-LABEL: ret_ps_mesa_i16:1377; GFX11: ; %bb.0:1378; GFX11-NEXT: s_movk_i32 s0, 0x7b1379; GFX11-NEXT: ; return to shader part epilog1380;1381; GFX1250-LABEL: ret_ps_mesa_i16:1382; GFX1250: ; %bb.0:1383; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11384; GFX1250-NEXT: s_movk_i32 s0, 0x7b1385; GFX1250-NEXT: ; return to shader part epilog1386 ret i16 1231387}1388 1389define amdgpu_kernel void @amd_kernel_i8(i8 %arg0) {1390; SI-LABEL: amd_kernel_i8:1391; SI: ; %bb.0: ; %entry1392; SI-NEXT: s_load_dword s0, s[4:5], 0x91393; SI-NEXT: s_mov_b32 s3, 0xf0001394; SI-NEXT: s_waitcnt lgkmcnt(0)1395; SI-NEXT: s_add_i32 s0, s0, s01396; SI-NEXT: s_mov_b32 s2, -11397; SI-NEXT: v_mov_b32_e32 v0, s01398; SI-NEXT: buffer_store_byte v0, off, s[0:3], 01399; SI-NEXT: s_endpgm1400;1401; VI-LABEL: amd_kernel_i8:1402; VI: ; %bb.0: ; %entry1403; VI-NEXT: s_load_dword s0, s[4:5], 0x241404; VI-NEXT: s_waitcnt lgkmcnt(0)1405; VI-NEXT: s_add_i32 s0, s0, s01406; VI-NEXT: v_mov_b32_e32 v0, s01407; VI-NEXT: flat_store_byte v[0:1], v01408; VI-NEXT: s_endpgm1409;1410; GFX11-LABEL: amd_kernel_i8:1411; GFX11: ; %bb.0: ; %entry1412; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x241413; GFX11-NEXT: s_waitcnt lgkmcnt(0)1414; GFX11-NEXT: s_add_i32 s0, s0, s01415; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1416; GFX11-NEXT: v_mov_b32_e32 v0, s01417; GFX11-NEXT: global_store_b8 v[0:1], v0, off1418; GFX11-NEXT: s_endpgm1419;1420; GFX1250-LABEL: amd_kernel_i8:1421; GFX1250: ; %bb.0: ; %entry1422; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11423; GFX1250-NEXT: s_load_b32 s0, s[4:5], 0x241424; GFX1250-NEXT: s_wait_kmcnt 0x01425; GFX1250-NEXT: s_add_co_i32 s0, s0, s01426; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1427; GFX1250-NEXT: v_mov_b32_e32 v0, s01428; GFX1250-NEXT: global_store_b8 v[0:1], v0, off1429; GFX1250-NEXT: s_endpgm1430entry:1431 %add = add i8 %arg0, %arg01432 store i8 %add, ptr addrspace(1) poison1433 ret void1434}1435 1436define amdgpu_kernel void @amd_kernel_v2i8(<2 x i8> %arg0) {1437; SI-LABEL: amd_kernel_v2i8:1438; SI: ; %bb.0: ; %entry1439; SI-NEXT: s_load_dword s2, s[4:5], 0x91440; SI-NEXT: s_mov_b64 s[0:1], 01441; SI-NEXT: s_mov_b32 s3, 0xf0001442; SI-NEXT: s_waitcnt lgkmcnt(0)1443; SI-NEXT: s_bfe_u32 s4, s2, 0x800081444; SI-NEXT: s_add_i32 s2, s2, s21445; SI-NEXT: s_and_b32 s2, s2, 0xff1446; SI-NEXT: s_add_i32 s4, s4, s41447; SI-NEXT: s_lshl_b32 s4, s4, 81448; SI-NEXT: s_or_b32 s4, s2, s41449; SI-NEXT: s_mov_b32 s2, -11450; SI-NEXT: v_mov_b32_e32 v0, s41451; SI-NEXT: buffer_store_short v0, off, s[0:3], 01452; SI-NEXT: s_endpgm1453;1454; VI-LABEL: amd_kernel_v2i8:1455; VI: ; %bb.0: ; %entry1456; VI-NEXT: s_load_dword s0, s[4:5], 0x241457; VI-NEXT: v_mov_b32_e32 v0, 01458; VI-NEXT: v_mov_b32_e32 v1, 01459; VI-NEXT: s_waitcnt lgkmcnt(0)1460; VI-NEXT: s_bfe_u32 s1, s0, 0x800081461; VI-NEXT: s_add_i32 s0, s0, s01462; VI-NEXT: s_add_i32 s1, s1, s11463; VI-NEXT: s_and_b32 s0, s0, 0xff1464; VI-NEXT: s_lshl_b32 s1, s1, 81465; VI-NEXT: s_or_b32 s0, s0, s11466; VI-NEXT: v_mov_b32_e32 v2, s01467; VI-NEXT: flat_store_short v[0:1], v21468; VI-NEXT: s_endpgm1469;1470; GFX11-LABEL: amd_kernel_v2i8:1471; GFX11: ; %bb.0: ; %entry1472; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x241473; GFX11-NEXT: v_mov_b32_e32 v0, 01474; GFX11-NEXT: s_waitcnt lgkmcnt(0)1475; GFX11-NEXT: s_bfe_u32 s1, s0, 0x800081476; GFX11-NEXT: s_add_i32 s0, s0, s01477; GFX11-NEXT: s_add_i32 s1, s1, s11478; GFX11-NEXT: s_and_b32 s0, s0, 0xff1479; GFX11-NEXT: s_lshl_b32 s1, s1, 81480; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)1481; GFX11-NEXT: s_or_b32 s0, s0, s11482; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s01483; GFX11-NEXT: global_store_b16 v[0:1], v2, off1484; GFX11-NEXT: s_endpgm1485;1486; GFX1250-LABEL: amd_kernel_v2i8:1487; GFX1250: ; %bb.0: ; %entry1488; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11489; GFX1250-NEXT: s_load_b32 s0, s[4:5], 0x241490; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 01491; GFX1250-NEXT: s_wait_kmcnt 0x01492; GFX1250-NEXT: s_bfe_u32 s1, s0, 0x800081493; GFX1250-NEXT: s_add_co_i32 s0, s0, s01494; GFX1250-NEXT: s_add_co_i32 s1, s1, s11495; GFX1250-NEXT: s_and_b32 s0, s0, 0xff1496; GFX1250-NEXT: s_lshl_b32 s1, s1, 81497; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)1498; GFX1250-NEXT: s_or_b32 s0, s0, s11499; GFX1250-NEXT: v_mov_b32_e32 v2, s01500; GFX1250-NEXT: global_store_b16 v[0:1], v2, off1501; GFX1250-NEXT: s_endpgm1502entry:1503 %add = add <2 x i8> %arg0, %arg01504 store <2 x i8> %add, ptr addrspace(1) null1505 ret void1506}1507 1508define amdgpu_kernel void @amd_kernel_v4i8(<4 x i8> %arg0) {1509; SI-LABEL: amd_kernel_v4i8:1510; SI: ; %bb.0: ; %entry1511; SI-NEXT: s_load_dword s2, s[4:5], 0x91512; SI-NEXT: s_mov_b64 s[0:1], 01513; SI-NEXT: s_mov_b32 s3, 0xf0001514; SI-NEXT: s_waitcnt lgkmcnt(0)1515; SI-NEXT: s_lshr_b32 s4, s2, 161516; SI-NEXT: s_lshr_b32 s5, s2, 241517; SI-NEXT: s_bfe_u32 s6, s2, 0x800081518; SI-NEXT: s_add_i32 s2, s2, s21519; SI-NEXT: s_add_i32 s5, s5, s51520; SI-NEXT: s_add_i32 s4, s4, s41521; SI-NEXT: s_and_b32 s2, s2, 0xff1522; SI-NEXT: s_add_i32 s6, s6, s61523; SI-NEXT: s_lshl_b32 s5, s5, 241524; SI-NEXT: s_and_b32 s4, s4, 0xff1525; SI-NEXT: s_lshl_b32 s6, s6, 81526; SI-NEXT: s_lshl_b32 s4, s4, 161527; SI-NEXT: s_or_b32 s2, s2, s61528; SI-NEXT: s_or_b32 s4, s5, s41529; SI-NEXT: s_and_b32 s2, s2, 0xffff1530; SI-NEXT: s_or_b32 s4, s2, s41531; SI-NEXT: s_mov_b32 s2, -11532; SI-NEXT: v_mov_b32_e32 v0, s41533; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01534; SI-NEXT: s_endpgm1535;1536; VI-LABEL: amd_kernel_v4i8:1537; VI: ; %bb.0: ; %entry1538; VI-NEXT: s_load_dword s0, s[4:5], 0x241539; VI-NEXT: v_mov_b32_e32 v0, 01540; VI-NEXT: v_mov_b32_e32 v1, 01541; VI-NEXT: s_waitcnt lgkmcnt(0)1542; VI-NEXT: s_lshr_b32 s1, s0, 161543; VI-NEXT: s_lshr_b32 s2, s0, 241544; VI-NEXT: s_bfe_u32 s3, s0, 0x800081545; VI-NEXT: s_add_i32 s2, s2, s21546; VI-NEXT: s_add_i32 s1, s1, s11547; VI-NEXT: s_lshl_b32 s2, s2, 81548; VI-NEXT: s_and_b32 s1, s1, 0xff1549; VI-NEXT: s_add_i32 s0, s0, s01550; VI-NEXT: s_add_i32 s3, s3, s31551; VI-NEXT: s_or_b32 s1, s1, s21552; VI-NEXT: s_and_b32 s0, s0, 0xff1553; VI-NEXT: s_lshl_b32 s2, s3, 81554; VI-NEXT: s_or_b32 s0, s0, s21555; VI-NEXT: s_lshl_b32 s1, s1, 161556; VI-NEXT: s_and_b32 s0, s0, 0xffff1557; VI-NEXT: s_or_b32 s0, s0, s11558; VI-NEXT: v_mov_b32_e32 v2, s01559; VI-NEXT: flat_store_dword v[0:1], v21560; VI-NEXT: s_endpgm1561;1562; GFX11-LABEL: amd_kernel_v4i8:1563; GFX11: ; %bb.0: ; %entry1564; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x241565; GFX11-NEXT: v_mov_b32_e32 v0, 01566; GFX11-NEXT: s_waitcnt lgkmcnt(0)1567; GFX11-NEXT: s_lshr_b32 s1, s0, 161568; GFX11-NEXT: s_lshr_b32 s2, s0, 241569; GFX11-NEXT: s_add_i32 s3, s0, s01570; GFX11-NEXT: s_bfe_u32 s0, s0, 0x800081571; GFX11-NEXT: s_add_i32 s2, s2, s21572; GFX11-NEXT: s_add_i32 s0, s0, s01573; GFX11-NEXT: s_add_i32 s1, s1, s11574; GFX11-NEXT: s_and_b32 s3, s3, 0xff1575; GFX11-NEXT: s_lshl_b32 s0, s0, 81576; GFX11-NEXT: s_lshl_b32 s2, s2, 81577; GFX11-NEXT: s_and_b32 s1, s1, 0xff1578; GFX11-NEXT: s_or_b32 s0, s3, s01579; GFX11-NEXT: s_or_b32 s1, s1, s21580; GFX11-NEXT: s_and_b32 s0, s0, 0xffff1581; GFX11-NEXT: s_lshl_b32 s1, s1, 161582; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)1583; GFX11-NEXT: s_or_b32 s0, s0, s11584; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s01585; GFX11-NEXT: global_store_b32 v[0:1], v2, off1586; GFX11-NEXT: s_endpgm1587;1588; GFX1250-LABEL: amd_kernel_v4i8:1589; GFX1250: ; %bb.0: ; %entry1590; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11591; GFX1250-NEXT: s_load_b32 s0, s[4:5], 0x241592; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 01593; GFX1250-NEXT: s_wait_kmcnt 0x01594; GFX1250-NEXT: s_lshr_b32 s1, s0, 161595; GFX1250-NEXT: s_lshr_b32 s2, s0, 241596; GFX1250-NEXT: s_add_co_i32 s3, s0, s01597; GFX1250-NEXT: s_bfe_u32 s0, s0, 0x800081598; GFX1250-NEXT: s_add_co_i32 s2, s2, s21599; GFX1250-NEXT: s_add_co_i32 s0, s0, s01600; GFX1250-NEXT: s_add_co_i32 s1, s1, s11601; GFX1250-NEXT: s_and_b32 s3, s3, 0xff1602; GFX1250-NEXT: s_lshl_b32 s0, s0, 81603; GFX1250-NEXT: s_lshl_b32 s2, s2, 81604; GFX1250-NEXT: s_and_b32 s1, s1, 0xff1605; GFX1250-NEXT: s_or_b32 s0, s3, s01606; GFX1250-NEXT: s_or_b32 s1, s1, s21607; GFX1250-NEXT: s_and_b32 s0, s0, 0xffff1608; GFX1250-NEXT: s_lshl_b32 s1, s1, 161609; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)1610; GFX1250-NEXT: s_or_b32 s0, s0, s11611; GFX1250-NEXT: v_mov_b32_e32 v2, s01612; GFX1250-NEXT: global_store_b32 v[0:1], v2, off1613; GFX1250-NEXT: s_endpgm1614entry:1615 %add = add <4 x i8> %arg0, %arg01616 store <4 x i8> %add, ptr addrspace(1) null1617 ret void1618}1619 1620define amdgpu_kernel void @amd_kernel_v3i8(<3 x i8> %arg0) {1621; SI-LABEL: amd_kernel_v3i8:1622; SI: ; %bb.0: ; %entry1623; SI-NEXT: s_load_dword s4, s[4:5], 0x91624; SI-NEXT: s_mov_b64 s[0:1], 21625; SI-NEXT: s_mov_b32 s3, 0xf0001626; SI-NEXT: s_mov_b32 s2, -11627; SI-NEXT: s_waitcnt lgkmcnt(0)1628; SI-NEXT: s_lshr_b32 s5, s4, 161629; SI-NEXT: s_bfe_u32 s6, s4, 0x800081630; SI-NEXT: s_add_i32 s4, s4, s41631; SI-NEXT: s_and_b32 s4, s4, 0xff1632; SI-NEXT: s_add_i32 s6, s6, s61633; SI-NEXT: s_add_i32 s5, s5, s51634; SI-NEXT: s_lshl_b32 s6, s6, 81635; SI-NEXT: v_mov_b32_e32 v0, s51636; SI-NEXT: buffer_store_byte v0, off, s[0:3], 01637; SI-NEXT: s_or_b32 s4, s4, s61638; SI-NEXT: s_mov_b64 s[0:1], 01639; SI-NEXT: s_waitcnt expcnt(0)1640; SI-NEXT: v_mov_b32_e32 v0, s41641; SI-NEXT: buffer_store_short v0, off, s[0:3], 01642; SI-NEXT: s_endpgm1643;1644; VI-LABEL: amd_kernel_v3i8:1645; VI: ; %bb.0: ; %entry1646; VI-NEXT: s_load_dword s0, s[4:5], 0x241647; VI-NEXT: v_mov_b32_e32 v0, 21648; VI-NEXT: v_mov_b32_e32 v1, 01649; VI-NEXT: s_waitcnt lgkmcnt(0)1650; VI-NEXT: s_lshr_b32 s1, s0, 161651; VI-NEXT: s_bfe_u32 s2, s0, 0x800081652; VI-NEXT: s_add_i32 s0, s0, s01653; VI-NEXT: s_add_i32 s2, s2, s21654; VI-NEXT: s_add_i32 s1, s1, s11655; VI-NEXT: s_and_b32 s0, s0, 0xff1656; VI-NEXT: s_lshl_b32 s2, s2, 81657; VI-NEXT: v_mov_b32_e32 v2, s11658; VI-NEXT: s_or_b32 s0, s0, s21659; VI-NEXT: flat_store_byte v[0:1], v21660; VI-NEXT: v_mov_b32_e32 v0, 01661; VI-NEXT: v_mov_b32_e32 v1, 01662; VI-NEXT: v_mov_b32_e32 v2, s01663; VI-NEXT: flat_store_short v[0:1], v21664; VI-NEXT: s_endpgm1665;1666; GFX11-LABEL: amd_kernel_v3i8:1667; GFX11: ; %bb.0: ; %entry1668; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x241669; GFX11-NEXT: v_mov_b32_e32 v0, 21670; GFX11-NEXT: s_waitcnt lgkmcnt(0)1671; GFX11-NEXT: s_bfe_u32 s2, s0, 0x800081672; GFX11-NEXT: s_lshr_b32 s1, s0, 161673; GFX11-NEXT: s_add_i32 s0, s0, s01674; GFX11-NEXT: s_add_i32 s2, s2, s21675; GFX11-NEXT: s_and_b32 s0, s0, 0xff1676; GFX11-NEXT: s_lshl_b32 s2, s2, 81677; GFX11-NEXT: s_add_i32 s1, s1, s11678; GFX11-NEXT: s_or_b32 s0, s0, s21679; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, s11680; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, s01681; GFX11-NEXT: v_mov_b32_e32 v3, 01682; GFX11-NEXT: s_clause 0x11683; GFX11-NEXT: global_store_b8 v[0:1], v4, off1684; GFX11-NEXT: global_store_b16 v[2:3], v5, off1685; GFX11-NEXT: s_endpgm1686;1687; GFX1250-LABEL: amd_kernel_v3i8:1688; GFX1250: ; %bb.0: ; %entry1689; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11690; GFX1250-NEXT: s_load_b32 s0, s[4:5], 0x241691; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 21692; GFX1250-NEXT: v_mov_b64_e32 v[2:3], 01693; GFX1250-NEXT: s_wait_kmcnt 0x01694; GFX1250-NEXT: s_bfe_u32 s2, s0, 0x800081695; GFX1250-NEXT: s_lshr_b32 s1, s0, 161696; GFX1250-NEXT: s_add_co_i32 s0, s0, s01697; GFX1250-NEXT: s_add_co_i32 s2, s2, s21698; GFX1250-NEXT: s_and_b32 s0, s0, 0xff1699; GFX1250-NEXT: s_lshl_b32 s2, s2, 81700; GFX1250-NEXT: s_add_co_i32 s1, s1, s11701; GFX1250-NEXT: s_or_b32 s0, s0, s21702; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1703; GFX1250-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v5, s01704; GFX1250-NEXT: s_clause 0x11705; GFX1250-NEXT: global_store_b8 v[0:1], v4, off1706; GFX1250-NEXT: global_store_b16 v[2:3], v5, off1707; GFX1250-NEXT: s_endpgm1708entry:1709 %add = add <3 x i8> %arg0, %arg01710 store <3 x i8> %add, ptr addrspace(1) null1711 ret void1712}1713 1714define amdgpu_kernel void @amd_kernel_v5i8(<5 x i8> %arg0) {1715; SI-LABEL: amd_kernel_v5i8:1716; SI: ; %bb.0: ; %entry1717; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x91718; SI-NEXT: s_mov_b64 s[0:1], 41719; SI-NEXT: s_mov_b32 s3, 0xf0001720; SI-NEXT: s_mov_b32 s2, -11721; SI-NEXT: s_waitcnt lgkmcnt(0)1722; SI-NEXT: s_lshr_b32 s6, s4, 161723; SI-NEXT: s_lshr_b32 s7, s4, 241724; SI-NEXT: s_bfe_u32 s8, s4, 0x800081725; SI-NEXT: s_add_i32 s4, s4, s41726; SI-NEXT: s_add_i32 s5, s5, s51727; SI-NEXT: s_add_i32 s7, s7, s71728; SI-NEXT: s_add_i32 s6, s6, s61729; SI-NEXT: s_and_b32 s4, s4, 0xff1730; SI-NEXT: s_add_i32 s8, s8, s81731; SI-NEXT: v_mov_b32_e32 v0, s51732; SI-NEXT: buffer_store_byte v0, off, s[0:3], 01733; SI-NEXT: s_lshl_b32 s0, s7, 241734; SI-NEXT: s_and_b32 s1, s6, 0xff1735; SI-NEXT: s_lshl_b32 s5, s8, 81736; SI-NEXT: s_lshl_b32 s1, s1, 161737; SI-NEXT: s_or_b32 s4, s4, s51738; SI-NEXT: s_or_b32 s0, s0, s11739; SI-NEXT: s_and_b32 s1, s4, 0xffff1740; SI-NEXT: s_or_b32 s4, s1, s01741; SI-NEXT: s_mov_b64 s[0:1], 01742; SI-NEXT: s_waitcnt expcnt(0)1743; SI-NEXT: v_mov_b32_e32 v0, s41744; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01745; SI-NEXT: s_endpgm1746;1747; VI-LABEL: amd_kernel_v5i8:1748; VI: ; %bb.0: ; %entry1749; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241750; VI-NEXT: v_mov_b32_e32 v0, 41751; VI-NEXT: v_mov_b32_e32 v1, 01752; VI-NEXT: s_waitcnt lgkmcnt(0)1753; VI-NEXT: s_lshr_b32 s2, s0, 161754; VI-NEXT: s_lshr_b32 s3, s0, 241755; VI-NEXT: s_bfe_u32 s4, s0, 0x800081756; VI-NEXT: s_add_i32 s3, s3, s31757; VI-NEXT: s_add_i32 s2, s2, s21758; VI-NEXT: s_lshl_b32 s3, s3, 81759; VI-NEXT: s_and_b32 s2, s2, 0xff1760; VI-NEXT: s_add_i32 s0, s0, s01761; VI-NEXT: s_add_i32 s4, s4, s41762; VI-NEXT: s_or_b32 s2, s2, s31763; VI-NEXT: s_and_b32 s0, s0, 0xff1764; VI-NEXT: s_lshl_b32 s3, s4, 81765; VI-NEXT: s_or_b32 s0, s0, s31766; VI-NEXT: s_add_i32 s1, s1, s11767; VI-NEXT: s_lshl_b32 s2, s2, 161768; VI-NEXT: s_and_b32 s0, s0, 0xffff1769; VI-NEXT: v_mov_b32_e32 v2, s11770; VI-NEXT: s_or_b32 s0, s0, s21771; VI-NEXT: flat_store_byte v[0:1], v21772; VI-NEXT: v_mov_b32_e32 v0, 01773; VI-NEXT: v_mov_b32_e32 v1, 01774; VI-NEXT: v_mov_b32_e32 v2, s01775; VI-NEXT: flat_store_dword v[0:1], v21776; VI-NEXT: s_endpgm1777;1778; GFX11-LABEL: amd_kernel_v5i8:1779; GFX11: ; %bb.0: ; %entry1780; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x241781; GFX11-NEXT: v_mov_b32_e32 v0, 41782; GFX11-NEXT: s_waitcnt lgkmcnt(0)1783; GFX11-NEXT: s_lshr_b32 s2, s0, 161784; GFX11-NEXT: s_lshr_b32 s3, s0, 241785; GFX11-NEXT: s_add_i32 s4, s0, s01786; GFX11-NEXT: s_bfe_u32 s0, s0, 0x800081787; GFX11-NEXT: s_add_i32 s3, s3, s31788; GFX11-NEXT: s_add_i32 s0, s0, s01789; GFX11-NEXT: s_add_i32 s2, s2, s21790; GFX11-NEXT: s_and_b32 s4, s4, 0xff1791; GFX11-NEXT: s_lshl_b32 s0, s0, 81792; GFX11-NEXT: s_lshl_b32 s3, s3, 81793; GFX11-NEXT: s_and_b32 s2, s2, 0xff1794; GFX11-NEXT: s_or_b32 s0, s4, s01795; GFX11-NEXT: s_or_b32 s2, s2, s31796; GFX11-NEXT: s_and_b32 s0, s0, 0xffff1797; GFX11-NEXT: s_lshl_b32 s2, s2, 161798; GFX11-NEXT: s_add_i32 s1, s1, s11799; GFX11-NEXT: s_or_b32 s0, s0, s21800; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, s11801; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, s01802; GFX11-NEXT: v_mov_b32_e32 v3, 01803; GFX11-NEXT: s_clause 0x11804; GFX11-NEXT: global_store_b8 v[0:1], v4, off1805; GFX11-NEXT: global_store_b32 v[2:3], v5, off1806; GFX11-NEXT: s_endpgm1807;1808; GFX1250-LABEL: amd_kernel_v5i8:1809; GFX1250: ; %bb.0: ; %entry1810; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11811; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x241812; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 41813; GFX1250-NEXT: v_mov_b64_e32 v[2:3], 01814; GFX1250-NEXT: s_wait_kmcnt 0x01815; GFX1250-NEXT: s_lshr_b32 s2, s0, 161816; GFX1250-NEXT: s_lshr_b32 s3, s0, 241817; GFX1250-NEXT: s_add_co_i32 s4, s0, s01818; GFX1250-NEXT: s_bfe_u32 s0, s0, 0x800081819; GFX1250-NEXT: s_add_co_i32 s3, s3, s31820; GFX1250-NEXT: s_add_co_i32 s0, s0, s01821; GFX1250-NEXT: s_add_co_i32 s2, s2, s21822; GFX1250-NEXT: s_and_b32 s4, s4, 0xff1823; GFX1250-NEXT: s_lshl_b32 s0, s0, 81824; GFX1250-NEXT: s_lshl_b32 s3, s3, 81825; GFX1250-NEXT: s_and_b32 s2, s2, 0xff1826; GFX1250-NEXT: s_or_b32 s0, s4, s01827; GFX1250-NEXT: s_or_b32 s2, s2, s31828; GFX1250-NEXT: s_and_b32 s0, s0, 0xffff1829; GFX1250-NEXT: s_lshl_b32 s2, s2, 161830; GFX1250-NEXT: s_add_co_i32 s1, s1, s11831; GFX1250-NEXT: s_or_b32 s0, s0, s21832; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1833; GFX1250-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v5, s01834; GFX1250-NEXT: s_clause 0x11835; GFX1250-NEXT: global_store_b8 v[0:1], v4, off1836; GFX1250-NEXT: global_store_b32 v[2:3], v5, off1837; GFX1250-NEXT: s_endpgm1838entry:1839 %add = add <5 x i8> %arg0, %arg01840 store <5 x i8> %add, ptr addrspace(1) null1841 ret void1842}1843 1844define amdgpu_kernel void @amd_kernel_v8i8(<8 x i8> %arg0) {1845; SI-LABEL: amd_kernel_v8i8:1846; SI: ; %bb.0: ; %entry1847; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x91848; SI-NEXT: s_mov_b64 s[0:1], 01849; SI-NEXT: s_mov_b32 s3, 0xf0001850; SI-NEXT: s_waitcnt lgkmcnt(0)1851; SI-NEXT: s_lshr_b32 s2, s4, 161852; SI-NEXT: s_lshr_b32 s6, s4, 241853; SI-NEXT: s_lshr_b32 s7, s5, 161854; SI-NEXT: s_lshr_b32 s8, s5, 241855; SI-NEXT: s_bfe_u32 s9, s4, 0x800081856; SI-NEXT: s_bfe_u32 s10, s5, 0x800081857; SI-NEXT: s_add_i32 s5, s5, s51858; SI-NEXT: s_add_i32 s4, s4, s41859; SI-NEXT: s_add_i32 s8, s8, s81860; SI-NEXT: s_add_i32 s7, s7, s71861; SI-NEXT: s_and_b32 s5, s5, 0xff1862; SI-NEXT: s_add_i32 s10, s10, s101863; SI-NEXT: s_add_i32 s6, s6, s61864; SI-NEXT: s_add_i32 s2, s2, s21865; SI-NEXT: s_and_b32 s4, s4, 0xff1866; SI-NEXT: s_add_i32 s9, s9, s91867; SI-NEXT: s_lshl_b32 s8, s8, 241868; SI-NEXT: s_and_b32 s7, s7, 0xff1869; SI-NEXT: s_lshl_b32 s10, s10, 81870; SI-NEXT: s_lshl_b32 s6, s6, 241871; SI-NEXT: s_and_b32 s2, s2, 0xff1872; SI-NEXT: s_lshl_b32 s9, s9, 81873; SI-NEXT: s_lshl_b32 s7, s7, 161874; SI-NEXT: s_or_b32 s5, s5, s101875; SI-NEXT: s_lshl_b32 s2, s2, 161876; SI-NEXT: s_or_b32 s4, s4, s91877; SI-NEXT: s_or_b32 s7, s8, s71878; SI-NEXT: s_and_b32 s5, s5, 0xffff1879; SI-NEXT: s_or_b32 s2, s6, s21880; SI-NEXT: s_and_b32 s4, s4, 0xffff1881; SI-NEXT: s_or_b32 s5, s5, s71882; SI-NEXT: s_or_b32 s4, s4, s21883; SI-NEXT: s_mov_b32 s2, -11884; SI-NEXT: v_mov_b32_e32 v0, s41885; SI-NEXT: v_mov_b32_e32 v1, s51886; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01887; SI-NEXT: s_endpgm1888;1889; VI-LABEL: amd_kernel_v8i8:1890; VI: ; %bb.0: ; %entry1891; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241892; VI-NEXT: v_mov_b32_e32 v2, 01893; VI-NEXT: v_mov_b32_e32 v3, 01894; VI-NEXT: s_waitcnt lgkmcnt(0)1895; VI-NEXT: s_lshr_b32 s2, s0, 161896; VI-NEXT: s_lshr_b32 s3, s0, 241897; VI-NEXT: s_lshr_b32 s4, s1, 161898; VI-NEXT: s_lshr_b32 s5, s1, 241899; VI-NEXT: s_bfe_u32 s6, s0, 0x800081900; VI-NEXT: s_bfe_u32 s7, s1, 0x800081901; VI-NEXT: s_add_i32 s5, s5, s51902; VI-NEXT: s_add_i32 s4, s4, s41903; VI-NEXT: s_add_i32 s3, s3, s31904; VI-NEXT: s_add_i32 s2, s2, s21905; VI-NEXT: s_lshl_b32 s5, s5, 81906; VI-NEXT: s_and_b32 s4, s4, 0xff1907; VI-NEXT: s_add_i32 s1, s1, s11908; VI-NEXT: s_add_i32 s7, s7, s71909; VI-NEXT: s_lshl_b32 s3, s3, 81910; VI-NEXT: s_and_b32 s2, s2, 0xff1911; VI-NEXT: s_add_i32 s0, s0, s01912; VI-NEXT: s_add_i32 s6, s6, s61913; VI-NEXT: s_or_b32 s4, s4, s51914; VI-NEXT: s_and_b32 s1, s1, 0xff1915; VI-NEXT: s_lshl_b32 s5, s7, 81916; VI-NEXT: s_or_b32 s2, s2, s31917; VI-NEXT: s_and_b32 s0, s0, 0xff1918; VI-NEXT: s_lshl_b32 s3, s6, 81919; VI-NEXT: s_or_b32 s1, s1, s51920; VI-NEXT: s_or_b32 s0, s0, s31921; VI-NEXT: s_lshl_b32 s4, s4, 161922; VI-NEXT: s_and_b32 s1, s1, 0xffff1923; VI-NEXT: s_lshl_b32 s2, s2, 161924; VI-NEXT: s_and_b32 s0, s0, 0xffff1925; VI-NEXT: s_or_b32 s1, s1, s41926; VI-NEXT: s_or_b32 s0, s0, s21927; VI-NEXT: v_mov_b32_e32 v0, s01928; VI-NEXT: v_mov_b32_e32 v1, s11929; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]1930; VI-NEXT: s_endpgm1931;1932; GFX11-LABEL: amd_kernel_v8i8:1933; GFX11: ; %bb.0: ; %entry1934; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x241935; GFX11-NEXT: s_waitcnt lgkmcnt(0)1936; GFX11-NEXT: s_lshr_b32 s2, s0, 161937; GFX11-NEXT: s_lshr_b32 s3, s0, 241938; GFX11-NEXT: s_lshr_b32 s4, s1, 161939; GFX11-NEXT: s_lshr_b32 s5, s1, 241940; GFX11-NEXT: s_bfe_u32 s6, s0, 0x800081941; GFX11-NEXT: s_bfe_u32 s7, s1, 0x800081942; GFX11-NEXT: s_add_i32 s1, s1, s11943; GFX11-NEXT: s_add_i32 s0, s0, s01944; GFX11-NEXT: s_add_i32 s7, s7, s71945; GFX11-NEXT: s_add_i32 s5, s5, s51946; GFX11-NEXT: s_add_i32 s4, s4, s41947; GFX11-NEXT: s_add_i32 s6, s6, s61948; GFX11-NEXT: s_add_i32 s3, s3, s31949; GFX11-NEXT: s_add_i32 s2, s2, s21950; GFX11-NEXT: s_and_b32 s1, s1, 0xff1951; GFX11-NEXT: s_and_b32 s0, s0, 0xff1952; GFX11-NEXT: s_lshl_b32 s7, s7, 81953; GFX11-NEXT: s_lshl_b32 s5, s5, 81954; GFX11-NEXT: s_and_b32 s4, s4, 0xff1955; GFX11-NEXT: s_lshl_b32 s6, s6, 81956; GFX11-NEXT: s_lshl_b32 s3, s3, 81957; GFX11-NEXT: s_and_b32 s2, s2, 0xff1958; GFX11-NEXT: s_or_b32 s1, s1, s71959; GFX11-NEXT: s_or_b32 s4, s4, s51960; GFX11-NEXT: s_or_b32 s0, s0, s61961; GFX11-NEXT: s_or_b32 s2, s2, s31962; GFX11-NEXT: s_and_b32 s1, s1, 0xffff1963; GFX11-NEXT: s_and_b32 s0, s0, 0xffff1964; GFX11-NEXT: s_lshl_b32 s2, s2, 161965; GFX11-NEXT: s_lshl_b32 s3, s4, 161966; GFX11-NEXT: s_or_b32 s0, s0, s21967; GFX11-NEXT: s_or_b32 s1, s1, s31968; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1969; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s11970; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, 01971; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off1972; GFX11-NEXT: s_endpgm1973;1974; GFX1250-LABEL: amd_kernel_v8i8:1975; GFX1250: ; %bb.0: ; %entry1976; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11977; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x241978; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 01979; GFX1250-NEXT: s_wait_kmcnt 0x01980; GFX1250-NEXT: s_lshr_b32 s2, s0, 161981; GFX1250-NEXT: s_lshr_b32 s3, s0, 241982; GFX1250-NEXT: s_lshr_b32 s4, s1, 161983; GFX1250-NEXT: s_lshr_b32 s5, s1, 241984; GFX1250-NEXT: s_bfe_u32 s6, s0, 0x800081985; GFX1250-NEXT: s_bfe_u32 s7, s1, 0x800081986; GFX1250-NEXT: s_add_co_i32 s1, s1, s11987; GFX1250-NEXT: s_add_co_i32 s0, s0, s01988; GFX1250-NEXT: s_add_co_i32 s7, s7, s71989; GFX1250-NEXT: s_add_co_i32 s5, s5, s51990; GFX1250-NEXT: s_add_co_i32 s4, s4, s41991; GFX1250-NEXT: s_add_co_i32 s6, s6, s61992; GFX1250-NEXT: s_add_co_i32 s3, s3, s31993; GFX1250-NEXT: s_add_co_i32 s2, s2, s21994; GFX1250-NEXT: s_and_b32 s1, s1, 0xff1995; GFX1250-NEXT: s_and_b32 s0, s0, 0xff1996; GFX1250-NEXT: s_lshl_b32 s7, s7, 81997; GFX1250-NEXT: s_lshl_b32 s5, s5, 81998; GFX1250-NEXT: s_and_b32 s4, s4, 0xff1999; GFX1250-NEXT: s_lshl_b32 s6, s6, 82000; GFX1250-NEXT: s_lshl_b32 s3, s3, 82001; GFX1250-NEXT: s_and_b32 s2, s2, 0xff2002; GFX1250-NEXT: s_or_b32 s1, s1, s72003; GFX1250-NEXT: s_or_b32 s4, s4, s52004; GFX1250-NEXT: s_or_b32 s0, s0, s62005; GFX1250-NEXT: s_or_b32 s2, s2, s32006; GFX1250-NEXT: s_and_b32 s1, s1, 0xffff2007; GFX1250-NEXT: s_lshl_b32 s3, s4, 162008; GFX1250-NEXT: s_and_b32 s0, s0, 0xffff2009; GFX1250-NEXT: s_lshl_b32 s2, s2, 162010; GFX1250-NEXT: s_or_b32 s1, s1, s32011; GFX1250-NEXT: s_or_b32 s0, s0, s22012; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)2013; GFX1250-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s02014; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off2015; GFX1250-NEXT: s_endpgm2016entry:2017 %add = add <8 x i8> %arg0, %arg02018 store <8 x i8> %add, ptr addrspace(1) null2019 ret void2020}2021 2022define amdgpu_kernel void @amd_kernel_v16i8(<16 x i8> %arg0) {2023; SI-LABEL: amd_kernel_v16i8:2024; SI: ; %bb.0: ; %entry2025; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92026; SI-NEXT: s_mov_b64 s[4:5], 02027; SI-NEXT: s_mov_b32 s7, 0xf0002028; SI-NEXT: s_waitcnt lgkmcnt(0)2029; SI-NEXT: s_lshr_b32 s6, s0, 162030; SI-NEXT: s_lshr_b32 s8, s0, 242031; SI-NEXT: s_lshr_b32 s9, s1, 162032; SI-NEXT: s_lshr_b32 s10, s1, 242033; SI-NEXT: s_lshr_b32 s11, s2, 162034; SI-NEXT: s_lshr_b32 s12, s2, 242035; SI-NEXT: s_lshr_b32 s13, s3, 162036; SI-NEXT: s_lshr_b32 s14, s3, 242037; SI-NEXT: s_bfe_u32 s15, s0, 0x800082038; SI-NEXT: s_bfe_u32 s16, s1, 0x800082039; SI-NEXT: s_bfe_u32 s17, s2, 0x800082040; SI-NEXT: s_bfe_u32 s18, s3, 0x800082041; SI-NEXT: s_add_i32 s3, s3, s32042; SI-NEXT: s_add_i32 s2, s2, s22043; SI-NEXT: s_add_i32 s1, s1, s12044; SI-NEXT: s_add_i32 s0, s0, s02045; SI-NEXT: s_add_i32 s14, s14, s142046; SI-NEXT: s_add_i32 s13, s13, s132047; SI-NEXT: s_and_b32 s3, s3, 0xff2048; SI-NEXT: s_add_i32 s18, s18, s182049; SI-NEXT: s_add_i32 s12, s12, s122050; SI-NEXT: s_add_i32 s11, s11, s112051; SI-NEXT: s_and_b32 s2, s2, 0xff2052; SI-NEXT: s_add_i32 s17, s17, s172053; SI-NEXT: s_add_i32 s10, s10, s102054; SI-NEXT: s_add_i32 s9, s9, s92055; SI-NEXT: s_and_b32 s1, s1, 0xff2056; SI-NEXT: s_add_i32 s16, s16, s162057; SI-NEXT: s_add_i32 s8, s8, s82058; SI-NEXT: s_add_i32 s6, s6, s62059; SI-NEXT: s_and_b32 s0, s0, 0xff2060; SI-NEXT: s_add_i32 s15, s15, s152061; SI-NEXT: s_lshl_b32 s14, s14, 242062; SI-NEXT: s_and_b32 s13, s13, 0xff2063; SI-NEXT: s_lshl_b32 s18, s18, 82064; SI-NEXT: s_lshl_b32 s12, s12, 242065; SI-NEXT: s_and_b32 s11, s11, 0xff2066; SI-NEXT: s_lshl_b32 s17, s17, 82067; SI-NEXT: s_lshl_b32 s10, s10, 242068; SI-NEXT: s_and_b32 s9, s9, 0xff2069; SI-NEXT: s_lshl_b32 s16, s16, 82070; SI-NEXT: s_lshl_b32 s8, s8, 242071; SI-NEXT: s_and_b32 s6, s6, 0xff2072; SI-NEXT: s_lshl_b32 s15, s15, 82073; SI-NEXT: s_lshl_b32 s13, s13, 162074; SI-NEXT: s_or_b32 s3, s3, s182075; SI-NEXT: s_lshl_b32 s11, s11, 162076; SI-NEXT: s_or_b32 s2, s2, s172077; SI-NEXT: s_lshl_b32 s9, s9, 162078; SI-NEXT: s_or_b32 s1, s1, s162079; SI-NEXT: s_lshl_b32 s6, s6, 162080; SI-NEXT: s_or_b32 s0, s0, s152081; SI-NEXT: s_or_b32 s13, s14, s132082; SI-NEXT: s_and_b32 s3, s3, 0xffff2083; SI-NEXT: s_or_b32 s11, s12, s112084; SI-NEXT: s_and_b32 s2, s2, 0xffff2085; SI-NEXT: s_or_b32 s9, s10, s92086; SI-NEXT: s_and_b32 s1, s1, 0xffff2087; SI-NEXT: s_or_b32 s6, s8, s62088; SI-NEXT: s_and_b32 s0, s0, 0xffff2089; SI-NEXT: s_or_b32 s3, s3, s132090; SI-NEXT: s_or_b32 s2, s2, s112091; SI-NEXT: s_or_b32 s1, s1, s92092; SI-NEXT: s_or_b32 s0, s0, s62093; SI-NEXT: s_mov_b32 s6, -12094; SI-NEXT: v_mov_b32_e32 v0, s02095; SI-NEXT: v_mov_b32_e32 v1, s12096; SI-NEXT: v_mov_b32_e32 v2, s22097; SI-NEXT: v_mov_b32_e32 v3, s32098; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 02099; SI-NEXT: s_endpgm2100;2101; VI-LABEL: amd_kernel_v16i8:2102; VI: ; %bb.0: ; %entry2103; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x242104; VI-NEXT: v_mov_b32_e32 v4, 02105; VI-NEXT: v_mov_b32_e32 v5, 02106; VI-NEXT: s_waitcnt lgkmcnt(0)2107; VI-NEXT: s_lshr_b32 s4, s0, 162108; VI-NEXT: s_lshr_b32 s5, s0, 242109; VI-NEXT: s_lshr_b32 s6, s1, 162110; VI-NEXT: s_lshr_b32 s7, s1, 242111; VI-NEXT: s_lshr_b32 s8, s2, 162112; VI-NEXT: s_lshr_b32 s9, s2, 242113; VI-NEXT: s_lshr_b32 s10, s3, 162114; VI-NEXT: s_lshr_b32 s11, s3, 242115; VI-NEXT: s_bfe_u32 s12, s0, 0x800082116; VI-NEXT: s_bfe_u32 s13, s1, 0x800082117; VI-NEXT: s_bfe_u32 s14, s2, 0x800082118; VI-NEXT: s_bfe_u32 s15, s3, 0x800082119; VI-NEXT: s_add_i32 s11, s11, s112120; VI-NEXT: s_add_i32 s10, s10, s102121; VI-NEXT: s_add_i32 s9, s9, s92122; VI-NEXT: s_add_i32 s8, s8, s82123; VI-NEXT: s_add_i32 s7, s7, s72124; VI-NEXT: s_add_i32 s6, s6, s62125; VI-NEXT: s_add_i32 s5, s5, s52126; VI-NEXT: s_add_i32 s4, s4, s42127; VI-NEXT: s_lshl_b32 s11, s11, 82128; VI-NEXT: s_and_b32 s10, s10, 0xff2129; VI-NEXT: s_add_i32 s3, s3, s32130; VI-NEXT: s_add_i32 s15, s15, s152131; VI-NEXT: s_lshl_b32 s9, s9, 82132; VI-NEXT: s_and_b32 s8, s8, 0xff2133; VI-NEXT: s_add_i32 s2, s2, s22134; VI-NEXT: s_add_i32 s14, s14, s142135; VI-NEXT: s_lshl_b32 s7, s7, 82136; VI-NEXT: s_and_b32 s6, s6, 0xff2137; VI-NEXT: s_add_i32 s1, s1, s12138; VI-NEXT: s_add_i32 s13, s13, s132139; VI-NEXT: s_lshl_b32 s5, s5, 82140; VI-NEXT: s_and_b32 s4, s4, 0xff2141; VI-NEXT: s_add_i32 s0, s0, s02142; VI-NEXT: s_add_i32 s12, s12, s122143; VI-NEXT: s_or_b32 s10, s10, s112144; VI-NEXT: s_and_b32 s3, s3, 0xff2145; VI-NEXT: s_lshl_b32 s11, s15, 82146; VI-NEXT: s_or_b32 s8, s8, s92147; VI-NEXT: s_and_b32 s2, s2, 0xff2148; VI-NEXT: s_lshl_b32 s9, s14, 82149; VI-NEXT: s_or_b32 s6, s6, s72150; VI-NEXT: s_and_b32 s1, s1, 0xff2151; VI-NEXT: s_lshl_b32 s7, s13, 82152; VI-NEXT: s_or_b32 s4, s4, s52153; VI-NEXT: s_and_b32 s0, s0, 0xff2154; VI-NEXT: s_lshl_b32 s5, s12, 82155; VI-NEXT: s_or_b32 s3, s3, s112156; VI-NEXT: s_or_b32 s2, s2, s92157; VI-NEXT: s_or_b32 s1, s1, s72158; VI-NEXT: s_or_b32 s0, s0, s52159; VI-NEXT: s_lshl_b32 s10, s10, 162160; VI-NEXT: s_and_b32 s3, s3, 0xffff2161; VI-NEXT: s_lshl_b32 s8, s8, 162162; VI-NEXT: s_and_b32 s2, s2, 0xffff2163; VI-NEXT: s_lshl_b32 s6, s6, 162164; VI-NEXT: s_and_b32 s1, s1, 0xffff2165; VI-NEXT: s_lshl_b32 s4, s4, 162166; VI-NEXT: s_and_b32 s0, s0, 0xffff2167; VI-NEXT: s_or_b32 s3, s3, s102168; VI-NEXT: s_or_b32 s2, s2, s82169; VI-NEXT: s_or_b32 s1, s1, s62170; VI-NEXT: s_or_b32 s0, s0, s42171; VI-NEXT: v_mov_b32_e32 v0, s02172; VI-NEXT: v_mov_b32_e32 v1, s12173; VI-NEXT: v_mov_b32_e32 v2, s22174; VI-NEXT: v_mov_b32_e32 v3, s32175; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]2176; VI-NEXT: s_endpgm2177;2178; GFX11-LABEL: amd_kernel_v16i8:2179; GFX11: ; %bb.0: ; %entry2180; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x242181; GFX11-NEXT: s_waitcnt lgkmcnt(0)2182; GFX11-NEXT: s_lshr_b32 s6, s1, 162183; GFX11-NEXT: s_lshr_b32 s7, s1, 242184; GFX11-NEXT: s_lshr_b32 s8, s2, 162185; GFX11-NEXT: s_lshr_b32 s9, s2, 242186; GFX11-NEXT: s_lshr_b32 s10, s3, 162187; GFX11-NEXT: s_lshr_b32 s11, s3, 242188; GFX11-NEXT: s_lshr_b32 s4, s0, 162189; GFX11-NEXT: s_lshr_b32 s5, s0, 242190; GFX11-NEXT: s_bfe_u32 s12, s0, 0x800082191; GFX11-NEXT: s_bfe_u32 s13, s1, 0x800082192; GFX11-NEXT: s_bfe_u32 s14, s2, 0x800082193; GFX11-NEXT: s_bfe_u32 s15, s3, 0x800082194; GFX11-NEXT: s_add_i32 s11, s11, s112195; GFX11-NEXT: s_add_i32 s10, s10, s102196; GFX11-NEXT: s_add_i32 s9, s9, s92197; GFX11-NEXT: s_add_i32 s8, s8, s82198; GFX11-NEXT: s_add_i32 s7, s7, s72199; GFX11-NEXT: s_add_i32 s6, s6, s62200; GFX11-NEXT: s_add_i32 s3, s3, s32201; GFX11-NEXT: s_add_i32 s2, s2, s22202; GFX11-NEXT: s_add_i32 s15, s15, s152203; GFX11-NEXT: s_add_i32 s14, s14, s142204; GFX11-NEXT: s_lshl_b32 s11, s11, 82205; GFX11-NEXT: s_and_b32 s10, s10, 0xff2206; GFX11-NEXT: s_lshl_b32 s9, s9, 82207; GFX11-NEXT: s_and_b32 s8, s8, 0xff2208; GFX11-NEXT: s_add_i32 s1, s1, s12209; GFX11-NEXT: s_add_i32 s13, s13, s132210; GFX11-NEXT: s_lshl_b32 s7, s7, 82211; GFX11-NEXT: s_and_b32 s6, s6, 0xff2212; GFX11-NEXT: s_add_i32 s0, s0, s02213; GFX11-NEXT: s_add_i32 s12, s12, s122214; GFX11-NEXT: s_add_i32 s5, s5, s52215; GFX11-NEXT: s_add_i32 s4, s4, s42216; GFX11-NEXT: s_and_b32 s3, s3, 0xff2217; GFX11-NEXT: s_and_b32 s2, s2, 0xff2218; GFX11-NEXT: s_lshl_b32 s15, s15, 82219; GFX11-NEXT: s_or_b32 s10, s10, s112220; GFX11-NEXT: s_lshl_b32 s11, s14, 82221; GFX11-NEXT: s_or_b32 s8, s8, s92222; GFX11-NEXT: s_and_b32 s1, s1, 0xff2223; GFX11-NEXT: s_lshl_b32 s9, s13, 82224; GFX11-NEXT: s_or_b32 s6, s6, s72225; GFX11-NEXT: s_and_b32 s0, s0, 0xff2226; GFX11-NEXT: s_lshl_b32 s7, s12, 82227; GFX11-NEXT: s_lshl_b32 s5, s5, 82228; GFX11-NEXT: s_and_b32 s4, s4, 0xff2229; GFX11-NEXT: s_or_b32 s3, s3, s152230; GFX11-NEXT: s_or_b32 s2, s2, s112231; GFX11-NEXT: s_or_b32 s1, s1, s92232; GFX11-NEXT: s_or_b32 s0, s0, s72233; GFX11-NEXT: s_or_b32 s4, s4, s52234; GFX11-NEXT: s_and_b32 s3, s3, 0xffff2235; GFX11-NEXT: s_lshl_b32 s10, s10, 162236; GFX11-NEXT: s_and_b32 s2, s2, 0xffff2237; GFX11-NEXT: s_lshl_b32 s8, s8, 162238; GFX11-NEXT: s_and_b32 s1, s1, 0xffff2239; GFX11-NEXT: s_and_b32 s0, s0, 0xffff2240; GFX11-NEXT: s_lshl_b32 s4, s4, 162241; GFX11-NEXT: s_lshl_b32 s5, s6, 162242; GFX11-NEXT: s_or_b32 s3, s3, s102243; GFX11-NEXT: s_or_b32 s2, s2, s82244; GFX11-NEXT: s_or_b32 s0, s0, s42245; GFX11-NEXT: s_or_b32 s1, s1, s52246; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, s32247; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s12248; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v5, 02249; GFX11-NEXT: global_store_b128 v[4:5], v[0:3], off2250; GFX11-NEXT: s_endpgm2251;2252; GFX1250-LABEL: amd_kernel_v16i8:2253; GFX1250: ; %bb.0: ; %entry2254; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12255; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x242256; GFX1250-NEXT: v_mov_b64_e32 v[4:5], 02257; GFX1250-NEXT: s_wait_kmcnt 0x02258; GFX1250-NEXT: s_lshr_b32 s6, s1, 162259; GFX1250-NEXT: s_lshr_b32 s7, s1, 242260; GFX1250-NEXT: s_lshr_b32 s8, s2, 162261; GFX1250-NEXT: s_lshr_b32 s9, s2, 242262; GFX1250-NEXT: s_lshr_b32 s10, s3, 162263; GFX1250-NEXT: s_lshr_b32 s11, s3, 242264; GFX1250-NEXT: s_lshr_b32 s4, s0, 162265; GFX1250-NEXT: s_lshr_b32 s5, s0, 242266; GFX1250-NEXT: s_bfe_u32 s12, s0, 0x800082267; GFX1250-NEXT: s_bfe_u32 s13, s1, 0x800082268; GFX1250-NEXT: s_bfe_u32 s14, s2, 0x800082269; GFX1250-NEXT: s_bfe_u32 s15, s3, 0x800082270; GFX1250-NEXT: s_add_co_i32 s11, s11, s112271; GFX1250-NEXT: s_add_co_i32 s10, s10, s102272; GFX1250-NEXT: s_add_co_i32 s9, s9, s92273; GFX1250-NEXT: s_add_co_i32 s8, s8, s82274; GFX1250-NEXT: s_add_co_i32 s7, s7, s72275; GFX1250-NEXT: s_add_co_i32 s6, s6, s62276; GFX1250-NEXT: s_add_co_i32 s3, s3, s32277; GFX1250-NEXT: s_add_co_i32 s2, s2, s22278; GFX1250-NEXT: s_add_co_i32 s15, s15, s152279; GFX1250-NEXT: s_add_co_i32 s14, s14, s142280; GFX1250-NEXT: s_lshl_b32 s11, s11, 82281; GFX1250-NEXT: s_and_b32 s10, s10, 0xff2282; GFX1250-NEXT: s_lshl_b32 s9, s9, 82283; GFX1250-NEXT: s_and_b32 s8, s8, 0xff2284; GFX1250-NEXT: s_add_co_i32 s1, s1, s12285; GFX1250-NEXT: s_add_co_i32 s13, s13, s132286; GFX1250-NEXT: s_lshl_b32 s7, s7, 82287; GFX1250-NEXT: s_and_b32 s6, s6, 0xff2288; GFX1250-NEXT: s_add_co_i32 s0, s0, s02289; GFX1250-NEXT: s_add_co_i32 s12, s12, s122290; GFX1250-NEXT: s_add_co_i32 s5, s5, s52291; GFX1250-NEXT: s_add_co_i32 s4, s4, s42292; GFX1250-NEXT: s_and_b32 s3, s3, 0xff2293; GFX1250-NEXT: s_and_b32 s2, s2, 0xff2294; GFX1250-NEXT: s_lshl_b32 s15, s15, 82295; GFX1250-NEXT: s_or_b32 s10, s10, s112296; GFX1250-NEXT: s_lshl_b32 s11, s14, 82297; GFX1250-NEXT: s_or_b32 s8, s8, s92298; GFX1250-NEXT: s_and_b32 s1, s1, 0xff2299; GFX1250-NEXT: s_lshl_b32 s9, s13, 82300; GFX1250-NEXT: s_or_b32 s6, s6, s72301; GFX1250-NEXT: s_and_b32 s0, s0, 0xff2302; GFX1250-NEXT: s_lshl_b32 s7, s12, 82303; GFX1250-NEXT: s_lshl_b32 s5, s5, 82304; GFX1250-NEXT: s_and_b32 s4, s4, 0xff2305; GFX1250-NEXT: s_or_b32 s3, s3, s152306; GFX1250-NEXT: s_or_b32 s2, s2, s112307; GFX1250-NEXT: s_or_b32 s1, s1, s92308; GFX1250-NEXT: s_or_b32 s0, s0, s72309; GFX1250-NEXT: s_or_b32 s4, s4, s52310; GFX1250-NEXT: s_and_b32 s3, s3, 0xffff2311; GFX1250-NEXT: s_lshl_b32 s10, s10, 162312; GFX1250-NEXT: s_and_b32 s2, s2, 0xffff2313; GFX1250-NEXT: s_lshl_b32 s8, s8, 162314; GFX1250-NEXT: s_and_b32 s1, s1, 0xffff2315; GFX1250-NEXT: s_and_b32 s0, s0, 0xffff2316; GFX1250-NEXT: s_lshl_b32 s4, s4, 162317; GFX1250-NEXT: s_lshl_b32 s5, s6, 162318; GFX1250-NEXT: s_or_b32 s3, s3, s102319; GFX1250-NEXT: s_or_b32 s2, s2, s82320; GFX1250-NEXT: s_or_b32 s0, s0, s42321; GFX1250-NEXT: s_or_b32 s1, s1, s52322; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)2323; GFX1250-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s12324; GFX1250-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s32325; GFX1250-NEXT: global_store_b128 v[4:5], v[0:3], off2326; GFX1250-NEXT: s_endpgm2327entry:2328 %add = add <16 x i8> %arg0, %arg02329 store <16 x i8> %add, ptr addrspace(1) null2330 ret void2331}2332 2333define amdgpu_kernel void @amd_kernel_v32i8(<32 x i8> %arg0) {2334; SI-LABEL: amd_kernel_v32i8:2335; SI: ; %bb.0: ; %entry2336; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x92337; SI-NEXT: s_mov_b64 s[8:9], 162338; SI-NEXT: s_mov_b32 s11, 0xf0002339; SI-NEXT: s_mov_b32 s10, -12340; SI-NEXT: s_waitcnt lgkmcnt(0)2341; SI-NEXT: s_lshr_b32 s12, s4, 162342; SI-NEXT: s_lshr_b32 s13, s4, 242343; SI-NEXT: s_lshr_b32 s14, s5, 162344; SI-NEXT: s_lshr_b32 s15, s5, 242345; SI-NEXT: s_lshr_b32 s16, s6, 162346; SI-NEXT: s_lshr_b32 s17, s6, 242347; SI-NEXT: s_lshr_b32 s18, s7, 162348; SI-NEXT: s_lshr_b32 s19, s7, 242349; SI-NEXT: s_lshr_b32 s20, s0, 162350; SI-NEXT: s_lshr_b32 s21, s0, 242351; SI-NEXT: s_lshr_b32 s22, s1, 162352; SI-NEXT: s_lshr_b32 s23, s1, 242353; SI-NEXT: s_lshr_b32 s24, s2, 162354; SI-NEXT: s_lshr_b32 s25, s2, 242355; SI-NEXT: s_lshr_b32 s26, s3, 162356; SI-NEXT: s_lshr_b32 s27, s3, 242357; SI-NEXT: s_bfe_u32 s28, s4, 0x800082358; SI-NEXT: s_bfe_u32 s29, s5, 0x800082359; SI-NEXT: s_bfe_u32 s30, s6, 0x800082360; SI-NEXT: s_bfe_u32 s31, s7, 0x800082361; SI-NEXT: s_bfe_u32 s33, s0, 0x800082362; SI-NEXT: s_bfe_u32 s34, s1, 0x800082363; SI-NEXT: s_bfe_u32 s35, s2, 0x800082364; SI-NEXT: s_bfe_u32 s36, s3, 0x800082365; SI-NEXT: s_add_i32 s3, s3, s32366; SI-NEXT: s_add_i32 s2, s2, s22367; SI-NEXT: s_add_i32 s1, s1, s12368; SI-NEXT: s_add_i32 s0, s0, s02369; SI-NEXT: s_add_i32 s7, s7, s72370; SI-NEXT: s_add_i32 s6, s6, s62371; SI-NEXT: s_add_i32 s5, s5, s52372; SI-NEXT: s_add_i32 s4, s4, s42373; SI-NEXT: s_add_i32 s27, s27, s272374; SI-NEXT: s_add_i32 s26, s26, s262375; SI-NEXT: s_and_b32 s3, s3, 0xff2376; SI-NEXT: s_add_i32 s36, s36, s362377; SI-NEXT: s_add_i32 s25, s25, s252378; SI-NEXT: s_add_i32 s24, s24, s242379; SI-NEXT: s_and_b32 s2, s2, 0xff2380; SI-NEXT: s_add_i32 s35, s35, s352381; SI-NEXT: s_add_i32 s23, s23, s232382; SI-NEXT: s_add_i32 s22, s22, s222383; SI-NEXT: s_and_b32 s1, s1, 0xff2384; SI-NEXT: s_add_i32 s34, s34, s342385; SI-NEXT: s_add_i32 s21, s21, s212386; SI-NEXT: s_add_i32 s20, s20, s202387; SI-NEXT: s_and_b32 s0, s0, 0xff2388; SI-NEXT: s_add_i32 s33, s33, s332389; SI-NEXT: s_add_i32 s19, s19, s192390; SI-NEXT: s_add_i32 s18, s18, s182391; SI-NEXT: s_and_b32 s7, s7, 0xff2392; SI-NEXT: s_add_i32 s31, s31, s312393; SI-NEXT: s_add_i32 s17, s17, s172394; SI-NEXT: s_add_i32 s16, s16, s162395; SI-NEXT: s_and_b32 s6, s6, 0xff2396; SI-NEXT: s_add_i32 s30, s30, s302397; SI-NEXT: s_add_i32 s15, s15, s152398; SI-NEXT: s_add_i32 s14, s14, s142399; SI-NEXT: s_and_b32 s5, s5, 0xff2400; SI-NEXT: s_add_i32 s29, s29, s292401; SI-NEXT: s_add_i32 s13, s13, s132402; SI-NEXT: s_add_i32 s12, s12, s122403; SI-NEXT: s_and_b32 s4, s4, 0xff2404; SI-NEXT: s_add_i32 s28, s28, s282405; SI-NEXT: s_lshl_b32 s27, s27, 242406; SI-NEXT: s_and_b32 s26, s26, 0xff2407; SI-NEXT: s_lshl_b32 s36, s36, 82408; SI-NEXT: s_lshl_b32 s25, s25, 242409; SI-NEXT: s_and_b32 s24, s24, 0xff2410; SI-NEXT: s_lshl_b32 s35, s35, 82411; SI-NEXT: s_lshl_b32 s23, s23, 242412; SI-NEXT: s_and_b32 s22, s22, 0xff2413; SI-NEXT: s_lshl_b32 s34, s34, 82414; SI-NEXT: s_lshl_b32 s21, s21, 242415; SI-NEXT: s_and_b32 s20, s20, 0xff2416; SI-NEXT: s_lshl_b32 s33, s33, 82417; SI-NEXT: s_lshl_b32 s19, s19, 242418; SI-NEXT: s_and_b32 s18, s18, 0xff2419; SI-NEXT: s_lshl_b32 s31, s31, 82420; SI-NEXT: s_lshl_b32 s17, s17, 242421; SI-NEXT: s_and_b32 s16, s16, 0xff2422; SI-NEXT: s_lshl_b32 s30, s30, 82423; SI-NEXT: s_lshl_b32 s15, s15, 242424; SI-NEXT: s_and_b32 s14, s14, 0xff2425; SI-NEXT: s_lshl_b32 s29, s29, 82426; SI-NEXT: s_lshl_b32 s13, s13, 242427; SI-NEXT: s_and_b32 s12, s12, 0xff2428; SI-NEXT: s_lshl_b32 s28, s28, 82429; SI-NEXT: s_lshl_b32 s26, s26, 162430; SI-NEXT: s_or_b32 s3, s3, s362431; SI-NEXT: s_lshl_b32 s24, s24, 162432; SI-NEXT: s_or_b32 s2, s2, s352433; SI-NEXT: s_lshl_b32 s22, s22, 162434; SI-NEXT: s_or_b32 s1, s1, s342435; SI-NEXT: s_lshl_b32 s20, s20, 162436; SI-NEXT: s_or_b32 s0, s0, s332437; SI-NEXT: s_lshl_b32 s18, s18, 162438; SI-NEXT: s_or_b32 s7, s7, s312439; SI-NEXT: s_lshl_b32 s16, s16, 162440; SI-NEXT: s_or_b32 s6, s6, s302441; SI-NEXT: s_lshl_b32 s14, s14, 162442; SI-NEXT: s_or_b32 s5, s5, s292443; SI-NEXT: s_lshl_b32 s12, s12, 162444; SI-NEXT: s_or_b32 s4, s4, s282445; SI-NEXT: s_or_b32 s26, s27, s262446; SI-NEXT: s_and_b32 s3, s3, 0xffff2447; SI-NEXT: s_or_b32 s24, s25, s242448; SI-NEXT: s_and_b32 s2, s2, 0xffff2449; SI-NEXT: s_or_b32 s22, s23, s222450; SI-NEXT: s_and_b32 s1, s1, 0xffff2451; SI-NEXT: s_or_b32 s20, s21, s202452; SI-NEXT: s_and_b32 s0, s0, 0xffff2453; SI-NEXT: s_or_b32 s18, s19, s182454; SI-NEXT: s_and_b32 s7, s7, 0xffff2455; SI-NEXT: s_or_b32 s16, s17, s162456; SI-NEXT: s_and_b32 s6, s6, 0xffff2457; SI-NEXT: s_or_b32 s14, s15, s142458; SI-NEXT: s_and_b32 s5, s5, 0xffff2459; SI-NEXT: s_or_b32 s12, s13, s122460; SI-NEXT: s_and_b32 s4, s4, 0xffff2461; SI-NEXT: s_or_b32 s3, s3, s262462; SI-NEXT: s_or_b32 s2, s2, s242463; SI-NEXT: s_or_b32 s1, s1, s222464; SI-NEXT: s_or_b32 s7, s7, s182465; SI-NEXT: s_or_b32 s6, s6, s162466; SI-NEXT: s_or_b32 s5, s5, s142467; SI-NEXT: s_or_b32 s4, s4, s122468; SI-NEXT: s_or_b32 s0, s0, s202469; SI-NEXT: v_mov_b32_e32 v0, s42470; SI-NEXT: v_mov_b32_e32 v1, s52471; SI-NEXT: v_mov_b32_e32 v2, s62472; SI-NEXT: v_mov_b32_e32 v3, s72473; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 02474; SI-NEXT: s_waitcnt expcnt(0)2475; SI-NEXT: v_mov_b32_e32 v0, s02476; SI-NEXT: v_mov_b32_e32 v1, s12477; SI-NEXT: v_mov_b32_e32 v2, s22478; SI-NEXT: v_mov_b32_e32 v3, s32479; SI-NEXT: s_mov_b64 s[8:9], 02480; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 02481; SI-NEXT: s_endpgm2482;2483; VI-LABEL: amd_kernel_v32i8:2484; VI: ; %bb.0: ; %entry2485; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x242486; VI-NEXT: v_mov_b32_e32 v4, 162487; VI-NEXT: v_mov_b32_e32 v5, 02488; VI-NEXT: s_waitcnt lgkmcnt(0)2489; VI-NEXT: s_lshr_b32 s8, s4, 162490; VI-NEXT: s_lshr_b32 s9, s4, 242491; VI-NEXT: s_lshr_b32 s10, s5, 162492; VI-NEXT: s_lshr_b32 s11, s5, 242493; VI-NEXT: s_lshr_b32 s12, s6, 162494; VI-NEXT: s_lshr_b32 s13, s6, 242495; VI-NEXT: s_lshr_b32 s14, s7, 162496; VI-NEXT: s_lshr_b32 s15, s7, 242497; VI-NEXT: s_bfe_u32 s24, s4, 0x800082498; VI-NEXT: s_bfe_u32 s25, s5, 0x800082499; VI-NEXT: s_bfe_u32 s26, s6, 0x800082500; VI-NEXT: s_bfe_u32 s27, s7, 0x800082501; VI-NEXT: s_add_i32 s15, s15, s152502; VI-NEXT: s_add_i32 s14, s14, s142503; VI-NEXT: s_add_i32 s13, s13, s132504; VI-NEXT: s_add_i32 s12, s12, s122505; VI-NEXT: s_add_i32 s11, s11, s112506; VI-NEXT: s_add_i32 s10, s10, s102507; VI-NEXT: s_add_i32 s9, s9, s92508; VI-NEXT: s_add_i32 s8, s8, s82509; VI-NEXT: s_lshr_b32 s16, s0, 162510; VI-NEXT: s_lshr_b32 s17, s0, 242511; VI-NEXT: s_lshr_b32 s18, s1, 162512; VI-NEXT: s_lshr_b32 s19, s1, 242513; VI-NEXT: s_lshr_b32 s20, s2, 162514; VI-NEXT: s_lshr_b32 s21, s2, 242515; VI-NEXT: s_lshr_b32 s22, s3, 162516; VI-NEXT: s_lshr_b32 s23, s3, 242517; VI-NEXT: s_lshl_b32 s15, s15, 82518; VI-NEXT: s_and_b32 s14, s14, 0xff2519; VI-NEXT: s_add_i32 s7, s7, s72520; VI-NEXT: s_add_i32 s27, s27, s272521; VI-NEXT: s_lshl_b32 s13, s13, 82522; VI-NEXT: s_and_b32 s12, s12, 0xff2523; VI-NEXT: s_add_i32 s6, s6, s62524; VI-NEXT: s_add_i32 s26, s26, s262525; VI-NEXT: s_lshl_b32 s11, s11, 82526; VI-NEXT: s_and_b32 s10, s10, 0xff2527; VI-NEXT: s_add_i32 s5, s5, s52528; VI-NEXT: s_add_i32 s25, s25, s252529; VI-NEXT: s_lshl_b32 s9, s9, 82530; VI-NEXT: s_and_b32 s8, s8, 0xff2531; VI-NEXT: s_add_i32 s4, s4, s42532; VI-NEXT: s_add_i32 s24, s24, s242533; VI-NEXT: s_bfe_u32 s28, s0, 0x800082534; VI-NEXT: s_bfe_u32 s29, s1, 0x800082535; VI-NEXT: s_bfe_u32 s30, s2, 0x800082536; VI-NEXT: s_bfe_u32 s31, s3, 0x800082537; VI-NEXT: s_add_i32 s23, s23, s232538; VI-NEXT: s_add_i32 s22, s22, s222539; VI-NEXT: s_add_i32 s21, s21, s212540; VI-NEXT: s_add_i32 s20, s20, s202541; VI-NEXT: s_add_i32 s19, s19, s192542; VI-NEXT: s_add_i32 s18, s18, s182543; VI-NEXT: s_add_i32 s17, s17, s172544; VI-NEXT: s_add_i32 s16, s16, s162545; VI-NEXT: s_or_b32 s14, s14, s152546; VI-NEXT: s_and_b32 s7, s7, 0xff2547; VI-NEXT: s_lshl_b32 s15, s27, 82548; VI-NEXT: s_or_b32 s12, s12, s132549; VI-NEXT: s_and_b32 s6, s6, 0xff2550; VI-NEXT: s_lshl_b32 s13, s26, 82551; VI-NEXT: s_or_b32 s10, s10, s112552; VI-NEXT: s_and_b32 s5, s5, 0xff2553; VI-NEXT: s_lshl_b32 s11, s25, 82554; VI-NEXT: s_or_b32 s8, s8, s92555; VI-NEXT: s_and_b32 s4, s4, 0xff2556; VI-NEXT: s_lshl_b32 s9, s24, 82557; VI-NEXT: s_lshl_b32 s23, s23, 82558; VI-NEXT: s_and_b32 s22, s22, 0xff2559; VI-NEXT: s_add_i32 s3, s3, s32560; VI-NEXT: s_add_i32 s31, s31, s312561; VI-NEXT: s_lshl_b32 s21, s21, 82562; VI-NEXT: s_and_b32 s20, s20, 0xff2563; VI-NEXT: s_add_i32 s2, s2, s22564; VI-NEXT: s_add_i32 s30, s30, s302565; VI-NEXT: s_lshl_b32 s19, s19, 82566; VI-NEXT: s_and_b32 s18, s18, 0xff2567; VI-NEXT: s_add_i32 s1, s1, s12568; VI-NEXT: s_add_i32 s29, s29, s292569; VI-NEXT: s_lshl_b32 s17, s17, 82570; VI-NEXT: s_and_b32 s16, s16, 0xff2571; VI-NEXT: s_add_i32 s0, s0, s02572; VI-NEXT: s_add_i32 s28, s28, s282573; VI-NEXT: s_or_b32 s7, s7, s152574; VI-NEXT: s_or_b32 s6, s6, s132575; VI-NEXT: s_or_b32 s5, s5, s112576; VI-NEXT: s_or_b32 s4, s4, s92577; VI-NEXT: s_or_b32 s22, s22, s232578; VI-NEXT: s_and_b32 s3, s3, 0xff2579; VI-NEXT: s_lshl_b32 s23, s31, 82580; VI-NEXT: s_or_b32 s20, s20, s212581; VI-NEXT: s_and_b32 s2, s2, 0xff2582; VI-NEXT: s_lshl_b32 s21, s30, 82583; VI-NEXT: s_or_b32 s18, s18, s192584; VI-NEXT: s_and_b32 s1, s1, 0xff2585; VI-NEXT: s_lshl_b32 s19, s29, 82586; VI-NEXT: s_or_b32 s16, s16, s172587; VI-NEXT: s_and_b32 s0, s0, 0xff2588; VI-NEXT: s_lshl_b32 s17, s28, 82589; VI-NEXT: s_lshl_b32 s14, s14, 162590; VI-NEXT: s_and_b32 s7, s7, 0xffff2591; VI-NEXT: s_lshl_b32 s12, s12, 162592; VI-NEXT: s_and_b32 s6, s6, 0xffff2593; VI-NEXT: s_lshl_b32 s10, s10, 162594; VI-NEXT: s_and_b32 s5, s5, 0xffff2595; VI-NEXT: s_lshl_b32 s8, s8, 162596; VI-NEXT: s_and_b32 s4, s4, 0xffff2597; VI-NEXT: s_or_b32 s3, s3, s232598; VI-NEXT: s_or_b32 s2, s2, s212599; VI-NEXT: s_or_b32 s1, s1, s192600; VI-NEXT: s_or_b32 s0, s0, s172601; VI-NEXT: s_or_b32 s7, s7, s142602; VI-NEXT: s_or_b32 s6, s6, s122603; VI-NEXT: s_or_b32 s5, s5, s102604; VI-NEXT: s_or_b32 s4, s4, s82605; VI-NEXT: s_lshl_b32 s22, s22, 162606; VI-NEXT: s_and_b32 s3, s3, 0xffff2607; VI-NEXT: s_lshl_b32 s20, s20, 162608; VI-NEXT: s_and_b32 s2, s2, 0xffff2609; VI-NEXT: s_lshl_b32 s18, s18, 162610; VI-NEXT: s_and_b32 s1, s1, 0xffff2611; VI-NEXT: s_lshl_b32 s16, s16, 162612; VI-NEXT: s_and_b32 s0, s0, 0xffff2613; VI-NEXT: v_mov_b32_e32 v0, s42614; VI-NEXT: v_mov_b32_e32 v1, s52615; VI-NEXT: v_mov_b32_e32 v2, s62616; VI-NEXT: v_mov_b32_e32 v3, s72617; VI-NEXT: s_or_b32 s3, s3, s222618; VI-NEXT: s_or_b32 s2, s2, s202619; VI-NEXT: s_or_b32 s1, s1, s182620; VI-NEXT: s_or_b32 s0, s0, s162621; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]2622; VI-NEXT: v_mov_b32_e32 v4, 02623; VI-NEXT: v_mov_b32_e32 v0, s02624; VI-NEXT: v_mov_b32_e32 v1, s12625; VI-NEXT: v_mov_b32_e32 v2, s22626; VI-NEXT: v_mov_b32_e32 v5, 02627; VI-NEXT: v_mov_b32_e32 v3, s32628; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]2629; VI-NEXT: s_endpgm2630;2631; GFX11-LABEL: amd_kernel_v32i8:2632; GFX11: ; %bb.0: ; %entry2633; GFX11-NEXT: s_load_b256 s[0:7], s[4:5], 0x242634; GFX11-NEXT: s_waitcnt lgkmcnt(0)2635; GFX11-NEXT: s_lshr_b32 s16, s0, 162636; GFX11-NEXT: s_lshr_b32 s17, s0, 242637; GFX11-NEXT: s_lshr_b32 s20, s2, 162638; GFX11-NEXT: s_lshr_b32 s21, s2, 242639; GFX11-NEXT: s_lshr_b32 s14, s7, 162640; GFX11-NEXT: s_lshr_b32 s15, s7, 242641; GFX11-NEXT: s_bfe_u32 s27, s7, 0x800082642; GFX11-NEXT: s_add_i32 s17, s17, s172643; GFX11-NEXT: s_add_i32 s16, s16, s162644; GFX11-NEXT: s_lshr_b32 s18, s1, 162645; GFX11-NEXT: s_lshr_b32 s19, s1, 242646; GFX11-NEXT: s_lshr_b32 s22, s3, 162647; GFX11-NEXT: s_lshr_b32 s23, s3, 242648; GFX11-NEXT: s_bfe_u32 s29, s1, 0x800082649; GFX11-NEXT: s_bfe_u32 s30, s3, 0x800082650; GFX11-NEXT: s_add_i32 s21, s21, s212651; GFX11-NEXT: s_add_i32 s20, s20, s202652; GFX11-NEXT: s_lshl_b32 s17, s17, 82653; GFX11-NEXT: s_and_b32 s16, s16, 0xff2654; GFX11-NEXT: s_add_i32 s7, s7, s72655; GFX11-NEXT: s_add_i32 s27, s27, s272656; GFX11-NEXT: s_add_i32 s15, s15, s152657; GFX11-NEXT: s_add_i32 s14, s14, s142658; GFX11-NEXT: s_add_i32 s3, s3, s32659; GFX11-NEXT: s_add_i32 s30, s30, s302660; GFX11-NEXT: s_add_i32 s23, s23, s232661; GFX11-NEXT: s_add_i32 s22, s22, s222662; GFX11-NEXT: s_lshl_b32 s21, s21, 82663; GFX11-NEXT: s_and_b32 s20, s20, 0xff2664; GFX11-NEXT: s_add_i32 s1, s1, s12665; GFX11-NEXT: s_add_i32 s29, s29, s292666; GFX11-NEXT: s_add_i32 s19, s19, s192667; GFX11-NEXT: s_add_i32 s18, s18, s182668; GFX11-NEXT: s_lshr_b32 s10, s5, 162669; GFX11-NEXT: s_lshr_b32 s11, s5, 242670; GFX11-NEXT: s_lshr_b32 s12, s6, 162671; GFX11-NEXT: s_lshr_b32 s13, s6, 242672; GFX11-NEXT: s_or_b32 s16, s16, s172673; GFX11-NEXT: s_and_b32 s7, s7, 0xff2674; GFX11-NEXT: s_lshl_b32 s17, s27, 82675; GFX11-NEXT: s_lshl_b32 s15, s15, 82676; GFX11-NEXT: s_and_b32 s14, s14, 0xff2677; GFX11-NEXT: s_and_b32 s3, s3, 0xff2678; GFX11-NEXT: s_lshl_b32 s30, s30, 82679; GFX11-NEXT: s_lshl_b32 s23, s23, 82680; GFX11-NEXT: s_and_b32 s22, s22, 0xff2681; GFX11-NEXT: s_or_b32 s20, s20, s212682; GFX11-NEXT: s_and_b32 s1, s1, 0xff2683; GFX11-NEXT: s_lshl_b32 s21, s29, 82684; GFX11-NEXT: s_lshl_b32 s19, s19, 82685; GFX11-NEXT: s_and_b32 s18, s18, 0xff2686; GFX11-NEXT: s_lshr_b32 s8, s4, 162687; GFX11-NEXT: s_lshr_b32 s9, s4, 242688; GFX11-NEXT: s_bfe_u32 s24, s4, 0x800082689; GFX11-NEXT: s_bfe_u32 s25, s5, 0x800082690; GFX11-NEXT: s_bfe_u32 s26, s6, 0x800082691; GFX11-NEXT: s_or_b32 s7, s7, s172692; GFX11-NEXT: s_or_b32 s14, s14, s152693; GFX11-NEXT: s_add_i32 s13, s13, s132694; GFX11-NEXT: s_add_i32 s12, s12, s122695; GFX11-NEXT: s_add_i32 s11, s11, s112696; GFX11-NEXT: s_add_i32 s10, s10, s102697; GFX11-NEXT: s_bfe_u32 s28, s0, 0x800082698; GFX11-NEXT: s_or_b32 s3, s3, s302699; GFX11-NEXT: s_or_b32 s22, s22, s232700; GFX11-NEXT: s_bfe_u32 s23, s2, 0x800082701; GFX11-NEXT: s_or_b32 s1, s1, s212702; GFX11-NEXT: s_or_b32 s18, s18, s192703; GFX11-NEXT: s_and_b32 s7, s7, 0xffff2704; GFX11-NEXT: s_lshl_b32 s14, s14, 162705; GFX11-NEXT: s_add_i32 s6, s6, s62706; GFX11-NEXT: s_add_i32 s26, s26, s262707; GFX11-NEXT: s_lshl_b32 s13, s13, 82708; GFX11-NEXT: s_and_b32 s12, s12, 0xff2709; GFX11-NEXT: s_add_i32 s5, s5, s52710; GFX11-NEXT: s_add_i32 s25, s25, s252711; GFX11-NEXT: s_lshl_b32 s11, s11, 82712; GFX11-NEXT: s_and_b32 s10, s10, 0xff2713; GFX11-NEXT: s_add_i32 s4, s4, s42714; GFX11-NEXT: s_add_i32 s24, s24, s242715; GFX11-NEXT: s_add_i32 s9, s9, s92716; GFX11-NEXT: s_add_i32 s8, s8, s82717; GFX11-NEXT: s_and_b32 s3, s3, 0xffff2718; GFX11-NEXT: s_lshl_b32 s22, s22, 162719; GFX11-NEXT: s_add_i32 s2, s2, s22720; GFX11-NEXT: s_add_i32 s23, s23, s232721; GFX11-NEXT: s_and_b32 s1, s1, 0xffff2722; GFX11-NEXT: s_lshl_b32 s18, s18, 162723; GFX11-NEXT: s_add_i32 s0, s0, s02724; GFX11-NEXT: s_add_i32 s28, s28, s282725; GFX11-NEXT: s_or_b32 s7, s7, s142726; GFX11-NEXT: s_and_b32 s6, s6, 0xff2727; GFX11-NEXT: s_lshl_b32 s14, s26, 82728; GFX11-NEXT: s_or_b32 s12, s12, s132729; GFX11-NEXT: s_and_b32 s5, s5, 0xff2730; GFX11-NEXT: s_lshl_b32 s13, s25, 82731; GFX11-NEXT: s_or_b32 s10, s10, s112732; GFX11-NEXT: s_and_b32 s4, s4, 0xff2733; GFX11-NEXT: s_lshl_b32 s11, s24, 82734; GFX11-NEXT: s_lshl_b32 s9, s9, 82735; GFX11-NEXT: s_and_b32 s8, s8, 0xff2736; GFX11-NEXT: s_or_b32 s3, s3, s222737; GFX11-NEXT: s_and_b32 s2, s2, 0xff2738; GFX11-NEXT: s_lshl_b32 s22, s23, 82739; GFX11-NEXT: s_or_b32 s1, s1, s182740; GFX11-NEXT: s_and_b32 s0, s0, 0xff2741; GFX11-NEXT: s_lshl_b32 s18, s28, 82742; GFX11-NEXT: s_or_b32 s6, s6, s142743; GFX11-NEXT: s_or_b32 s5, s5, s132744; GFX11-NEXT: s_or_b32 s4, s4, s112745; GFX11-NEXT: s_or_b32 s8, s8, s92746; GFX11-NEXT: s_or_b32 s2, s2, s222747; GFX11-NEXT: s_or_b32 s0, s0, s182748; GFX11-NEXT: s_and_b32 s6, s6, 0xffff2749; GFX11-NEXT: s_lshl_b32 s12, s12, 162750; GFX11-NEXT: s_and_b32 s5, s5, 0xffff2751; GFX11-NEXT: s_and_b32 s4, s4, 0xffff2752; GFX11-NEXT: s_lshl_b32 s8, s8, 162753; GFX11-NEXT: s_lshl_b32 s9, s10, 162754; GFX11-NEXT: s_and_b32 s2, s2, 0xffff2755; GFX11-NEXT: s_lshl_b32 s20, s20, 162756; GFX11-NEXT: s_and_b32 s0, s0, 0xffff2757; GFX11-NEXT: s_lshl_b32 s16, s16, 162758; GFX11-NEXT: s_or_b32 s6, s6, s122759; GFX11-NEXT: s_or_b32 s4, s4, s82760; GFX11-NEXT: s_or_b32 s5, s5, s92761; GFX11-NEXT: s_or_b32 s2, s2, s202762; GFX11-NEXT: s_or_b32 s0, s0, s162763; GFX11-NEXT: v_dual_mov_b32 v8, 16 :: v_dual_mov_b32 v5, s12764; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s52765; GFX11-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s72766; GFX11-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v4, s02767; GFX11-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v7, s32768; GFX11-NEXT: v_dual_mov_b32 v6, s2 :: v_dual_mov_b32 v11, 02769; GFX11-NEXT: s_clause 0x12770; GFX11-NEXT: global_store_b128 v[8:9], v[0:3], off2771; GFX11-NEXT: global_store_b128 v[10:11], v[4:7], off2772; GFX11-NEXT: s_endpgm2773;2774; GFX1250-LABEL: amd_kernel_v32i8:2775; GFX1250: ; %bb.0: ; %entry2776; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12777; GFX1250-NEXT: s_load_b256 s[8:15], s[4:5], 0x242778; GFX1250-NEXT: v_mov_b64_e32 v[8:9], 162779; GFX1250-NEXT: v_mov_b64_e32 v[10:11], 02780; GFX1250-NEXT: s_wait_kmcnt 0x02781; GFX1250-NEXT: s_lshr_b32 s16, s8, 162782; GFX1250-NEXT: s_lshr_b32 s17, s8, 242783; GFX1250-NEXT: s_lshr_b32 s6, s15, 162784; GFX1250-NEXT: s_lshr_b32 s7, s15, 242785; GFX1250-NEXT: s_bfe_u32 s27, s15, 0x800082786; GFX1250-NEXT: s_add_co_i32 s17, s17, s172787; GFX1250-NEXT: s_add_co_i32 s16, s16, s162788; GFX1250-NEXT: s_lshl_b32 s17, s17, 82789; GFX1250-NEXT: s_and_b32 s16, s16, 0xff2790; GFX1250-NEXT: s_add_co_i32 s15, s15, s152791; GFX1250-NEXT: s_add_co_i32 s27, s27, s272792; GFX1250-NEXT: s_add_co_i32 s7, s7, s72793; GFX1250-NEXT: s_add_co_i32 s6, s6, s62794; GFX1250-NEXT: s_or_b32 s16, s16, s172795; GFX1250-NEXT: s_and_b32 s15, s15, 0xff2796; GFX1250-NEXT: s_lshl_b32 s17, s27, 82797; GFX1250-NEXT: s_lshl_b32 s7, s7, 82798; GFX1250-NEXT: s_and_b32 s6, s6, 0xff2799; GFX1250-NEXT: s_or_b32 s15, s15, s172800; GFX1250-NEXT: s_or_b32 s6, s6, s72801; GFX1250-NEXT: s_bfe_u32 s26, s14, 0x800082802; GFX1250-NEXT: s_and_b32 s7, s15, 0xffff2803; GFX1250-NEXT: s_lshl_b32 s6, s6, 162804; GFX1250-NEXT: s_lshr_b32 s20, s10, 162805; GFX1250-NEXT: s_lshr_b32 s21, s10, 242806; GFX1250-NEXT: s_lshr_b32 s4, s14, 162807; GFX1250-NEXT: s_lshr_b32 s5, s14, 242808; GFX1250-NEXT: s_or_b32 s6, s7, s62809; GFX1250-NEXT: s_add_co_i32 s7, s14, s142810; GFX1250-NEXT: s_add_co_i32 s26, s26, s262811; GFX1250-NEXT: s_lshr_b32 s18, s9, 162812; GFX1250-NEXT: s_lshr_b32 s19, s9, 242813; GFX1250-NEXT: s_lshr_b32 s22, s11, 162814; GFX1250-NEXT: s_lshr_b32 s23, s11, 242815; GFX1250-NEXT: s_bfe_u32 s29, s9, 0x800082816; GFX1250-NEXT: s_bfe_u32 s30, s11, 0x800082817; GFX1250-NEXT: s_add_co_i32 s21, s21, s212818; GFX1250-NEXT: s_add_co_i32 s20, s20, s202819; GFX1250-NEXT: s_lshr_b32 s2, s13, 162820; GFX1250-NEXT: s_lshr_b32 s3, s13, 242821; GFX1250-NEXT: s_and_b32 s7, s7, 0xff2822; GFX1250-NEXT: s_lshl_b32 s14, s26, 82823; GFX1250-NEXT: s_add_co_i32 s5, s5, s52824; GFX1250-NEXT: s_add_co_i32 s4, s4, s42825; GFX1250-NEXT: s_add_co_i32 s11, s11, s112826; GFX1250-NEXT: s_add_co_i32 s30, s30, s302827; GFX1250-NEXT: s_add_co_i32 s23, s23, s232828; GFX1250-NEXT: s_add_co_i32 s22, s22, s222829; GFX1250-NEXT: s_lshl_b32 s21, s21, 82830; GFX1250-NEXT: s_and_b32 s20, s20, 0xff2831; GFX1250-NEXT: s_add_co_i32 s9, s9, s92832; GFX1250-NEXT: s_add_co_i32 s29, s29, s292833; GFX1250-NEXT: s_add_co_i32 s19, s19, s192834; GFX1250-NEXT: s_add_co_i32 s18, s18, s182835; GFX1250-NEXT: s_bfe_u32 s25, s13, 0x800082836; GFX1250-NEXT: s_lshl_b32 s5, s5, 82837; GFX1250-NEXT: s_and_b32 s4, s4, 0xff2838; GFX1250-NEXT: s_or_b32 s7, s7, s142839; GFX1250-NEXT: s_add_co_i32 s3, s3, s32840; GFX1250-NEXT: s_add_co_i32 s2, s2, s22841; GFX1250-NEXT: s_and_b32 s11, s11, 0xff2842; GFX1250-NEXT: s_lshl_b32 s30, s30, 82843; GFX1250-NEXT: s_lshl_b32 s23, s23, 82844; GFX1250-NEXT: s_and_b32 s22, s22, 0xff2845; GFX1250-NEXT: s_or_b32 s20, s20, s212846; GFX1250-NEXT: s_and_b32 s9, s9, 0xff2847; GFX1250-NEXT: s_lshl_b32 s21, s29, 82848; GFX1250-NEXT: s_lshl_b32 s19, s19, 82849; GFX1250-NEXT: s_and_b32 s18, s18, 0xff2850; GFX1250-NEXT: s_lshr_b32 s0, s12, 162851; GFX1250-NEXT: s_lshr_b32 s1, s12, 242852; GFX1250-NEXT: s_bfe_u32 s24, s12, 0x800082853; GFX1250-NEXT: s_or_b32 s4, s4, s52854; GFX1250-NEXT: s_and_b32 s5, s7, 0xffff2855; GFX1250-NEXT: s_add_co_i32 s7, s13, s132856; GFX1250-NEXT: s_add_co_i32 s25, s25, s252857; GFX1250-NEXT: s_lshl_b32 s3, s3, 82858; GFX1250-NEXT: s_and_b32 s2, s2, 0xff2859; GFX1250-NEXT: s_bfe_u32 s28, s8, 0x800082860; GFX1250-NEXT: s_or_b32 s11, s11, s302861; GFX1250-NEXT: s_or_b32 s22, s22, s232862; GFX1250-NEXT: s_bfe_u32 s23, s10, 0x800082863; GFX1250-NEXT: s_or_b32 s9, s9, s212864; GFX1250-NEXT: s_or_b32 s18, s18, s192865; GFX1250-NEXT: s_lshl_b32 s4, s4, 162866; GFX1250-NEXT: s_and_b32 s7, s7, 0xff2867; GFX1250-NEXT: s_lshl_b32 s13, s25, 82868; GFX1250-NEXT: s_or_b32 s2, s2, s32869; GFX1250-NEXT: s_add_co_i32 s3, s12, s122870; GFX1250-NEXT: s_add_co_i32 s24, s24, s242871; GFX1250-NEXT: s_add_co_i32 s1, s1, s12872; GFX1250-NEXT: s_add_co_i32 s0, s0, s02873; GFX1250-NEXT: s_and_b32 s11, s11, 0xffff2874; GFX1250-NEXT: s_lshl_b32 s22, s22, 162875; GFX1250-NEXT: s_add_co_i32 s10, s10, s102876; GFX1250-NEXT: s_add_co_i32 s23, s23, s232877; GFX1250-NEXT: s_and_b32 s9, s9, 0xffff2878; GFX1250-NEXT: s_lshl_b32 s18, s18, 162879; GFX1250-NEXT: s_add_co_i32 s8, s8, s82880; GFX1250-NEXT: s_add_co_i32 s28, s28, s282881; GFX1250-NEXT: s_or_b32 s4, s5, s42882; GFX1250-NEXT: s_or_b32 s5, s7, s132883; GFX1250-NEXT: s_and_b32 s3, s3, 0xff2884; GFX1250-NEXT: s_lshl_b32 s7, s24, 82885; GFX1250-NEXT: s_lshl_b32 s1, s1, 82886; GFX1250-NEXT: s_and_b32 s0, s0, 0xff2887; GFX1250-NEXT: s_or_b32 s11, s11, s222888; GFX1250-NEXT: s_and_b32 s10, s10, 0xff2889; GFX1250-NEXT: s_lshl_b32 s22, s23, 82890; GFX1250-NEXT: s_or_b32 s9, s9, s182891; GFX1250-NEXT: s_and_b32 s8, s8, 0xff2892; GFX1250-NEXT: s_lshl_b32 s18, s28, 82893; GFX1250-NEXT: s_or_b32 s3, s3, s72894; GFX1250-NEXT: s_or_b32 s0, s0, s12895; GFX1250-NEXT: s_or_b32 s10, s10, s222896; GFX1250-NEXT: s_or_b32 s8, s8, s182897; GFX1250-NEXT: s_and_b32 s5, s5, 0xffff2898; GFX1250-NEXT: s_and_b32 s1, s3, 0xffff2899; GFX1250-NEXT: s_lshl_b32 s0, s0, 162900; GFX1250-NEXT: s_lshl_b32 s2, s2, 162901; GFX1250-NEXT: s_and_b32 s10, s10, 0xffff2902; GFX1250-NEXT: s_lshl_b32 s20, s20, 162903; GFX1250-NEXT: s_and_b32 s8, s8, 0xffff2904; GFX1250-NEXT: s_lshl_b32 s16, s16, 162905; GFX1250-NEXT: s_or_b32 s0, s1, s02906; GFX1250-NEXT: s_or_b32 s1, s5, s22907; GFX1250-NEXT: s_or_b32 s10, s10, s202908; GFX1250-NEXT: s_or_b32 s8, s8, s162909; GFX1250-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s12910; GFX1250-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s62911; GFX1250-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s92912; GFX1250-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s112913; GFX1250-NEXT: s_clause 0x12914; GFX1250-NEXT: global_store_b128 v[8:9], v[0:3], off2915; GFX1250-NEXT: global_store_b128 v[10:11], v[4:7], off2916; GFX1250-NEXT: s_endpgm2917entry:2918 %add = add <32 x i8> %arg0, %arg02919 store <32 x i8> %add, ptr addrspace(1) null2920 ret void2921}2922 2923define amdgpu_cs void @amdgpu_cs_i1(i1 %arg0) {2924; SI-LABEL: amdgpu_cs_i1:2925; SI: ; %bb.0:2926; SI-NEXT: v_and_b32_e32 v0, 1, v02927; SI-NEXT: s_mov_b32 s3, 0xf0002928; SI-NEXT: s_mov_b32 s2, -12929; SI-NEXT: buffer_store_byte v0, off, s[0:3], 02930; SI-NEXT: s_endpgm2931;2932; VI-LABEL: amdgpu_cs_i1:2933; VI: ; %bb.0:2934; VI-NEXT: v_and_b32_e32 v0, 1, v02935; VI-NEXT: flat_store_byte v[0:1], v02936; VI-NEXT: s_endpgm2937;2938; GFX11-LABEL: amdgpu_cs_i1:2939; GFX11: ; %bb.0:2940; GFX11-NEXT: v_and_b32_e32 v0, 1, v02941; GFX11-NEXT: global_store_b8 v[0:1], v0, off2942; GFX11-NEXT: s_endpgm2943;2944; GFX1250-LABEL: amdgpu_cs_i1:2945; GFX1250: ; %bb.0:2946; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12947; GFX1250-NEXT: v_and_b32_e32 v0, 1, v02948; GFX1250-NEXT: global_store_b8 v[0:1], v0, off2949; GFX1250-NEXT: s_endpgm2950 store i1 %arg0, ptr addrspace(1) poison2951 ret void2952}2953 2954define amdgpu_cs void @amdgpu_cs_v8i1(<8 x i1> %arg0) {2955; SI-LABEL: amdgpu_cs_v8i1:2956; SI: ; %bb.0:2957; SI-NEXT: v_lshlrev_b32_e32 v7, 3, v72958; SI-NEXT: v_and_b32_e32 v6, 1, v62959; SI-NEXT: v_lshlrev_b32_e32 v5, 1, v52960; SI-NEXT: v_and_b32_e32 v4, 1, v42961; SI-NEXT: v_lshlrev_b32_e32 v3, 3, v32962; SI-NEXT: v_and_b32_e32 v2, 1, v22963; SI-NEXT: v_lshlrev_b32_e32 v1, 1, v12964; SI-NEXT: v_and_b32_e32 v0, 1, v02965; SI-NEXT: s_mov_b32 s3, 0xf0002966; SI-NEXT: v_lshlrev_b32_e32 v6, 2, v62967; SI-NEXT: v_or_b32_e32 v4, v4, v52968; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v22969; SI-NEXT: v_or_b32_e32 v0, v0, v12970; SI-NEXT: v_or_b32_e32 v1, v7, v62971; SI-NEXT: v_and_b32_e32 v4, 3, v42972; SI-NEXT: v_or_b32_e32 v2, v3, v22973; SI-NEXT: v_and_b32_e32 v0, 3, v02974; SI-NEXT: v_or_b32_e32 v1, v4, v12975; SI-NEXT: v_or_b32_e32 v0, v0, v22976; SI-NEXT: v_lshlrev_b32_e32 v1, 4, v12977; SI-NEXT: v_and_b32_e32 v0, 15, v02978; SI-NEXT: v_or_b32_e32 v0, v0, v12979; SI-NEXT: s_mov_b32 s2, -12980; SI-NEXT: buffer_store_byte v0, off, s[0:3], 02981; SI-NEXT: s_endpgm2982;2983; VI-LABEL: amdgpu_cs_v8i1:2984; VI: ; %bb.0:2985; VI-NEXT: v_and_b32_e32 v6, 1, v62986; VI-NEXT: v_lshlrev_b16_e32 v5, 1, v52987; VI-NEXT: v_and_b32_e32 v4, 1, v42988; VI-NEXT: v_and_b32_e32 v2, 1, v22989; VI-NEXT: v_lshlrev_b16_e32 v1, 1, v12990; VI-NEXT: v_and_b32_e32 v0, 1, v02991; VI-NEXT: v_lshlrev_b16_e32 v7, 3, v72992; VI-NEXT: v_lshlrev_b16_e32 v6, 2, v62993; VI-NEXT: v_or_b32_e32 v4, v4, v52994; VI-NEXT: v_lshlrev_b16_e32 v3, 3, v32995; VI-NEXT: v_lshlrev_b16_e32 v2, 2, v22996; VI-NEXT: v_or_b32_e32 v0, v0, v12997; VI-NEXT: v_or_b32_e32 v6, v7, v62998; VI-NEXT: v_and_b32_e32 v4, 3, v42999; VI-NEXT: v_or_b32_e32 v2, v3, v23000; VI-NEXT: v_and_b32_e32 v0, 3, v03001; VI-NEXT: v_or_b32_e32 v4, v4, v63002; VI-NEXT: v_or_b32_e32 v0, v0, v23003; VI-NEXT: v_lshlrev_b16_e32 v4, 4, v43004; VI-NEXT: v_and_b32_e32 v0, 15, v03005; VI-NEXT: v_or_b32_e32 v0, v0, v43006; VI-NEXT: flat_store_byte v[0:1], v03007; VI-NEXT: s_endpgm3008;3009; GFX11-TRUE16-LABEL: amdgpu_cs_v8i1:3010; GFX11-TRUE16: ; %bb.0:3011; GFX11-TRUE16-NEXT: v_and_b16 v6.l, v6.l, 13012; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 1, v5.l3013; GFX11-TRUE16-NEXT: v_and_b16 v0.h, v4.l, 13014; GFX11-TRUE16-NEXT: v_and_b16 v1.h, v2.l, 13015; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 1, v1.l3016; GFX11-TRUE16-NEXT: v_and_b16 v0.l, v0.l, 13017; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 3, v7.l3018; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 2, v6.l3019; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v0.h, v4.h3020; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 3, v3.l3021; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 2, v1.h3022; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l3023; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v5.h, v2.l3024; GFX11-TRUE16-NEXT: v_and_b16 v0.h, v0.h, 33025; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3026; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v2.h, v1.h3027; GFX11-TRUE16-NEXT: v_and_b16 v0.l, v0.l, 33028; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)3029; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v0.h, v1.l3030; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.h3031; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3032; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 4, v0.h3033; GFX11-TRUE16-NEXT: v_and_b16 v0.l, v0.l, 153034; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)3035; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h3036; GFX11-TRUE16-NEXT: global_store_b8 v[0:1], v0, off3037; GFX11-TRUE16-NEXT: s_endpgm3038;3039; GFX11-FAKE16-LABEL: amdgpu_cs_v8i1:3040; GFX11-FAKE16: ; %bb.0:3041; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 1, v63042; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 1, v53043; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 1, v43044; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 1, v23045; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 1, v13046; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v03047; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 3, v73048; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 2, v63049; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v53050; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 3, v33051; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 2, v23052; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v13053; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v7, v63054; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 3, v43055; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3056; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v23057; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 3, v03058; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)3059; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v13060; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v23061; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3062; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 4, v13063; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 15, v03064; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)3065; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v13066; GFX11-FAKE16-NEXT: global_store_b8 v[0:1], v0, off3067; GFX11-FAKE16-NEXT: s_endpgm3068;3069; GFX1250-TRUE16-LABEL: amdgpu_cs_v8i1:3070; GFX1250-TRUE16: ; %bb.0:3071; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 13072; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v2.h, 3, v3.l3073; GFX1250-TRUE16-NEXT: v_and_b16 v3.l, v6.l, 13074; GFX1250-TRUE16-NEXT: v_and_b16 v2.l, v2.l, 13075; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v1.h, 3, v7.l3076; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v3.h, 1, v5.l3077; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v1.l, 1, v1.l3078; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v3.l, 2, v3.l3079; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v2.l, 2, v2.l3080; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)3081; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, 1 bitop3:0xec3082; GFX1250-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v3.l3083; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.h, v4.l, v3.h, 1 bitop3:0xec3084; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)3085; GFX1250-TRUE16-NEXT: v_or_b16 v2.l, v2.h, v2.l3086; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.h, v1.h, v0.h, 3 bitop3:0xec3087; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3088; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v2.l, 3 bitop3:0xec3089; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v0.h, 4, v0.h3090; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)3091; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v0.h, 15 bitop3:0xec3092; GFX1250-TRUE16-NEXT: global_store_b8 v[0:1], v0, off3093; GFX1250-TRUE16-NEXT: s_endpgm3094;3095; GFX1250-FAKE16-LABEL: amdgpu_cs_v8i1:3096; GFX1250-FAKE16: ; %bb.0:3097; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 13098; GFX1250-FAKE16-NEXT: v_and_b32_e32 v6, 1, v63099; GFX1250-FAKE16-NEXT: v_and_b32_e32 v2, 1, v23100; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v7, 3, v73101; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v5, 1, v53102; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v3, 3, v33103; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v6, 2, v63104; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v2, 2, v23105; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v1, 1, v13106; GFX1250-FAKE16-NEXT: v_bitop3_b16 v4, v4, v5, 1 bitop3:0xec3107; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3108; GFX1250-FAKE16-NEXT: v_or_b32_e32 v6, v7, v63109; GFX1250-FAKE16-NEXT: v_or_b32_e32 v2, v3, v23110; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)3111; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, 1 bitop3:0xec3112; GFX1250-FAKE16-NEXT: v_bitop3_b16 v1, v4, v6, 3 bitop3:0xec3113; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3114; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v2, 3 bitop3:0xec3115; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v1, 4, v13116; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)3117; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, 15 bitop3:0xec3118; GFX1250-FAKE16-NEXT: global_store_b8 v[0:1], v0, off3119; GFX1250-FAKE16-NEXT: s_endpgm3120 store <8 x i1> %arg0, ptr addrspace(1) poison3121 ret void3122}3123 3124define amdgpu_cs void @amdgpu_cs_v16i1(<16 x i1> %arg0) {3125; SI-LABEL: amdgpu_cs_v16i1:3126; SI: ; %bb.0:3127; SI-NEXT: v_lshlrev_b32_e32 v15, 3, v153128; SI-NEXT: v_and_b32_e32 v14, 1, v143129; SI-NEXT: v_lshlrev_b32_e32 v13, 1, v133130; SI-NEXT: v_and_b32_e32 v12, 1, v123131; SI-NEXT: v_lshlrev_b32_e32 v11, 3, v113132; SI-NEXT: v_and_b32_e32 v10, 1, v103133; SI-NEXT: v_lshlrev_b32_e32 v9, 1, v93134; SI-NEXT: v_and_b32_e32 v8, 1, v83135; SI-NEXT: v_lshlrev_b32_e32 v7, 3, v73136; SI-NEXT: v_and_b32_e32 v6, 1, v63137; SI-NEXT: v_lshlrev_b32_e32 v5, 1, v53138; SI-NEXT: v_and_b32_e32 v4, 1, v43139; SI-NEXT: v_lshlrev_b32_e32 v3, 3, v33140; SI-NEXT: v_and_b32_e32 v2, 1, v23141; SI-NEXT: v_lshlrev_b32_e32 v1, 1, v13142; SI-NEXT: v_and_b32_e32 v0, 1, v03143; SI-NEXT: s_mov_b32 s3, 0xf0003144; SI-NEXT: v_lshlrev_b32_e32 v14, 2, v143145; SI-NEXT: v_or_b32_e32 v12, v12, v133146; SI-NEXT: v_lshlrev_b32_e32 v10, 2, v103147; SI-NEXT: v_or_b32_e32 v8, v8, v93148; SI-NEXT: v_lshlrev_b32_e32 v6, 2, v63149; SI-NEXT: v_or_b32_e32 v4, v4, v53150; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v23151; SI-NEXT: v_or_b32_e32 v0, v0, v13152; SI-NEXT: v_or_b32_e32 v1, v15, v143153; SI-NEXT: v_and_b32_e32 v5, 3, v123154; SI-NEXT: v_or_b32_e32 v9, v11, v103155; SI-NEXT: v_and_b32_e32 v8, 3, v83156; SI-NEXT: v_or_b32_e32 v6, v7, v63157; SI-NEXT: v_and_b32_e32 v4, 3, v43158; SI-NEXT: v_or_b32_e32 v2, v3, v23159; SI-NEXT: v_and_b32_e32 v0, 3, v03160; SI-NEXT: v_or_b32_e32 v1, v5, v13161; SI-NEXT: v_or_b32_e32 v3, v8, v93162; SI-NEXT: v_or_b32_e32 v4, v4, v63163; SI-NEXT: v_or_b32_e32 v0, v0, v23164; SI-NEXT: v_lshlrev_b32_e32 v1, 12, v13165; SI-NEXT: v_and_b32_e32 v2, 15, v33166; SI-NEXT: v_lshlrev_b32_e32 v3, 4, v43167; SI-NEXT: v_and_b32_e32 v0, 15, v03168; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v23169; SI-NEXT: v_or_b32_e32 v0, v0, v33170; SI-NEXT: v_or_b32_e32 v1, v1, v23171; SI-NEXT: v_and_b32_e32 v0, 0xff, v03172; SI-NEXT: v_or_b32_e32 v0, v0, v13173; SI-NEXT: s_mov_b32 s2, -13174; SI-NEXT: buffer_store_short v0, off, s[0:3], 03175; SI-NEXT: s_endpgm3176;3177; VI-LABEL: amdgpu_cs_v16i1:3178; VI: ; %bb.0:3179; VI-NEXT: v_and_b32_e32 v14, 1, v143180; VI-NEXT: v_lshlrev_b16_e32 v13, 1, v133181; VI-NEXT: v_and_b32_e32 v12, 1, v123182; VI-NEXT: v_and_b32_e32 v10, 1, v103183; VI-NEXT: v_lshlrev_b16_e32 v9, 1, v93184; VI-NEXT: v_and_b32_e32 v8, 1, v83185; VI-NEXT: v_and_b32_e32 v6, 1, v63186; VI-NEXT: v_lshlrev_b16_e32 v5, 1, v53187; VI-NEXT: v_and_b32_e32 v4, 1, v43188; VI-NEXT: v_and_b32_e32 v2, 1, v23189; VI-NEXT: v_lshlrev_b16_e32 v1, 1, v13190; VI-NEXT: v_and_b32_e32 v0, 1, v03191; VI-NEXT: v_lshlrev_b16_e32 v15, 3, v153192; VI-NEXT: v_lshlrev_b16_e32 v14, 2, v143193; VI-NEXT: v_or_b32_e32 v12, v12, v133194; VI-NEXT: v_lshlrev_b16_e32 v11, 3, v113195; VI-NEXT: v_lshlrev_b16_e32 v10, 2, v103196; VI-NEXT: v_or_b32_e32 v8, v8, v93197; VI-NEXT: v_lshlrev_b16_e32 v7, 3, v73198; VI-NEXT: v_lshlrev_b16_e32 v6, 2, v63199; VI-NEXT: v_or_b32_e32 v4, v4, v53200; VI-NEXT: v_lshlrev_b16_e32 v3, 3, v33201; VI-NEXT: v_lshlrev_b16_e32 v2, 2, v23202; VI-NEXT: v_or_b32_e32 v0, v0, v13203; VI-NEXT: v_or_b32_e32 v14, v15, v143204; VI-NEXT: v_and_b32_e32 v12, 3, v123205; VI-NEXT: v_or_b32_e32 v10, v11, v103206; VI-NEXT: v_and_b32_e32 v8, 3, v83207; VI-NEXT: v_or_b32_e32 v6, v7, v63208; VI-NEXT: v_and_b32_e32 v4, 3, v43209; VI-NEXT: v_or_b32_e32 v2, v3, v23210; VI-NEXT: v_and_b32_e32 v0, 3, v03211; VI-NEXT: v_or_b32_e32 v12, v12, v143212; VI-NEXT: v_or_b32_e32 v8, v8, v103213; VI-NEXT: v_mov_b32_e32 v9, 153214; VI-NEXT: v_or_b32_e32 v4, v4, v63215; VI-NEXT: v_or_b32_e32 v0, v0, v23216; VI-NEXT: v_lshlrev_b16_e32 v12, 12, v123217; VI-NEXT: v_and_b32_sdwa v8, v8, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3218; VI-NEXT: v_lshlrev_b16_e32 v4, 4, v43219; VI-NEXT: v_and_b32_e32 v0, 15, v03220; VI-NEXT: v_or_b32_e32 v8, v12, v83221; VI-NEXT: v_or_b32_e32 v0, v0, v43222; VI-NEXT: v_or_b32_sdwa v0, v0, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD3223; VI-NEXT: flat_store_short v[0:1], v03224; VI-NEXT: s_endpgm3225;3226; GFX11-TRUE16-LABEL: amdgpu_cs_v16i1:3227; GFX11-TRUE16: ; %bb.0:3228; GFX11-TRUE16-NEXT: v_and_b16 v10.l, v10.l, 13229; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 1, v9.l3230; GFX11-TRUE16-NEXT: v_and_b16 v8.l, v8.l, 13231; GFX11-TRUE16-NEXT: v_and_b16 v6.l, v6.l, 13232; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 1, v5.l3233; GFX11-TRUE16-NEXT: v_and_b16 v0.h, v4.l, 13234; GFX11-TRUE16-NEXT: v_and_b16 v1.h, v2.l, 13235; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 1, v1.l3236; GFX11-TRUE16-NEXT: v_and_b16 v0.l, v0.l, 13237; GFX11-TRUE16-NEXT: v_and_b16 v14.l, v14.l, 13238; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.l, 1, v13.l3239; GFX11-TRUE16-NEXT: v_and_b16 v12.l, v12.l, 13240; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 3, v11.l3241; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 2, v10.l3242; GFX11-TRUE16-NEXT: v_or_b16 v5.h, v8.l, v9.l3243; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.l, 3, v7.l3244; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 2, v6.l3245; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v0.h, v4.h3246; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 3, v3.l3247; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 2, v1.h3248; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l3249; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.h, 3, v15.l3250; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.h, 2, v14.l3251; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v12.l, v13.l3252; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v9.h, v10.l3253; GFX11-TRUE16-NEXT: v_and_b16 v1.l, v5.h, 33254; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v7.l, v2.l3255; GFX11-TRUE16-NEXT: v_and_b16 v0.h, v0.h, 33256; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v2.h, v1.h3257; GFX11-TRUE16-NEXT: v_and_b16 v0.l, v0.l, 33258; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v12.h, v10.h3259; GFX11-TRUE16-NEXT: v_and_b16 v3.l, v8.h, 33260; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.l, v6.h3261; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v0.h, v2.l3262; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.h3263; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3264; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v3.l, v2.h3265; GFX11-TRUE16-NEXT: v_and_b16 v1.l, v1.l, 153266; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3267; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 4, v0.h3268; GFX11-TRUE16-NEXT: v_and_b16 v0.l, v0.l, 153269; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3270; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 12, v1.h3271; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l3272; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)3273; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h3274; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l3275; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)3276; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l3277; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h3278; GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v0, off3279; GFX11-TRUE16-NEXT: s_endpgm3280;3281; GFX11-FAKE16-LABEL: amdgpu_cs_v16i1:3282; GFX11-FAKE16: ; %bb.0:3283; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 1, v103284; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 1, v93285; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 1, v83286; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 1, v63287; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 1, v53288; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 1, v43289; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 1, v23290; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 1, v13291; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v03292; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 1, v143293; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 1, v133294; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 1, v123295; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 3, v113296; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 2, v103297; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v93298; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 3, v73299; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 2, v63300; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v53301; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 3, v33302; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 2, v23303; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v13304; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 3, v153305; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 2, v143306; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v133307; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v103308; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 3, v83309; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v63310; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 3, v43311; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v23312; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 3, v03313; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v15, v143314; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 3, v123315; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v103316; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v53317; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v23318; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3319; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v33320; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 15, v13321; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3322; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 4, v43323; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 15, v03324; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3325; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 12, v23326; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v13327; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)3328; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v33329; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v13330; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)3331; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v03332; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v13333; GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v0, off3334; GFX11-FAKE16-NEXT: s_endpgm3335;3336; GFX1250-TRUE16-LABEL: amdgpu_cs_v16i1:3337; GFX1250-TRUE16: ; %bb.0:3338; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 13339; GFX1250-TRUE16-NEXT: v_and_b16 v2.h, v6.l, 13340; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v1.h, 3, v7.l3341; GFX1250-TRUE16-NEXT: v_and_b16 v4.h, v10.l, 13342; GFX1250-TRUE16-NEXT: v_and_b16 v2.l, v2.l, 13343; GFX1250-TRUE16-NEXT: v_and_b16 v3.h, v8.l, 13344; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v2.h, 2, v2.h3345; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v5.h, 3, v11.l3346; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v4.h, 2, v4.h3347; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v6.l, 3, v15.l3348; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v6.h, 1, v13.l3349; GFX1250-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v2.h3350; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v1.h, 1, v5.l3351; GFX1250-TRUE16-NEXT: v_and_b16 v5.l, v14.l, 13352; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v2.h, 1, v9.l3353; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v3.l, 3, v3.l3354; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v2.l, 2, v2.l3355; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v1.l, 1, v1.l3356; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v5.l, 2, v5.l3357; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.h, v4.l, v1.h, 1 bitop3:0xec3358; GFX1250-TRUE16-NEXT: v_bitop3_b16 v2.h, v3.h, 3, v2.h bitop3:0xc83359; GFX1250-TRUE16-NEXT: v_or_b16 v3.h, v5.h, v4.h3360; GFX1250-TRUE16-NEXT: v_bitop3_b16 v4.h, v12.l, v6.h, 1 bitop3:0xec3361; GFX1250-TRUE16-NEXT: v_or_b16 v4.l, v6.l, v5.l3362; GFX1250-TRUE16-NEXT: v_or_b16 v2.l, v3.l, v2.l3363; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, 1 bitop3:0xec3364; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.h, v1.h, v0.h, 3 bitop3:0xec3365; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.l, v2.h, 15, v3.h bitop3:0xc83366; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.h, v4.h, v4.l, 3 bitop3:0xec3367; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3368; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v2.l, 3 bitop3:0xec3369; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v0.h, 4, v0.h3370; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3371; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l3372; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v1.h, 12, v1.h3373; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)3374; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v0.h, 15 bitop3:0xec3375; GFX1250-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l3376; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)3377; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v0.h, 0xff bitop3:0xec3378; GFX1250-TRUE16-NEXT: global_store_b16 v[0:1], v0, off3379; GFX1250-TRUE16-NEXT: s_endpgm3380;3381; GFX1250-FAKE16-LABEL: amdgpu_cs_v16i1:3382; GFX1250-FAKE16: ; %bb.0:3383; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 13384; GFX1250-FAKE16-NEXT: v_and_b32_e32 v6, 1, v63385; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v7, 3, v73386; GFX1250-FAKE16-NEXT: v_and_b32_e32 v2, 1, v23387; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v5, 1, v53388; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v9, 1, v93389; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v6, 2, v63390; GFX1250-FAKE16-NEXT: v_and_b32_e32 v8, 1, v83391; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v11, 3, v113392; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v13, 1, v133393; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v3, 3, v33394; GFX1250-FAKE16-NEXT: v_or_b32_e32 v6, v7, v63395; GFX1250-FAKE16-NEXT: v_and_b32_e32 v7, 1, v103396; GFX1250-FAKE16-NEXT: v_and_b32_e32 v10, 1, v143397; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v14, 3, v153398; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v2, 2, v23399; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v1, 1, v13400; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v7, 2, v73401; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v10, 2, v103402; GFX1250-FAKE16-NEXT: v_bitop3_b16 v4, v4, v5, 1 bitop3:0xec3403; GFX1250-FAKE16-NEXT: v_bitop3_b16 v5, v8, 3, v9 bitop3:0xc83404; GFX1250-FAKE16-NEXT: v_bitop3_b16 v9, v12, v13, 1 bitop3:0xec3405; GFX1250-FAKE16-NEXT: v_or_b32_e32 v7, v11, v73406; GFX1250-FAKE16-NEXT: v_or_b32_e32 v8, v14, v103407; GFX1250-FAKE16-NEXT: v_or_b32_e32 v2, v3, v23408; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, 1 bitop3:0xec3409; GFX1250-FAKE16-NEXT: v_bitop3_b16 v1, v4, v6, 3 bitop3:0xec3410; GFX1250-FAKE16-NEXT: v_bitop3_b16 v3, v5, 15, v7 bitop3:0xc83411; GFX1250-FAKE16-NEXT: v_bitop3_b16 v4, v9, v8, 3 bitop3:0xec3412; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3413; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v2, 3 bitop3:0xec3414; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v1, 4, v13415; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3416; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v33417; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v3, 12, v43418; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)3419; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, 15 bitop3:0xec3420; GFX1250-FAKE16-NEXT: v_or_b32_e32 v1, v3, v23421; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)3422; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, 0xff bitop3:0xec3423; GFX1250-FAKE16-NEXT: global_store_b16 v[0:1], v0, off3424; GFX1250-FAKE16-NEXT: s_endpgm3425 store <16 x i1> %arg0, ptr addrspace(1) poison3426 ret void3427}3428 3429define amdgpu_cs void @amdgpu_cs_v32i1(<32 x i1> %arg0) {3430; SI-LABEL: amdgpu_cs_v32i1:3431; SI: ; %bb.0:3432; SI-NEXT: v_lshlrev_b32_e32 v29, 1, v293433; SI-NEXT: v_and_b32_e32 v28, 1, v283434; SI-NEXT: v_lshlrev_b32_e32 v25, 1, v253435; SI-NEXT: v_and_b32_e32 v24, 1, v243436; SI-NEXT: v_lshlrev_b32_e32 v21, 1, v213437; SI-NEXT: v_and_b32_e32 v20, 1, v203438; SI-NEXT: v_lshlrev_b32_e32 v17, 1, v173439; SI-NEXT: v_and_b32_e32 v16, 1, v163440; SI-NEXT: v_lshlrev_b32_e32 v13, 1, v133441; SI-NEXT: v_and_b32_e32 v12, 1, v123442; SI-NEXT: v_lshlrev_b32_e32 v9, 1, v93443; SI-NEXT: v_and_b32_e32 v8, 1, v83444; SI-NEXT: v_lshlrev_b32_e32 v5, 1, v53445; SI-NEXT: v_and_b32_e32 v4, 1, v43446; SI-NEXT: v_lshlrev_b32_e32 v1, 1, v13447; SI-NEXT: v_and_b32_e32 v0, 1, v03448; SI-NEXT: v_lshlrev_b32_e32 v31, 3, v313449; SI-NEXT: v_and_b32_e32 v30, 1, v303450; SI-NEXT: v_lshlrev_b32_e32 v27, 3, v273451; SI-NEXT: v_and_b32_e32 v26, 1, v263452; SI-NEXT: v_lshlrev_b32_e32 v23, 3, v233453; SI-NEXT: v_and_b32_e32 v22, 1, v223454; SI-NEXT: v_lshlrev_b32_e32 v19, 3, v193455; SI-NEXT: v_and_b32_e32 v18, 1, v183456; SI-NEXT: v_lshlrev_b32_e32 v15, 3, v153457; SI-NEXT: v_and_b32_e32 v14, 1, v143458; SI-NEXT: v_lshlrev_b32_e32 v11, 3, v113459; SI-NEXT: v_and_b32_e32 v10, 1, v103460; SI-NEXT: v_lshlrev_b32_e32 v7, 3, v73461; SI-NEXT: v_and_b32_e32 v6, 1, v63462; SI-NEXT: v_lshlrev_b32_e32 v3, 3, v33463; SI-NEXT: v_and_b32_e32 v2, 1, v23464; SI-NEXT: s_mov_b32 s3, 0xf0003465; SI-NEXT: v_or_b32_e32 v28, v28, v293466; SI-NEXT: v_or_b32_e32 v24, v24, v253467; SI-NEXT: v_or_b32_e32 v20, v20, v213468; SI-NEXT: v_or_b32_e32 v16, v16, v173469; SI-NEXT: v_or_b32_e32 v12, v12, v133470; SI-NEXT: v_or_b32_e32 v8, v8, v93471; SI-NEXT: v_or_b32_e32 v4, v4, v53472; SI-NEXT: v_or_b32_e32 v0, v0, v13473; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v303474; SI-NEXT: v_lshlrev_b32_e32 v5, 2, v263475; SI-NEXT: v_lshlrev_b32_e32 v9, 2, v223476; SI-NEXT: v_lshlrev_b32_e32 v13, 2, v183477; SI-NEXT: v_lshlrev_b32_e32 v14, 2, v143478; SI-NEXT: v_lshlrev_b32_e32 v10, 2, v103479; SI-NEXT: v_lshlrev_b32_e32 v6, 2, v63480; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v23481; SI-NEXT: v_or_b32_e32 v1, v31, v13482; SI-NEXT: v_or_b32_e32 v5, v27, v53483; SI-NEXT: v_or_b32_e32 v9, v23, v93484; SI-NEXT: v_or_b32_e32 v13, v19, v133485; SI-NEXT: v_and_b32_e32 v17, 3, v283486; SI-NEXT: v_and_b32_e32 v18, 3, v243487; SI-NEXT: v_and_b32_e32 v19, 3, v203488; SI-NEXT: v_and_b32_e32 v16, 3, v163489; SI-NEXT: v_or_b32_e32 v14, v15, v143490; SI-NEXT: v_and_b32_e32 v12, 3, v123491; SI-NEXT: v_or_b32_e32 v10, v11, v103492; SI-NEXT: v_and_b32_e32 v8, 3, v83493; SI-NEXT: v_or_b32_e32 v6, v7, v63494; SI-NEXT: v_and_b32_e32 v4, 3, v43495; SI-NEXT: v_or_b32_e32 v2, v3, v23496; SI-NEXT: v_and_b32_e32 v0, 3, v03497; SI-NEXT: v_or_b32_e32 v1, v17, v13498; SI-NEXT: v_or_b32_e32 v3, v18, v53499; SI-NEXT: v_or_b32_e32 v5, v19, v93500; SI-NEXT: v_or_b32_e32 v7, v16, v133501; SI-NEXT: v_or_b32_e32 v9, v12, v143502; SI-NEXT: v_or_b32_e32 v8, v8, v103503; SI-NEXT: v_or_b32_e32 v4, v4, v63504; SI-NEXT: v_or_b32_e32 v0, v0, v23505; SI-NEXT: v_lshlrev_b32_e32 v1, 12, v13506; SI-NEXT: v_and_b32_e32 v2, 15, v33507; SI-NEXT: v_lshlrev_b32_e32 v3, 4, v53508; SI-NEXT: v_and_b32_e32 v5, 15, v73509; SI-NEXT: v_lshlrev_b32_e32 v6, 12, v93510; SI-NEXT: v_and_b32_e32 v7, 15, v83511; SI-NEXT: v_lshlrev_b32_e32 v4, 4, v43512; SI-NEXT: v_and_b32_e32 v0, 15, v03513; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v23514; SI-NEXT: v_or_b32_e32 v3, v5, v33515; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v73516; SI-NEXT: v_or_b32_e32 v0, v0, v43517; SI-NEXT: v_or_b32_e32 v1, v1, v23518; SI-NEXT: v_and_b32_e32 v2, 0xff, v33519; SI-NEXT: v_or_b32_e32 v3, v6, v53520; SI-NEXT: v_and_b32_e32 v0, 0xff, v03521; SI-NEXT: v_or_b32_e32 v1, v2, v13522; SI-NEXT: v_or_b32_e32 v0, v0, v33523; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v13524; SI-NEXT: v_and_b32_e32 v0, 0xffff, v03525; SI-NEXT: v_or_b32_e32 v0, v0, v13526; SI-NEXT: s_mov_b32 s2, -13527; SI-NEXT: buffer_store_dword v0, off, s[0:3], 03528; SI-NEXT: s_endpgm3529;3530; VI-LABEL: amdgpu_cs_v32i1:3531; VI: ; %bb.0:3532; VI-NEXT: v_and_b32_e32 v6, 1, v63533; VI-NEXT: v_lshlrev_b16_e32 v5, 1, v53534; VI-NEXT: v_and_b32_e32 v4, 1, v43535; VI-NEXT: v_and_b32_e32 v2, 1, v23536; VI-NEXT: v_lshlrev_b16_e32 v1, 1, v13537; VI-NEXT: v_and_b32_e32 v0, 1, v03538; VI-NEXT: v_lshlrev_b16_e32 v7, 3, v73539; VI-NEXT: v_lshlrev_b16_e32 v6, 2, v63540; VI-NEXT: v_or_b32_e32 v4, v4, v53541; VI-NEXT: v_lshlrev_b16_e32 v3, 3, v33542; VI-NEXT: v_lshlrev_b16_e32 v2, 2, v23543; VI-NEXT: v_or_b32_e32 v0, v0, v13544; VI-NEXT: v_or_b32_e32 v6, v7, v63545; VI-NEXT: v_and_b32_e32 v4, 3, v43546; VI-NEXT: v_or_b32_e32 v2, v3, v23547; VI-NEXT: v_and_b32_e32 v0, 3, v03548; VI-NEXT: v_or_b32_e32 v4, v4, v63549; VI-NEXT: v_or_b32_e32 v0, v0, v23550; VI-NEXT: v_lshlrev_b16_e32 v1, 4, v43551; VI-NEXT: v_and_b32_e32 v0, 15, v03552; VI-NEXT: v_and_b32_e32 v2, 1, v303553; VI-NEXT: v_or_b32_e32 v0, v0, v13554; VI-NEXT: v_lshlrev_b16_e32 v1, 3, v313555; VI-NEXT: v_lshlrev_b16_e32 v2, 2, v23556; VI-NEXT: v_or_b32_e32 v1, v1, v23557; VI-NEXT: v_lshlrev_b16_e32 v2, 1, v293558; VI-NEXT: v_and_b32_e32 v3, 1, v283559; VI-NEXT: v_or_b32_e32 v2, v3, v23560; VI-NEXT: v_and_b32_e32 v2, 3, v23561; VI-NEXT: v_and_b32_e32 v3, 1, v263562; VI-NEXT: v_or_b32_e32 v1, v2, v13563; VI-NEXT: v_lshlrev_b16_e32 v2, 3, v273564; VI-NEXT: v_lshlrev_b16_e32 v3, 2, v33565; VI-NEXT: v_and_b32_e32 v10, 1, v103566; VI-NEXT: v_lshlrev_b16_e32 v9, 1, v93567; VI-NEXT: v_and_b32_e32 v8, 1, v83568; VI-NEXT: v_or_b32_e32 v2, v2, v33569; VI-NEXT: v_lshlrev_b16_e32 v3, 1, v253570; VI-NEXT: v_and_b32_e32 v4, 1, v243571; VI-NEXT: v_lshlrev_b16_e32 v11, 3, v113572; VI-NEXT: v_lshlrev_b16_e32 v10, 2, v103573; VI-NEXT: v_or_b32_e32 v8, v8, v93574; VI-NEXT: v_or_b32_e32 v3, v4, v33575; VI-NEXT: v_or_b32_e32 v10, v11, v103576; VI-NEXT: v_and_b32_e32 v8, 3, v83577; VI-NEXT: v_and_b32_e32 v3, 3, v33578; VI-NEXT: v_or_b32_e32 v8, v8, v103579; VI-NEXT: v_mov_b32_e32 v10, 153580; VI-NEXT: v_or_b32_e32 v2, v3, v23581; VI-NEXT: v_lshlrev_b16_e32 v1, 12, v13582; VI-NEXT: v_and_b32_sdwa v2, v2, v10 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3583; VI-NEXT: v_and_b32_e32 v3, 1, v223584; VI-NEXT: v_or_b32_e32 v1, v1, v23585; VI-NEXT: v_lshlrev_b16_e32 v2, 3, v233586; VI-NEXT: v_lshlrev_b16_e32 v3, 2, v33587; VI-NEXT: v_or_b32_e32 v2, v2, v33588; VI-NEXT: v_lshlrev_b16_e32 v3, 1, v213589; VI-NEXT: v_and_b32_e32 v4, 1, v203590; VI-NEXT: v_or_b32_e32 v3, v4, v33591; VI-NEXT: v_and_b32_e32 v3, 3, v33592; VI-NEXT: v_and_b32_e32 v4, 1, v183593; VI-NEXT: v_or_b32_e32 v2, v3, v23594; VI-NEXT: v_lshlrev_b16_e32 v3, 3, v193595; VI-NEXT: v_lshlrev_b16_e32 v4, 2, v43596; VI-NEXT: v_and_b32_e32 v14, 1, v143597; VI-NEXT: v_lshlrev_b16_e32 v13, 1, v133598; VI-NEXT: v_and_b32_e32 v12, 1, v123599; VI-NEXT: v_or_b32_e32 v3, v3, v43600; VI-NEXT: v_lshlrev_b16_e32 v4, 1, v173601; VI-NEXT: v_and_b32_e32 v5, 1, v163602; VI-NEXT: v_lshlrev_b16_e32 v15, 3, v153603; VI-NEXT: v_lshlrev_b16_e32 v14, 2, v143604; VI-NEXT: v_or_b32_e32 v12, v12, v133605; VI-NEXT: v_or_b32_e32 v4, v5, v43606; VI-NEXT: v_or_b32_e32 v14, v15, v143607; VI-NEXT: v_and_b32_e32 v12, 3, v123608; VI-NEXT: v_and_b32_e32 v4, 3, v43609; VI-NEXT: v_or_b32_e32 v12, v12, v143610; VI-NEXT: v_or_b32_e32 v3, v4, v33611; VI-NEXT: v_lshlrev_b16_e32 v9, 12, v123612; VI-NEXT: v_and_b32_sdwa v8, v8, v10 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3613; VI-NEXT: v_lshlrev_b16_e32 v2, 4, v23614; VI-NEXT: v_and_b32_e32 v3, 15, v33615; VI-NEXT: v_or_b32_e32 v8, v9, v83616; VI-NEXT: v_or_b32_e32 v2, v3, v23617; VI-NEXT: v_or_b32_sdwa v0, v0, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD3618; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD3619; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD3620; VI-NEXT: flat_store_dword v[0:1], v03621; VI-NEXT: s_endpgm3622;3623; GFX11-TRUE16-LABEL: amdgpu_cs_v32i1:3624; GFX11-TRUE16: ; %bb.0:3625; GFX11-TRUE16-NEXT: v_and_b16 v26.l, v26.l, 13626; GFX11-TRUE16-NEXT: v_lshlrev_b16 v25.l, 1, v25.l3627; GFX11-TRUE16-NEXT: v_and_b16 v24.l, v24.l, 13628; GFX11-TRUE16-NEXT: v_and_b16 v20.h, v22.l, 13629; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 1, v21.l3630; GFX11-TRUE16-NEXT: v_and_b16 v20.l, v20.l, 13631; GFX11-TRUE16-NEXT: v_and_b16 v17.h, v18.l, 13632; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 1, v17.l3633; GFX11-TRUE16-NEXT: v_and_b16 v16.l, v16.l, 13634; GFX11-TRUE16-NEXT: v_and_b16 v10.l, v10.l, 13635; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 1, v9.l3636; GFX11-TRUE16-NEXT: v_and_b16 v8.l, v8.l, 13637; GFX11-TRUE16-NEXT: v_and_b16 v6.l, v6.l, 13638; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 1, v5.l3639; GFX11-TRUE16-NEXT: v_and_b16 v0.h, v4.l, 13640; GFX11-TRUE16-NEXT: v_and_b16 v1.h, v2.l, 13641; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 1, v1.l3642; GFX11-TRUE16-NEXT: v_and_b16 v0.l, v0.l, 13643; GFX11-TRUE16-NEXT: v_and_b16 v30.l, v30.l, 13644; GFX11-TRUE16-NEXT: v_lshlrev_b16 v29.l, 1, v29.l3645; GFX11-TRUE16-NEXT: v_and_b16 v28.l, v28.l, 13646; GFX11-TRUE16-NEXT: v_lshlrev_b16 v25.h, 3, v27.l3647; GFX11-TRUE16-NEXT: v_lshlrev_b16 v26.l, 2, v26.l3648; GFX11-TRUE16-NEXT: v_or_b16 v22.h, v24.l, v25.l3649; GFX11-TRUE16-NEXT: v_lshlrev_b16 v22.l, 3, v23.l3650; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.h, 2, v20.h3651; GFX11-TRUE16-NEXT: v_or_b16 v16.h, v20.l, v21.l3652; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 3, v19.l3653; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 2, v17.h3654; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v16.l, v17.l3655; GFX11-TRUE16-NEXT: v_and_b16 v14.l, v14.l, 13656; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.l, 1, v13.l3657; GFX11-TRUE16-NEXT: v_and_b16 v12.l, v12.l, 13658; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 3, v11.l3659; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 2, v10.l3660; GFX11-TRUE16-NEXT: v_or_b16 v5.h, v8.l, v9.l3661; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.l, 3, v7.l3662; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 2, v6.l3663; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v0.h, v4.h3664; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 3, v3.l3665; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 2, v1.h3666; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l3667; GFX11-TRUE16-NEXT: v_lshlrev_b16 v28.h, 3, v31.l3668; GFX11-TRUE16-NEXT: v_lshlrev_b16 v29.h, 2, v30.l3669; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v28.l, v29.l3670; GFX11-TRUE16-NEXT: v_or_b16 v25.h, v25.h, v26.l3671; GFX11-TRUE16-NEXT: v_and_b16 v21.h, v22.h, 33672; GFX11-TRUE16-NEXT: v_or_b16 v18.l, v22.l, v20.h3673; GFX11-TRUE16-NEXT: v_and_b16 v16.h, v16.h, 33674; GFX11-TRUE16-NEXT: v_or_b16 v17.h, v18.h, v17.h3675; GFX11-TRUE16-NEXT: v_and_b16 v16.l, v16.l, 33676; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.h, 3, v15.l3677; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.h, 2, v14.l3678; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v12.l, v13.l3679; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v9.h, v10.l3680; GFX11-TRUE16-NEXT: v_and_b16 v1.l, v5.h, 33681; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v7.l, v2.l3682; GFX11-TRUE16-NEXT: v_and_b16 v0.h, v0.h, 33683; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v2.h, v1.h3684; GFX11-TRUE16-NEXT: v_and_b16 v0.l, v0.l, 33685; GFX11-TRUE16-NEXT: v_or_b16 v26.h, v28.h, v29.h3686; GFX11-TRUE16-NEXT: v_and_b16 v24.h, v28.l, 33687; GFX11-TRUE16-NEXT: v_or_b16 v19.l, v21.h, v25.h3688; GFX11-TRUE16-NEXT: v_or_b16 v16.h, v16.h, v18.l3689; GFX11-TRUE16-NEXT: v_or_b16 v15.h, v16.l, v17.h3690; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v12.h, v10.h3691; GFX11-TRUE16-NEXT: v_and_b16 v3.l, v8.h, 33692; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.l, v6.h3693; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v0.h, v2.l3694; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.h3695; GFX11-TRUE16-NEXT: v_or_b16 v24.h, v24.h, v26.h3696; GFX11-TRUE16-NEXT: v_and_b16 v14.h, v19.l, 153697; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.h, 4, v16.h3698; GFX11-TRUE16-NEXT: v_and_b16 v1.h, v15.h, 153699; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v3.l, v2.h3700; GFX11-TRUE16-NEXT: v_and_b16 v1.l, v1.l, 153701; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 4, v0.h3702; GFX11-TRUE16-NEXT: v_and_b16 v0.l, v0.l, 153703; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 12, v24.h3704; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v14.h3705; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v1.h, v16.h3706; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 12, v2.l3707; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l3708; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h3709; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v17.l, v2.h3710; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h3711; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3712; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.l3713; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l3714; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)3715; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v0.h3716; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l3717; GFX11-TRUE16-NEXT: global_store_b32 v[0:1], v0, off3718; GFX11-TRUE16-NEXT: s_endpgm3719;3720; GFX11-FAKE16-LABEL: amdgpu_cs_v32i1:3721; GFX11-FAKE16: ; %bb.0:3722; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 1, v103723; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 1, v93724; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 1, v83725; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 3, v113726; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 1, v63727; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 2, v103728; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 1, v23729; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v93730; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 1, v13731; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v03732; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 1, v143733; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 1, v133734; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 1, v123735; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 1, v53736; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 1, v43737; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v103738; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 3, v83739; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 3, v73740; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 2, v63741; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 3, v33742; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 2, v23743; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v13744; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 3, v153745; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 2, v143746; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v133747; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v53748; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v63749; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v93750; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v23751; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 3, v03752; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v143753; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 3, v123754; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 15, v63755; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 1, v293756; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v23757; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 1, v263758; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 1, v283759; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 1, v253760; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 1, v243761; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 3, v43762; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v12, v133763; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 3, v273764; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 2, v23765; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v63766; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v93767; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 1, v223768; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 1, v213769; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 1, v203770; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 1, v183771; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 1, v173772; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 1, v163773; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v53774; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 1, v303775; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v8, v23776; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 3, v233777; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 2, v93778; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v103779; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 3, v193780; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 2, v133781; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v143782; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 3, v313783; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 2, v53784; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 3, v73785; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v93786; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 3, v103787; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v133788; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 3, v143789; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v11, v53790; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 3, v63791; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v7, v23792; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v83793; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v103794; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 4, v43795; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 15, v03796; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v53797; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 15, v23798; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 4, v73799; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 15, v83800; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 12, v13801; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v33802; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v43803; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 12, v53804; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v23805; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v63806; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v33807; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v03808; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3809; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v23810; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v53811; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)3812; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v13813; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v23814; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3815; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v03816; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v13817; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)3818; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v13819; GFX11-FAKE16-NEXT: global_store_b32 v[0:1], v0, off3820; GFX11-FAKE16-NEXT: s_endpgm3821;3822; GFX1250-TRUE16-LABEL: amdgpu_cs_v32i1:3823; GFX1250-TRUE16: ; %bb.0:3824; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 13825; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v18.h, 3, v19.l3826; GFX1250-TRUE16-NEXT: v_and_b16 v19.l, v22.l, 13827; GFX1250-TRUE16-NEXT: v_and_b16 v18.l, v18.l, 13828; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v17.h, 3, v23.l3829; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v19.h, 1, v21.l3830; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v17.l, 1, v17.l3831; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v19.l, 2, v19.l3832; GFX1250-TRUE16-NEXT: v_and_b16 v3.h, v6.l, 13833; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v18.l, 2, v18.l3834; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v1.h, 3, v7.l3835; GFX1250-TRUE16-NEXT: v_bitop3_b16 v16.l, v16.l, v17.l, 1 bitop3:0xec3836; GFX1250-TRUE16-NEXT: v_or_b16 v16.h, v17.h, v19.l3837; GFX1250-TRUE16-NEXT: v_bitop3_b16 v17.h, v20.l, v19.h, 1 bitop3:0xec3838; GFX1250-TRUE16-NEXT: v_and_b16 v17.l, v26.l, 13839; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v3.h, 2, v3.h3840; GFX1250-TRUE16-NEXT: v_or_b16 v18.l, v18.h, v18.l3841; GFX1250-TRUE16-NEXT: v_and_b16 v18.h, v24.l, 13842; GFX1250-TRUE16-NEXT: v_bitop3_b16 v16.h, v17.h, v16.h, 3 bitop3:0xec3843; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v17.h, 1, v25.l3844; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v19.l, 3, v27.l3845; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v17.l, 2, v17.l3846; GFX1250-TRUE16-NEXT: v_and_b16 v19.h, v30.l, 13847; GFX1250-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v3.h3848; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v1.h, 1, v5.l3849; GFX1250-TRUE16-NEXT: v_and_b16 v5.l, v10.l, 13850; GFX1250-TRUE16-NEXT: v_and_b16 v5.h, v14.l, 13851; GFX1250-TRUE16-NEXT: v_bitop3_b16 v17.h, v18.h, 3, v17.h bitop3:0xc83852; GFX1250-TRUE16-NEXT: v_or_b16 v17.l, v19.l, v17.l3853; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v18.h, 3, v31.l3854; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v19.l, 2, v19.h3855; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v19.h, 1, v29.l3856; GFX1250-TRUE16-NEXT: v_and_b16 v2.l, v2.l, 13857; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v3.h, 1, v9.l3858; GFX1250-TRUE16-NEXT: v_and_b16 v4.h, v8.l, 13859; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v6.l, 3, v11.l3860; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v5.l, 2, v5.l3861; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v6.h, 3, v15.l3862; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v5.h, 2, v5.h3863; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v7.l, 1, v13.l3864; GFX1250-TRUE16-NEXT: v_bitop3_b16 v17.l, v17.h, 15, v17.l bitop3:0xc83865; GFX1250-TRUE16-NEXT: v_bitop3_b16 v16.l, v16.l, v18.l, 3 bitop3:0xec3866; GFX1250-TRUE16-NEXT: v_or_b16 v17.h, v18.h, v19.l3867; GFX1250-TRUE16-NEXT: v_bitop3_b16 v18.l, v28.l, v19.h, 1 bitop3:0xec3868; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v3.l, 3, v3.l3869; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v2.l, 2, v2.l3870; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v1.l, 1, v1.l3871; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.h, v4.l, v1.h, 1 bitop3:0xec3872; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.h, v4.h, 3, v3.h bitop3:0xc83873; GFX1250-TRUE16-NEXT: v_or_b16 v4.l, v6.l, v5.l3874; GFX1250-TRUE16-NEXT: v_or_b16 v4.h, v6.h, v5.h3875; GFX1250-TRUE16-NEXT: v_bitop3_b16 v5.l, v12.l, v7.l, 1 bitop3:0xec3876; GFX1250-TRUE16-NEXT: v_bitop3_b16 v2.h, v18.l, v17.h, 3 bitop3:0xec3877; GFX1250-TRUE16-NEXT: v_or_b16 v2.l, v3.l, v2.l3878; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, 1 bitop3:0xec3879; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.h, v1.h, v0.h, 3 bitop3:0xec3880; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.l, v3.h, 15, v4.l bitop3:0xc83881; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.h, v5.l, v4.h, 3 bitop3:0xec3882; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v16.h, 4, v16.h3883; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v17.l3884; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v2.h, 12, v2.h3885; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v2.l, 3 bitop3:0xec3886; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v0.h, 4, v0.h3887; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l3888; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v1.h, 12, v1.h3889; GFX1250-TRUE16-NEXT: v_bitop3_b16 v2.l, v16.l, v16.h, 15 bitop3:0xec3890; GFX1250-TRUE16-NEXT: v_or_b16 v2.h, v2.h, v17.l3891; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v0.h, 15 bitop3:0xec3892; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)3893; GFX1250-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l3894; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.h, v2.l, v2.h, 0xff bitop3:0xec3895; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)3896; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.l, v0.l, v0.h, 0xff bitop3:0xec3897; GFX1250-TRUE16-NEXT: global_store_b32 v[0:1], v1, off3898; GFX1250-TRUE16-NEXT: s_endpgm3899;3900; GFX1250-FAKE16-LABEL: amdgpu_cs_v32i1:3901; GFX1250-FAKE16: ; %bb.0:3902; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 13903; GFX1250-FAKE16-NEXT: v_and_b32_e32 v2, 1, v23904; GFX1250-FAKE16-NEXT: v_and_b32_e32 v6, 1, v63905; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v3, 3, v33906; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v7, 3, v73907; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v5, 1, v53908; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v2, 2, v23909; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v6, 2, v63910; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v1, 1, v13911; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3912; GFX1250-FAKE16-NEXT: v_bitop3_b16 v4, v4, v5, 1 bitop3:0xec3913; GFX1250-FAKE16-NEXT: v_or_b32_e32 v2, v3, v23914; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)3915; GFX1250-FAKE16-NEXT: v_or_b32_e32 v3, v7, v63916; GFX1250-FAKE16-NEXT: v_and_b32_e32 v6, 1, v103917; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v5, 1, v93918; GFX1250-FAKE16-NEXT: v_and_b32_e32 v7, 1, v83919; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v8, 3, v113920; GFX1250-FAKE16-NEXT: v_bitop3_b16 v3, v4, v3, 3 bitop3:0xec3921; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v6, 2, v63922; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, 1 bitop3:0xec3923; GFX1250-FAKE16-NEXT: v_bitop3_b16 v4, v7, 3, v5 bitop3:0xc83924; GFX1250-FAKE16-NEXT: v_and_b32_e32 v1, 1, v143925; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v7, 3, v233926; GFX1250-FAKE16-NEXT: v_or_b32_e32 v5, v8, v63927; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v6, 3, v153928; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v2, 3 bitop3:0xec3929; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v1, 2, v13930; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v2, 1, v133931; GFX1250-FAKE16-NEXT: v_bitop3_b16 v4, v4, 15, v5 bitop3:0xc83932; GFX1250-FAKE16-NEXT: v_and_b32_e32 v5, 1, v223933; GFX1250-FAKE16-NEXT: v_and_b32_e32 v9, 1, v263934; GFX1250-FAKE16-NEXT: v_and_b32_e32 v11, 1, v303935; GFX1250-FAKE16-NEXT: v_or_b32_e32 v1, v6, v13936; GFX1250-FAKE16-NEXT: v_bitop3_b16 v2, v12, v2, 1 bitop3:0xec3937; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v5, 2, v53938; GFX1250-FAKE16-NEXT: v_and_b32_e32 v6, 1, v183939; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v10, 1, v253940; GFX1250-FAKE16-NEXT: v_and_b32_e32 v12, 1, v243941; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v13, 3, v273942; GFX1250-FAKE16-NEXT: v_or_b32_e32 v5, v7, v53943; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v7, 1, v213944; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v9, 2, v93945; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v14, 3, v313946; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v11, 2, v113947; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v15, 1, v293948; GFX1250-FAKE16-NEXT: v_bitop3_b16 v1, v2, v1, 3 bitop3:0xec3949; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v2, 3, v193950; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v6, 2, v63951; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v8, 1, v173952; GFX1250-FAKE16-NEXT: v_bitop3_b16 v7, v20, v7, 1 bitop3:0xec3953; GFX1250-FAKE16-NEXT: v_bitop3_b16 v10, v12, 3, v10 bitop3:0xc83954; GFX1250-FAKE16-NEXT: v_or_b32_e32 v9, v13, v93955; GFX1250-FAKE16-NEXT: v_or_b32_e32 v11, v14, v113956; GFX1250-FAKE16-NEXT: v_bitop3_b16 v12, v28, v15, 1 bitop3:0xec3957; GFX1250-FAKE16-NEXT: v_or_b32_e32 v2, v2, v63958; GFX1250-FAKE16-NEXT: v_bitop3_b16 v6, v16, v8, 1 bitop3:0xec3959; GFX1250-FAKE16-NEXT: v_bitop3_b16 v5, v7, v5, 3 bitop3:0xec3960; GFX1250-FAKE16-NEXT: v_bitop3_b16 v7, v10, 15, v9 bitop3:0xc83961; GFX1250-FAKE16-NEXT: v_bitop3_b16 v8, v12, v11, 3 bitop3:0xec3962; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v3, 4, v33963; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v43964; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v1, 12, v13965; GFX1250-FAKE16-NEXT: v_bitop3_b16 v2, v6, v2, 3 bitop3:0xec3966; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v5, 4, v53967; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v73968; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v7, 12, v83969; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v3, 15 bitop3:0xec3970; GFX1250-FAKE16-NEXT: v_or_b32_e32 v1, v1, v43971; GFX1250-FAKE16-NEXT: v_bitop3_b16 v2, v2, v5, 15 bitop3:0xec3972; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)3973; GFX1250-FAKE16-NEXT: v_or_b32_e32 v3, v7, v63974; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, 0xff bitop3:0xec3975; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3976; GFX1250-FAKE16-NEXT: v_bitop3_b16 v1, v2, v3, 0xff bitop3:0xec3977; GFX1250-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v03978; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)3979; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v13980; GFX1250-FAKE16-NEXT: v_or_b32_e32 v0, v0, v13981; GFX1250-FAKE16-NEXT: global_store_b32 v[0:1], v0, off3982; GFX1250-FAKE16-NEXT: s_endpgm3983 store <32 x i1> %arg0, ptr addrspace(1) poison3984 ret void3985}3986 3987define amdgpu_cs void @amdgpu_cs_inreg_i1(i1 inreg %arg0) {3988; SI-LABEL: amdgpu_cs_inreg_i1:3989; SI: ; %bb.0:3990; SI-NEXT: s_and_b32 s0, s0, 13991; SI-NEXT: s_mov_b32 s3, 0xf0003992; SI-NEXT: s_mov_b32 s2, -13993; SI-NEXT: v_mov_b32_e32 v0, s03994; SI-NEXT: buffer_store_byte v0, off, s[0:3], 03995; SI-NEXT: s_endpgm3996;3997; VI-LABEL: amdgpu_cs_inreg_i1:3998; VI: ; %bb.0:3999; VI-NEXT: s_and_b32 s0, s0, 14000; VI-NEXT: v_mov_b32_e32 v0, s04001; VI-NEXT: flat_store_byte v[0:1], v04002; VI-NEXT: s_endpgm4003;4004; GFX11-LABEL: amdgpu_cs_inreg_i1:4005; GFX11: ; %bb.0:4006; GFX11-NEXT: s_and_b32 s0, s0, 14007; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)4008; GFX11-NEXT: v_mov_b32_e32 v0, s04009; GFX11-NEXT: global_store_b8 v[0:1], v0, off4010; GFX11-NEXT: s_endpgm4011;4012; GFX1250-LABEL: amdgpu_cs_inreg_i1:4013; GFX1250: ; %bb.0:4014; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 14015; GFX1250-NEXT: s_and_b32 s0, s0, 14016; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)4017; GFX1250-NEXT: v_mov_b32_e32 v0, s04018; GFX1250-NEXT: global_store_b8 v[0:1], v0, off4019; GFX1250-NEXT: s_endpgm4020 store i1 %arg0, ptr addrspace(1) poison4021 ret void4022}4023 4024define amdgpu_cs void @amdgpu_cs_inreg_v8i1(<8 x i1> inreg %arg0) {4025; SI-LABEL: amdgpu_cs_inreg_v8i1:4026; SI: ; %bb.0:4027; SI-NEXT: s_lshl_b32 s7, s7, 34028; SI-NEXT: s_and_b32 s6, s6, 14029; SI-NEXT: s_lshl_b32 s5, s5, 14030; SI-NEXT: s_and_b32 s4, s4, 14031; SI-NEXT: s_lshl_b32 s8, s3, 34032; SI-NEXT: s_and_b32 s2, s2, 14033; SI-NEXT: s_lshl_b32 s1, s1, 14034; SI-NEXT: s_and_b32 s0, s0, 14035; SI-NEXT: s_mov_b32 s3, 0xf0004036; SI-NEXT: s_lshl_b32 s6, s6, 24037; SI-NEXT: s_or_b32 s4, s4, s54038; SI-NEXT: s_lshl_b32 s2, s2, 24039; SI-NEXT: s_or_b32 s0, s0, s14040; SI-NEXT: s_or_b32 s1, s7, s64041; SI-NEXT: s_and_b32 s4, s4, 34042; SI-NEXT: s_or_b32 s2, s8, s24043; SI-NEXT: s_and_b32 s0, s0, 34044; SI-NEXT: s_or_b32 s1, s4, s14045; SI-NEXT: s_or_b32 s0, s0, s24046; SI-NEXT: s_lshl_b32 s1, s1, 44047; SI-NEXT: s_and_b32 s0, s0, 154048; SI-NEXT: s_or_b32 s0, s0, s14049; SI-NEXT: s_mov_b32 s2, -14050; SI-NEXT: v_mov_b32_e32 v0, s04051; SI-NEXT: buffer_store_byte v0, off, s[0:3], 04052; SI-NEXT: s_endpgm4053;4054; VI-LABEL: amdgpu_cs_inreg_v8i1:4055; VI: ; %bb.0:4056; VI-NEXT: s_and_b32 s6, s6, 14057; VI-NEXT: s_lshl_b32 s5, s5, 14058; VI-NEXT: s_and_b32 s4, s4, 14059; VI-NEXT: s_and_b32 s2, s2, 14060; VI-NEXT: s_lshl_b32 s1, s1, 14061; VI-NEXT: s_and_b32 s0, s0, 14062; VI-NEXT: s_lshl_b32 s7, s7, 34063; VI-NEXT: s_lshl_b32 s6, s6, 24064; VI-NEXT: s_or_b32 s4, s4, s54065; VI-NEXT: s_lshl_b32 s3, s3, 34066; VI-NEXT: s_lshl_b32 s2, s2, 24067; VI-NEXT: s_or_b32 s0, s0, s14068; VI-NEXT: s_or_b32 s6, s7, s64069; VI-NEXT: s_and_b32 s4, s4, 34070; VI-NEXT: s_or_b32 s2, s3, s24071; VI-NEXT: s_and_b32 s0, s0, 34072; VI-NEXT: s_or_b32 s4, s4, s64073; VI-NEXT: s_or_b32 s0, s0, s24074; VI-NEXT: s_lshl_b32 s4, s4, 44075; VI-NEXT: s_and_b32 s0, s0, 154076; VI-NEXT: s_or_b32 s0, s0, s44077; VI-NEXT: v_mov_b32_e32 v0, s04078; VI-NEXT: flat_store_byte v[0:1], v04079; VI-NEXT: s_endpgm4080;4081; GFX11-LABEL: amdgpu_cs_inreg_v8i1:4082; GFX11: ; %bb.0:4083; GFX11-NEXT: s_and_b32 s6, s6, 14084; GFX11-NEXT: s_lshl_b32 s5, s5, 14085; GFX11-NEXT: s_and_b32 s4, s4, 14086; GFX11-NEXT: s_and_b32 s2, s2, 14087; GFX11-NEXT: s_lshl_b32 s1, s1, 14088; GFX11-NEXT: s_and_b32 s0, s0, 14089; GFX11-NEXT: s_lshl_b32 s7, s7, 34090; GFX11-NEXT: s_lshl_b32 s6, s6, 24091; GFX11-NEXT: s_or_b32 s4, s4, s54092; GFX11-NEXT: s_lshl_b32 s3, s3, 34093; GFX11-NEXT: s_lshl_b32 s2, s2, 24094; GFX11-NEXT: s_or_b32 s0, s0, s14095; GFX11-NEXT: s_or_b32 s5, s7, s64096; GFX11-NEXT: s_and_b32 s4, s4, 34097; GFX11-NEXT: s_or_b32 s1, s3, s24098; GFX11-NEXT: s_and_b32 s0, s0, 34099; GFX11-NEXT: s_or_b32 s2, s4, s54100; GFX11-NEXT: s_or_b32 s0, s0, s14101; GFX11-NEXT: s_lshl_b32 s1, s2, 44102; GFX11-NEXT: s_and_b32 s0, s0, 154103; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)4104; GFX11-NEXT: s_or_b32 s0, s0, s14105; GFX11-NEXT: v_mov_b32_e32 v0, s04106; GFX11-NEXT: global_store_b8 v[0:1], v0, off4107; GFX11-NEXT: s_endpgm4108;4109; GFX1250-LABEL: amdgpu_cs_inreg_v8i1:4110; GFX1250: ; %bb.0:4111; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 14112; GFX1250-NEXT: s_and_b32 s6, s6, 14113; GFX1250-NEXT: s_lshl_b32 s5, s5, 14114; GFX1250-NEXT: s_and_b32 s4, s4, 14115; GFX1250-NEXT: s_and_b32 s2, s2, 14116; GFX1250-NEXT: s_lshl_b32 s1, s1, 14117; GFX1250-NEXT: s_and_b32 s0, s0, 14118; GFX1250-NEXT: s_lshl_b32 s7, s7, 34119; GFX1250-NEXT: s_lshl_b32 s6, s6, 24120; GFX1250-NEXT: s_or_b32 s4, s4, s54121; GFX1250-NEXT: s_lshl_b32 s3, s3, 34122; GFX1250-NEXT: s_lshl_b32 s2, s2, 24123; GFX1250-NEXT: s_or_b32 s0, s0, s14124; GFX1250-NEXT: s_or_b32 s5, s7, s64125; GFX1250-NEXT: s_and_b32 s4, s4, 34126; GFX1250-NEXT: s_or_b32 s1, s3, s24127; GFX1250-NEXT: s_and_b32 s0, s0, 34128; GFX1250-NEXT: s_or_b32 s2, s4, s54129; GFX1250-NEXT: s_or_b32 s0, s0, s14130; GFX1250-NEXT: s_lshl_b32 s1, s2, 44131; GFX1250-NEXT: s_and_b32 s0, s0, 154132; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)4133; GFX1250-NEXT: s_or_b32 s0, s0, s14134; GFX1250-NEXT: v_mov_b32_e32 v0, s04135; GFX1250-NEXT: global_store_b8 v[0:1], v0, off4136; GFX1250-NEXT: s_endpgm4137 store <8 x i1> %arg0, ptr addrspace(1) poison4138 ret void4139}4140 4141define amdgpu_cs void @amdgpu_cs_inreg_v16i1(<16 x i1> inreg %arg0) {4142; SI-LABEL: amdgpu_cs_inreg_v16i1:4143; SI: ; %bb.0:4144; SI-NEXT: s_lshl_b32 s15, s15, 34145; SI-NEXT: s_and_b32 s14, s14, 14146; SI-NEXT: s_lshl_b32 s13, s13, 14147; SI-NEXT: s_and_b32 s12, s12, 14148; SI-NEXT: s_lshl_b32 s11, s11, 34149; SI-NEXT: s_and_b32 s10, s10, 14150; SI-NEXT: s_lshl_b32 s9, s9, 14151; SI-NEXT: s_and_b32 s8, s8, 14152; SI-NEXT: s_lshl_b32 s7, s7, 34153; SI-NEXT: s_and_b32 s6, s6, 14154; SI-NEXT: s_lshl_b32 s5, s5, 14155; SI-NEXT: s_and_b32 s4, s4, 14156; SI-NEXT: s_lshl_b32 s16, s3, 34157; SI-NEXT: s_and_b32 s2, s2, 14158; SI-NEXT: s_lshl_b32 s1, s1, 14159; SI-NEXT: s_and_b32 s0, s0, 14160; SI-NEXT: s_mov_b32 s3, 0xf0004161; SI-NEXT: s_lshl_b32 s14, s14, 24162; SI-NEXT: s_or_b32 s12, s12, s134163; SI-NEXT: s_lshl_b32 s10, s10, 24164; SI-NEXT: s_or_b32 s8, s8, s94165; SI-NEXT: s_lshl_b32 s6, s6, 24166; SI-NEXT: s_or_b32 s4, s4, s54167; SI-NEXT: s_lshl_b32 s2, s2, 24168; SI-NEXT: s_or_b32 s0, s0, s14169; SI-NEXT: s_or_b32 s1, s15, s144170; SI-NEXT: s_and_b32 s5, s12, 34171; SI-NEXT: s_or_b32 s9, s11, s104172; SI-NEXT: s_and_b32 s8, s8, 34173; SI-NEXT: s_or_b32 s6, s7, s64174; SI-NEXT: s_and_b32 s4, s4, 34175; SI-NEXT: s_or_b32 s2, s16, s24176; SI-NEXT: s_and_b32 s0, s0, 34177; SI-NEXT: s_or_b32 s1, s5, s14178; SI-NEXT: s_or_b32 s5, s8, s94179; SI-NEXT: s_or_b32 s4, s4, s64180; SI-NEXT: s_or_b32 s0, s0, s24181; SI-NEXT: s_lshl_b32 s1, s1, 124182; SI-NEXT: s_and_b32 s2, s5, 154183; SI-NEXT: s_lshl_b32 s4, s4, 44184; SI-NEXT: s_and_b32 s0, s0, 154185; SI-NEXT: s_lshl_b32 s2, s2, 84186; SI-NEXT: s_or_b32 s0, s0, s44187; SI-NEXT: s_or_b32 s1, s1, s24188; SI-NEXT: s_and_b32 s0, s0, 0xff4189; SI-NEXT: s_or_b32 s0, s0, s14190; SI-NEXT: s_mov_b32 s2, -14191; SI-NEXT: v_mov_b32_e32 v0, s04192; SI-NEXT: buffer_store_short v0, off, s[0:3], 04193; SI-NEXT: s_endpgm4194;4195; VI-LABEL: amdgpu_cs_inreg_v16i1:4196; VI: ; %bb.0:4197; VI-NEXT: s_and_b32 s10, s10, 14198; VI-NEXT: s_lshl_b32 s9, s9, 14199; VI-NEXT: s_and_b32 s8, s8, 14200; VI-NEXT: s_and_b32 s6, s6, 14201; VI-NEXT: s_lshl_b32 s5, s5, 14202; VI-NEXT: s_and_b32 s4, s4, 14203; VI-NEXT: s_and_b32 s2, s2, 14204; VI-NEXT: s_lshl_b32 s1, s1, 14205; VI-NEXT: s_and_b32 s0, s0, 14206; VI-NEXT: s_and_b32 s14, s14, 14207; VI-NEXT: s_lshl_b32 s13, s13, 14208; VI-NEXT: s_and_b32 s12, s12, 14209; VI-NEXT: s_lshl_b32 s11, s11, 34210; VI-NEXT: s_lshl_b32 s10, s10, 24211; VI-NEXT: s_or_b32 s8, s8, s94212; VI-NEXT: s_lshl_b32 s7, s7, 34213; VI-NEXT: s_lshl_b32 s6, s6, 24214; VI-NEXT: s_or_b32 s4, s4, s54215; VI-NEXT: s_lshl_b32 s3, s3, 34216; VI-NEXT: s_lshl_b32 s2, s2, 24217; VI-NEXT: s_or_b32 s0, s0, s14218; VI-NEXT: s_lshl_b32 s15, s15, 34219; VI-NEXT: s_lshl_b32 s14, s14, 24220; VI-NEXT: s_or_b32 s12, s12, s134221; VI-NEXT: s_or_b32 s10, s11, s104222; VI-NEXT: s_and_b32 s8, s8, 34223; VI-NEXT: s_or_b32 s6, s7, s64224; VI-NEXT: s_and_b32 s4, s4, 34225; VI-NEXT: s_or_b32 s2, s3, s24226; VI-NEXT: s_and_b32 s0, s0, 34227; VI-NEXT: s_or_b32 s14, s15, s144228; VI-NEXT: s_and_b32 s12, s12, 34229; VI-NEXT: s_or_b32 s8, s8, s104230; VI-NEXT: s_or_b32 s4, s4, s64231; VI-NEXT: s_or_b32 s0, s0, s24232; VI-NEXT: s_or_b32 s12, s12, s144233; VI-NEXT: s_and_b32 s8, s8, 154234; VI-NEXT: s_lshl_b32 s4, s4, 44235; VI-NEXT: s_and_b32 s0, s0, 154236; VI-NEXT: s_lshl_b32 s12, s12, 124237; VI-NEXT: s_lshl_b32 s8, s8, 84238; VI-NEXT: s_or_b32 s0, s0, s44239; VI-NEXT: s_or_b32 s8, s12, s84240; VI-NEXT: s_and_b32 s0, s0, 0xff4241; VI-NEXT: s_or_b32 s0, s0, s84242; VI-NEXT: v_mov_b32_e32 v0, s04243; VI-NEXT: flat_store_short v[0:1], v04244; VI-NEXT: s_endpgm4245;4246; GFX11-LABEL: amdgpu_cs_inreg_v16i1:4247; GFX11: ; %bb.0:4248; GFX11-NEXT: s_and_b32 s10, s10, 14249; GFX11-NEXT: s_lshl_b32 s9, s9, 14250; GFX11-NEXT: s_and_b32 s8, s8, 14251; GFX11-NEXT: s_and_b32 s6, s6, 14252; GFX11-NEXT: s_lshl_b32 s5, s5, 14253; GFX11-NEXT: s_and_b32 s4, s4, 14254; GFX11-NEXT: s_and_b32 s2, s2, 14255; GFX11-NEXT: s_lshl_b32 s1, s1, 14256; GFX11-NEXT: s_and_b32 s0, s0, 14257; GFX11-NEXT: s_and_b32 s14, s14, 14258; GFX11-NEXT: s_lshl_b32 s13, s13, 14259; GFX11-NEXT: s_and_b32 s12, s12, 14260; GFX11-NEXT: s_lshl_b32 s11, s11, 34261; GFX11-NEXT: s_lshl_b32 s10, s10, 24262; GFX11-NEXT: s_or_b32 s8, s8, s94263; GFX11-NEXT: s_lshl_b32 s7, s7, 34264; GFX11-NEXT: s_lshl_b32 s6, s6, 24265; GFX11-NEXT: s_or_b32 s4, s4, s54266; GFX11-NEXT: s_lshl_b32 s3, s3, 34267; GFX11-NEXT: s_lshl_b32 s2, s2, 24268; GFX11-NEXT: s_or_b32 s0, s0, s14269; GFX11-NEXT: s_lshl_b32 s15, s15, 34270; GFX11-NEXT: s_lshl_b32 s14, s14, 24271; GFX11-NEXT: s_or_b32 s12, s12, s134272; GFX11-NEXT: s_or_b32 s9, s11, s104273; GFX11-NEXT: s_and_b32 s8, s8, 34274; GFX11-NEXT: s_or_b32 s5, s7, s64275; GFX11-NEXT: s_and_b32 s4, s4, 34276; GFX11-NEXT: s_or_b32 s1, s3, s24277; GFX11-NEXT: s_and_b32 s0, s0, 34278; GFX11-NEXT: s_or_b32 s13, s15, s144279; GFX11-NEXT: s_and_b32 s12, s12, 34280; GFX11-NEXT: s_or_b32 s8, s8, s94281; GFX11-NEXT: s_or_b32 s2, s4, s54282; GFX11-NEXT: s_or_b32 s0, s0, s14283; GFX11-NEXT: s_or_b32 s10, s12, s134284; GFX11-NEXT: s_and_b32 s8, s8, 154285; GFX11-NEXT: s_lshl_b32 s1, s2, 44286; GFX11-NEXT: s_and_b32 s0, s0, 154287; GFX11-NEXT: s_lshl_b32 s9, s10, 124288; GFX11-NEXT: s_lshl_b32 s2, s8, 84289; GFX11-NEXT: s_or_b32 s0, s0, s14290; GFX11-NEXT: s_or_b32 s1, s9, s24291; GFX11-NEXT: s_and_b32 s0, s0, 0xff4292; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)4293; GFX11-NEXT: s_or_b32 s0, s0, s14294; GFX11-NEXT: v_mov_b32_e32 v0, s04295; GFX11-NEXT: global_store_b16 v[0:1], v0, off4296; GFX11-NEXT: s_endpgm4297;4298; GFX1250-LABEL: amdgpu_cs_inreg_v16i1:4299; GFX1250: ; %bb.0:4300; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 14301; GFX1250-NEXT: s_and_b32 s10, s10, 14302; GFX1250-NEXT: s_lshl_b32 s9, s9, 14303; GFX1250-NEXT: s_and_b32 s8, s8, 14304; GFX1250-NEXT: s_and_b32 s6, s6, 14305; GFX1250-NEXT: s_lshl_b32 s5, s5, 14306; GFX1250-NEXT: s_and_b32 s4, s4, 14307; GFX1250-NEXT: s_and_b32 s2, s2, 14308; GFX1250-NEXT: s_lshl_b32 s1, s1, 14309; GFX1250-NEXT: s_and_b32 s0, s0, 14310; GFX1250-NEXT: s_and_b32 s14, s14, 14311; GFX1250-NEXT: s_lshl_b32 s13, s13, 14312; GFX1250-NEXT: s_and_b32 s12, s12, 14313; GFX1250-NEXT: s_lshl_b32 s11, s11, 34314; GFX1250-NEXT: s_lshl_b32 s10, s10, 24315; GFX1250-NEXT: s_or_b32 s8, s8, s94316; GFX1250-NEXT: s_lshl_b32 s7, s7, 34317; GFX1250-NEXT: s_lshl_b32 s6, s6, 24318; GFX1250-NEXT: s_or_b32 s4, s4, s54319; GFX1250-NEXT: s_lshl_b32 s3, s3, 34320; GFX1250-NEXT: s_lshl_b32 s2, s2, 24321; GFX1250-NEXT: s_or_b32 s0, s0, s14322; GFX1250-NEXT: s_lshl_b32 s15, s15, 34323; GFX1250-NEXT: s_lshl_b32 s14, s14, 24324; GFX1250-NEXT: s_or_b32 s12, s12, s134325; GFX1250-NEXT: s_or_b32 s9, s11, s104326; GFX1250-NEXT: s_and_b32 s8, s8, 34327; GFX1250-NEXT: s_or_b32 s5, s7, s64328; GFX1250-NEXT: s_and_b32 s4, s4, 34329; GFX1250-NEXT: s_or_b32 s1, s3, s24330; GFX1250-NEXT: s_and_b32 s0, s0, 34331; GFX1250-NEXT: s_or_b32 s13, s15, s144332; GFX1250-NEXT: s_and_b32 s12, s12, 34333; GFX1250-NEXT: s_or_b32 s8, s8, s94334; GFX1250-NEXT: s_or_b32 s2, s4, s54335; GFX1250-NEXT: s_or_b32 s0, s0, s14336; GFX1250-NEXT: s_or_b32 s10, s12, s134337; GFX1250-NEXT: s_and_b32 s8, s8, 154338; GFX1250-NEXT: s_lshl_b32 s1, s2, 44339; GFX1250-NEXT: s_and_b32 s0, s0, 154340; GFX1250-NEXT: s_lshl_b32 s9, s10, 124341; GFX1250-NEXT: s_lshl_b32 s2, s8, 84342; GFX1250-NEXT: s_or_b32 s0, s0, s14343; GFX1250-NEXT: s_or_b32 s1, s9, s24344; GFX1250-NEXT: s_and_b32 s0, s0, 0xff4345; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)4346; GFX1250-NEXT: s_or_b32 s0, s0, s14347; GFX1250-NEXT: v_mov_b32_e32 v0, s04348; GFX1250-NEXT: global_store_b16 v[0:1], v0, off4349; GFX1250-NEXT: s_endpgm4350 store <16 x i1> %arg0, ptr addrspace(1) poison4351 ret void4352}4353 4354define amdgpu_cs void @amdgpu_cs_inreg_v32i1(<32 x i1> inreg %arg0) {4355; SI-LABEL: amdgpu_cs_inreg_v32i1:4356; SI: ; %bb.0:4357; SI-NEXT: s_lshl_b32 s31, s31, 34358; SI-NEXT: s_and_b32 s30, s30, 14359; SI-NEXT: s_lshl_b32 s29, s29, 14360; SI-NEXT: s_and_b32 s28, s28, 14361; SI-NEXT: s_lshl_b32 s27, s27, 34362; SI-NEXT: s_and_b32 s26, s26, 14363; SI-NEXT: s_lshl_b32 s25, s25, 14364; SI-NEXT: s_and_b32 s24, s24, 14365; SI-NEXT: s_lshl_b32 s23, s23, 34366; SI-NEXT: s_and_b32 s22, s22, 14367; SI-NEXT: s_lshl_b32 s21, s21, 14368; SI-NEXT: s_and_b32 s20, s20, 14369; SI-NEXT: s_lshl_b32 s19, s19, 34370; SI-NEXT: s_and_b32 s18, s18, 14371; SI-NEXT: s_lshl_b32 s17, s17, 14372; SI-NEXT: s_and_b32 s16, s16, 14373; SI-NEXT: s_lshl_b32 s15, s15, 34374; SI-NEXT: s_and_b32 s14, s14, 14375; SI-NEXT: s_lshl_b32 s13, s13, 14376; SI-NEXT: s_and_b32 s12, s12, 14377; SI-NEXT: s_lshl_b32 s11, s11, 34378; SI-NEXT: s_and_b32 s10, s10, 14379; SI-NEXT: s_lshl_b32 s9, s9, 14380; SI-NEXT: s_and_b32 s8, s8, 14381; SI-NEXT: s_lshl_b32 s7, s7, 34382; SI-NEXT: s_and_b32 s6, s6, 14383; SI-NEXT: s_lshl_b32 s5, s5, 14384; SI-NEXT: s_and_b32 s4, s4, 14385; SI-NEXT: s_lshl_b32 s33, s3, 34386; SI-NEXT: s_and_b32 s2, s2, 14387; SI-NEXT: s_lshl_b32 s1, s1, 14388; SI-NEXT: s_and_b32 s0, s0, 14389; SI-NEXT: s_mov_b32 s3, 0xf0004390; SI-NEXT: s_lshl_b32 s30, s30, 24391; SI-NEXT: s_or_b32 s28, s28, s294392; SI-NEXT: s_lshl_b32 s26, s26, 24393; SI-NEXT: s_or_b32 s24, s24, s254394; SI-NEXT: s_lshl_b32 s22, s22, 24395; SI-NEXT: s_or_b32 s20, s20, s214396; SI-NEXT: s_lshl_b32 s18, s18, 24397; SI-NEXT: s_or_b32 s16, s16, s174398; SI-NEXT: s_lshl_b32 s14, s14, 24399; SI-NEXT: s_or_b32 s12, s12, s134400; SI-NEXT: s_lshl_b32 s10, s10, 24401; SI-NEXT: s_or_b32 s8, s8, s94402; SI-NEXT: s_lshl_b32 s6, s6, 24403; SI-NEXT: s_or_b32 s4, s4, s54404; SI-NEXT: s_lshl_b32 s2, s2, 24405; SI-NEXT: s_or_b32 s0, s0, s14406; SI-NEXT: s_or_b32 s1, s31, s304407; SI-NEXT: s_and_b32 s5, s28, 34408; SI-NEXT: s_or_b32 s9, s27, s264409; SI-NEXT: s_and_b32 s13, s24, 34410; SI-NEXT: s_or_b32 s17, s23, s224411; SI-NEXT: s_and_b32 s20, s20, 34412; SI-NEXT: s_or_b32 s18, s19, s184413; SI-NEXT: s_and_b32 s16, s16, 34414; SI-NEXT: s_or_b32 s14, s15, s144415; SI-NEXT: s_and_b32 s12, s12, 34416; SI-NEXT: s_or_b32 s10, s11, s104417; SI-NEXT: s_and_b32 s8, s8, 34418; SI-NEXT: s_or_b32 s6, s7, s64419; SI-NEXT: s_and_b32 s4, s4, 34420; SI-NEXT: s_or_b32 s2, s33, s24421; SI-NEXT: s_and_b32 s0, s0, 34422; SI-NEXT: s_or_b32 s1, s5, s14423; SI-NEXT: s_or_b32 s5, s13, s94424; SI-NEXT: s_or_b32 s7, s20, s174425; SI-NEXT: s_or_b32 s9, s16, s184426; SI-NEXT: s_or_b32 s11, s12, s144427; SI-NEXT: s_or_b32 s8, s8, s104428; SI-NEXT: s_or_b32 s4, s4, s64429; SI-NEXT: s_or_b32 s0, s0, s24430; SI-NEXT: s_lshl_b32 s1, s1, 124431; SI-NEXT: s_and_b32 s2, s5, 154432; SI-NEXT: s_lshl_b32 s5, s7, 44433; SI-NEXT: s_and_b32 s6, s9, 154434; SI-NEXT: s_lshl_b32 s7, s11, 124435; SI-NEXT: s_and_b32 s8, s8, 154436; SI-NEXT: s_lshl_b32 s4, s4, 44437; SI-NEXT: s_and_b32 s0, s0, 154438; SI-NEXT: s_lshl_b32 s2, s2, 84439; SI-NEXT: s_or_b32 s5, s6, s54440; SI-NEXT: s_lshl_b32 s6, s8, 84441; SI-NEXT: s_or_b32 s0, s0, s44442; SI-NEXT: s_or_b32 s1, s1, s24443; SI-NEXT: s_and_b32 s2, s5, 0xff4444; SI-NEXT: s_or_b32 s4, s7, s64445; SI-NEXT: s_and_b32 s0, s0, 0xff4446; SI-NEXT: s_or_b32 s1, s2, s14447; SI-NEXT: s_or_b32 s0, s0, s44448; SI-NEXT: s_lshl_b32 s1, s1, 164449; SI-NEXT: s_and_b32 s0, s0, 0xffff4450; SI-NEXT: s_or_b32 s0, s0, s14451; SI-NEXT: s_mov_b32 s2, -14452; SI-NEXT: v_mov_b32_e32 v0, s04453; SI-NEXT: buffer_store_dword v0, off, s[0:3], 04454; SI-NEXT: s_endpgm4455;4456; VI-LABEL: amdgpu_cs_inreg_v32i1:4457; VI: ; %bb.0:4458; VI-NEXT: s_and_b32 s26, s26, 14459; VI-NEXT: s_lshl_b32 s25, s25, 14460; VI-NEXT: s_and_b32 s24, s24, 14461; VI-NEXT: s_and_b32 s22, s22, 14462; VI-NEXT: s_lshl_b32 s21, s21, 14463; VI-NEXT: s_and_b32 s20, s20, 14464; VI-NEXT: s_and_b32 s18, s18, 14465; VI-NEXT: s_lshl_b32 s17, s17, 14466; VI-NEXT: s_and_b32 s16, s16, 14467; VI-NEXT: s_and_b32 s10, s10, 14468; VI-NEXT: s_lshl_b32 s9, s9, 14469; VI-NEXT: s_and_b32 s8, s8, 14470; VI-NEXT: s_and_b32 s6, s6, 14471; VI-NEXT: s_lshl_b32 s5, s5, 14472; VI-NEXT: s_and_b32 s4, s4, 14473; VI-NEXT: s_and_b32 s2, s2, 14474; VI-NEXT: s_lshl_b32 s1, s1, 14475; VI-NEXT: s_and_b32 s0, s0, 14476; VI-NEXT: s_and_b32 s30, s30, 14477; VI-NEXT: s_lshl_b32 s29, s29, 14478; VI-NEXT: s_and_b32 s28, s28, 14479; VI-NEXT: s_lshl_b32 s27, s27, 34480; VI-NEXT: s_lshl_b32 s26, s26, 24481; VI-NEXT: s_or_b32 s24, s24, s254482; VI-NEXT: s_lshl_b32 s23, s23, 34483; VI-NEXT: s_lshl_b32 s22, s22, 24484; VI-NEXT: s_or_b32 s20, s20, s214485; VI-NEXT: s_lshl_b32 s19, s19, 34486; VI-NEXT: s_lshl_b32 s18, s18, 24487; VI-NEXT: s_or_b32 s16, s16, s174488; VI-NEXT: s_and_b32 s14, s14, 14489; VI-NEXT: s_lshl_b32 s13, s13, 14490; VI-NEXT: s_and_b32 s12, s12, 14491; VI-NEXT: s_lshl_b32 s11, s11, 34492; VI-NEXT: s_lshl_b32 s10, s10, 24493; VI-NEXT: s_or_b32 s8, s8, s94494; VI-NEXT: s_lshl_b32 s7, s7, 34495; VI-NEXT: s_lshl_b32 s6, s6, 24496; VI-NEXT: s_or_b32 s4, s4, s54497; VI-NEXT: s_lshl_b32 s3, s3, 34498; VI-NEXT: s_lshl_b32 s2, s2, 24499; VI-NEXT: s_or_b32 s0, s0, s14500; VI-NEXT: s_lshl_b32 s31, s31, 34501; VI-NEXT: s_lshl_b32 s30, s30, 24502; VI-NEXT: s_or_b32 s28, s28, s294503; VI-NEXT: s_or_b32 s26, s27, s264504; VI-NEXT: s_and_b32 s24, s24, 34505; VI-NEXT: s_or_b32 s22, s23, s224506; VI-NEXT: s_and_b32 s20, s20, 34507; VI-NEXT: s_or_b32 s18, s19, s184508; VI-NEXT: s_and_b32 s16, s16, 34509; VI-NEXT: s_lshl_b32 s15, s15, 34510; VI-NEXT: s_lshl_b32 s14, s14, 24511; VI-NEXT: s_or_b32 s12, s12, s134512; VI-NEXT: s_or_b32 s10, s11, s104513; VI-NEXT: s_and_b32 s8, s8, 34514; VI-NEXT: s_or_b32 s6, s7, s64515; VI-NEXT: s_and_b32 s4, s4, 34516; VI-NEXT: s_or_b32 s2, s3, s24517; VI-NEXT: s_and_b32 s0, s0, 34518; VI-NEXT: s_or_b32 s30, s31, s304519; VI-NEXT: s_and_b32 s28, s28, 34520; VI-NEXT: s_or_b32 s24, s24, s264521; VI-NEXT: s_or_b32 s20, s20, s224522; VI-NEXT: s_or_b32 s16, s16, s184523; VI-NEXT: s_or_b32 s14, s15, s144524; VI-NEXT: s_and_b32 s12, s12, 34525; VI-NEXT: s_or_b32 s8, s8, s104526; VI-NEXT: s_or_b32 s4, s4, s64527; VI-NEXT: s_or_b32 s0, s0, s24528; VI-NEXT: s_or_b32 s28, s28, s304529; VI-NEXT: s_and_b32 s24, s24, 154530; VI-NEXT: s_lshl_b32 s20, s20, 44531; VI-NEXT: s_and_b32 s16, s16, 154532; VI-NEXT: s_or_b32 s12, s12, s144533; VI-NEXT: s_and_b32 s8, s8, 154534; VI-NEXT: s_lshl_b32 s4, s4, 44535; VI-NEXT: s_and_b32 s0, s0, 154536; VI-NEXT: s_lshl_b32 s28, s28, 124537; VI-NEXT: s_lshl_b32 s24, s24, 84538; VI-NEXT: s_or_b32 s16, s16, s204539; VI-NEXT: s_lshl_b32 s12, s12, 124540; VI-NEXT: s_lshl_b32 s8, s8, 84541; VI-NEXT: s_or_b32 s0, s0, s44542; VI-NEXT: s_or_b32 s24, s28, s244543; VI-NEXT: s_and_b32 s16, s16, 0xff4544; VI-NEXT: s_or_b32 s8, s12, s84545; VI-NEXT: s_and_b32 s0, s0, 0xff4546; VI-NEXT: s_or_b32 s16, s16, s244547; VI-NEXT: s_or_b32 s0, s0, s84548; VI-NEXT: s_lshl_b32 s16, s16, 164549; VI-NEXT: s_and_b32 s0, s0, 0xffff4550; VI-NEXT: s_or_b32 s0, s0, s164551; VI-NEXT: v_mov_b32_e32 v0, s04552; VI-NEXT: flat_store_dword v[0:1], v04553; VI-NEXT: s_endpgm4554;4555; GFX11-LABEL: amdgpu_cs_inreg_v32i1:4556; GFX11: ; %bb.0:4557; GFX11-NEXT: s_and_b32 s10, s10, 14558; GFX11-NEXT: s_lshl_b32 s9, s9, 14559; GFX11-NEXT: s_and_b32 s8, s8, 14560; GFX11-NEXT: s_and_b32 s14, s14, 14561; GFX11-NEXT: s_lshl_b32 s13, s13, 14562; GFX11-NEXT: s_and_b32 s12, s12, 14563; GFX11-NEXT: s_lshl_b32 s11, s11, 34564; GFX11-NEXT: s_lshl_b32 s10, s10, 24565; GFX11-NEXT: s_or_b32 s8, s8, s94566; GFX11-NEXT: s_and_b32 s6, s6, 14567; GFX11-NEXT: s_lshl_b32 s5, s5, 14568; GFX11-NEXT: s_and_b32 s4, s4, 14569; GFX11-NEXT: s_and_b32 s2, s2, 14570; GFX11-NEXT: s_lshl_b32 s1, s1, 14571; GFX11-NEXT: s_and_b32 s0, s0, 14572; GFX11-NEXT: s_lshl_b32 s15, s15, 34573; GFX11-NEXT: s_lshl_b32 s14, s14, 24574; GFX11-NEXT: s_or_b32 s12, s12, s134575; GFX11-NEXT: s_or_b32 s9, s11, s104576; GFX11-NEXT: s_and_b32 s8, s8, 34577; GFX11-NEXT: s_lshl_b32 s7, s7, 34578; GFX11-NEXT: s_lshl_b32 s6, s6, 24579; GFX11-NEXT: s_or_b32 s4, s4, s54580; GFX11-NEXT: s_lshl_b32 s3, s3, 34581; GFX11-NEXT: s_lshl_b32 s2, s2, 24582; GFX11-NEXT: s_or_b32 s0, s0, s14583; GFX11-NEXT: s_or_b32 s13, s15, s144584; GFX11-NEXT: s_and_b32 s12, s12, 34585; GFX11-NEXT: s_or_b32 s8, s8, s94586; GFX11-NEXT: s_or_b32 s5, s7, s64587; GFX11-NEXT: s_and_b32 s4, s4, 34588; GFX11-NEXT: s_or_b32 s1, s3, s24589; GFX11-NEXT: s_and_b32 s0, s0, 34590; GFX11-NEXT: s_or_b32 s10, s12, s134591; GFX11-NEXT: s_and_b32 s8, s8, 154592; GFX11-NEXT: s_or_b32 s2, s4, s54593; GFX11-NEXT: s_or_b32 s0, s0, s14594; GFX11-NEXT: s_lshl_b32 s9, s10, 124595; GFX11-NEXT: s_lshl_b32 s1, s2, 44596; GFX11-NEXT: s_and_b32 s0, s0, 154597; GFX11-NEXT: s_lshl_b32 s2, s8, 84598; GFX11-NEXT: s_and_b32 s3, s30, 14599; GFX11-NEXT: s_lshl_b32 s4, s29, 14600; GFX11-NEXT: s_and_b32 s5, s28, 14601; GFX11-NEXT: s_or_b32 s0, s0, s14602; GFX11-NEXT: s_or_b32 s1, s9, s24603; GFX11-NEXT: s_lshl_b32 s2, s31, 34604; GFX11-NEXT: s_lshl_b32 s3, s3, 24605; GFX11-NEXT: s_or_b32 s4, s5, s44606; GFX11-NEXT: s_and_b32 s5, s26, 14607; GFX11-NEXT: s_lshl_b32 s6, s25, 14608; GFX11-NEXT: s_and_b32 s7, s24, 14609; GFX11-NEXT: s_or_b32 s2, s2, s34610; GFX11-NEXT: s_and_b32 s3, s4, 34611; GFX11-NEXT: s_lshl_b32 s4, s27, 34612; GFX11-NEXT: s_lshl_b32 s5, s5, 24613; GFX11-NEXT: s_or_b32 s6, s7, s64614; GFX11-NEXT: s_or_b32 s4, s4, s54615; GFX11-NEXT: s_and_b32 s5, s6, 34616; GFX11-NEXT: s_or_b32 s2, s3, s24617; GFX11-NEXT: s_or_b32 s3, s5, s44618; GFX11-NEXT: s_and_b32 s5, s22, 14619; GFX11-NEXT: s_lshl_b32 s6, s21, 14620; GFX11-NEXT: s_and_b32 s7, s20, 14621; GFX11-NEXT: s_lshl_b32 s4, s23, 34622; GFX11-NEXT: s_lshl_b32 s5, s5, 24623; GFX11-NEXT: s_or_b32 s6, s7, s64624; GFX11-NEXT: s_and_b32 s7, s18, 14625; GFX11-NEXT: s_lshl_b32 s8, s17, 14626; GFX11-NEXT: s_and_b32 s9, s16, 14627; GFX11-NEXT: s_or_b32 s4, s4, s54628; GFX11-NEXT: s_and_b32 s5, s6, 34629; GFX11-NEXT: s_lshl_b32 s6, s19, 34630; GFX11-NEXT: s_lshl_b32 s7, s7, 24631; GFX11-NEXT: s_or_b32 s8, s9, s84632; GFX11-NEXT: s_or_b32 s6, s6, s74633; GFX11-NEXT: s_and_b32 s7, s8, 34634; GFX11-NEXT: s_or_b32 s4, s5, s44635; GFX11-NEXT: s_or_b32 s5, s7, s64636; GFX11-NEXT: s_and_b32 s3, s3, 154637; GFX11-NEXT: s_lshl_b32 s4, s4, 44638; GFX11-NEXT: s_and_b32 s5, s5, 154639; GFX11-NEXT: s_lshl_b32 s2, s2, 124640; GFX11-NEXT: s_lshl_b32 s3, s3, 84641; GFX11-NEXT: s_or_b32 s4, s5, s44642; GFX11-NEXT: s_and_b32 s0, s0, 0xff4643; GFX11-NEXT: s_or_b32 s2, s2, s34644; GFX11-NEXT: s_and_b32 s3, s4, 0xff4645; GFX11-NEXT: s_or_b32 s0, s0, s14646; GFX11-NEXT: s_or_b32 s1, s3, s24647; GFX11-NEXT: s_and_b32 s0, s0, 0xffff4648; GFX11-NEXT: s_lshl_b32 s1, s1, 164649; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)4650; GFX11-NEXT: s_or_b32 s0, s0, s14651; GFX11-NEXT: v_mov_b32_e32 v0, s04652; GFX11-NEXT: global_store_b32 v[0:1], v0, off4653; GFX11-NEXT: s_endpgm4654;4655; GFX1250-LABEL: amdgpu_cs_inreg_v32i1:4656; GFX1250: ; %bb.0:4657; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 14658; GFX1250-NEXT: s_and_b32 s10, s10, 14659; GFX1250-NEXT: s_lshl_b32 s9, s9, 14660; GFX1250-NEXT: s_and_b32 s8, s8, 14661; GFX1250-NEXT: s_and_b32 s14, s14, 14662; GFX1250-NEXT: s_lshl_b32 s13, s13, 14663; GFX1250-NEXT: s_and_b32 s12, s12, 14664; GFX1250-NEXT: s_lshl_b32 s11, s11, 34665; GFX1250-NEXT: s_lshl_b32 s10, s10, 24666; GFX1250-NEXT: s_or_b32 s8, s8, s94667; GFX1250-NEXT: s_and_b32 s6, s6, 14668; GFX1250-NEXT: s_lshl_b32 s5, s5, 14669; GFX1250-NEXT: s_and_b32 s4, s4, 14670; GFX1250-NEXT: s_and_b32 s2, s2, 14671; GFX1250-NEXT: s_lshl_b32 s1, s1, 14672; GFX1250-NEXT: s_and_b32 s0, s0, 14673; GFX1250-NEXT: s_lshl_b32 s15, s15, 34674; GFX1250-NEXT: s_lshl_b32 s14, s14, 24675; GFX1250-NEXT: s_or_b32 s12, s12, s134676; GFX1250-NEXT: s_or_b32 s9, s11, s104677; GFX1250-NEXT: s_and_b32 s8, s8, 34678; GFX1250-NEXT: s_lshl_b32 s7, s7, 34679; GFX1250-NEXT: s_lshl_b32 s6, s6, 24680; GFX1250-NEXT: s_or_b32 s4, s4, s54681; GFX1250-NEXT: s_lshl_b32 s3, s3, 34682; GFX1250-NEXT: s_lshl_b32 s2, s2, 24683; GFX1250-NEXT: s_or_b32 s0, s0, s14684; GFX1250-NEXT: s_or_b32 s13, s15, s144685; GFX1250-NEXT: s_and_b32 s12, s12, 34686; GFX1250-NEXT: s_or_b32 s8, s8, s94687; GFX1250-NEXT: s_or_b32 s5, s7, s64688; GFX1250-NEXT: s_and_b32 s4, s4, 34689; GFX1250-NEXT: s_or_b32 s1, s3, s24690; GFX1250-NEXT: s_and_b32 s0, s0, 34691; GFX1250-NEXT: s_or_b32 s10, s12, s134692; GFX1250-NEXT: s_and_b32 s8, s8, 154693; GFX1250-NEXT: s_or_b32 s2, s4, s54694; GFX1250-NEXT: s_or_b32 s0, s0, s14695; GFX1250-NEXT: s_lshl_b32 s9, s10, 124696; GFX1250-NEXT: s_lshl_b32 s1, s2, 44697; GFX1250-NEXT: s_and_b32 s0, s0, 154698; GFX1250-NEXT: s_lshl_b32 s2, s8, 84699; GFX1250-NEXT: s_and_b32 s3, s30, 14700; GFX1250-NEXT: s_lshl_b32 s4, s29, 14701; GFX1250-NEXT: s_and_b32 s5, s28, 14702; GFX1250-NEXT: s_or_b32 s0, s0, s14703; GFX1250-NEXT: s_or_b32 s1, s9, s24704; GFX1250-NEXT: s_lshl_b32 s2, s31, 34705; GFX1250-NEXT: s_lshl_b32 s3, s3, 24706; GFX1250-NEXT: s_or_b32 s4, s5, s44707; GFX1250-NEXT: s_and_b32 s5, s26, 14708; GFX1250-NEXT: s_lshl_b32 s6, s25, 14709; GFX1250-NEXT: s_and_b32 s7, s24, 14710; GFX1250-NEXT: s_or_b32 s2, s2, s34711; GFX1250-NEXT: s_and_b32 s3, s4, 34712; GFX1250-NEXT: s_lshl_b32 s4, s27, 34713; GFX1250-NEXT: s_lshl_b32 s5, s5, 24714; GFX1250-NEXT: s_or_b32 s6, s7, s64715; GFX1250-NEXT: s_or_b32 s4, s4, s54716; GFX1250-NEXT: s_and_b32 s5, s6, 34717; GFX1250-NEXT: s_or_b32 s2, s3, s24718; GFX1250-NEXT: s_or_b32 s3, s5, s44719; GFX1250-NEXT: s_and_b32 s5, s22, 14720; GFX1250-NEXT: s_lshl_b32 s6, s21, 14721; GFX1250-NEXT: s_and_b32 s7, s20, 14722; GFX1250-NEXT: s_lshl_b32 s4, s23, 34723; GFX1250-NEXT: s_lshl_b32 s5, s5, 24724; GFX1250-NEXT: s_or_b32 s6, s7, s64725; GFX1250-NEXT: s_and_b32 s7, s18, 14726; GFX1250-NEXT: s_lshl_b32 s8, s17, 14727; GFX1250-NEXT: s_and_b32 s9, s16, 14728; GFX1250-NEXT: s_or_b32 s4, s4, s54729; GFX1250-NEXT: s_and_b32 s5, s6, 34730; GFX1250-NEXT: s_lshl_b32 s6, s19, 34731; GFX1250-NEXT: s_lshl_b32 s7, s7, 24732; GFX1250-NEXT: s_or_b32 s8, s9, s84733; GFX1250-NEXT: s_or_b32 s6, s6, s74734; GFX1250-NEXT: s_and_b32 s7, s8, 34735; GFX1250-NEXT: s_or_b32 s4, s5, s44736; GFX1250-NEXT: s_or_b32 s5, s7, s64737; GFX1250-NEXT: s_and_b32 s3, s3, 154738; GFX1250-NEXT: s_lshl_b32 s4, s4, 44739; GFX1250-NEXT: s_and_b32 s5, s5, 154740; GFX1250-NEXT: s_lshl_b32 s2, s2, 124741; GFX1250-NEXT: s_lshl_b32 s3, s3, 84742; GFX1250-NEXT: s_or_b32 s4, s5, s44743; GFX1250-NEXT: s_and_b32 s0, s0, 0xff4744; GFX1250-NEXT: s_or_b32 s2, s2, s34745; GFX1250-NEXT: s_and_b32 s3, s4, 0xff4746; GFX1250-NEXT: s_or_b32 s0, s0, s14747; GFX1250-NEXT: s_or_b32 s1, s3, s24748; GFX1250-NEXT: s_and_b32 s0, s0, 0xffff4749; GFX1250-NEXT: s_lshl_b32 s1, s1, 164750; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)4751; GFX1250-NEXT: s_or_b32 s0, s0, s14752; GFX1250-NEXT: v_mov_b32_e32 v0, s04753; GFX1250-NEXT: global_store_b32 v[0:1], v0, off4754; GFX1250-NEXT: s_endpgm4755 store <32 x i1> %arg0, ptr addrspace(1) poison4756 ret void4757}4758 4759define amdgpu_cs void @amdgpu_cs_i1_sext(i1 signext %arg0) {4760; SI-LABEL: amdgpu_cs_i1_sext:4761; SI: ; %bb.0:4762; SI-NEXT: v_and_b32_e32 v0, 1, v04763; SI-NEXT: s_mov_b32 s3, 0xf0004764; SI-NEXT: s_mov_b32 s2, -14765; SI-NEXT: buffer_store_byte v0, off, s[0:3], 04766; SI-NEXT: s_endpgm4767;4768; VI-LABEL: amdgpu_cs_i1_sext:4769; VI: ; %bb.0:4770; VI-NEXT: v_and_b32_e32 v0, 1, v04771; VI-NEXT: flat_store_byte v[0:1], v04772; VI-NEXT: s_endpgm4773;4774; GFX11-LABEL: amdgpu_cs_i1_sext:4775; GFX11: ; %bb.0:4776; GFX11-NEXT: v_and_b32_e32 v0, 1, v04777; GFX11-NEXT: global_store_b8 v[0:1], v0, off4778; GFX11-NEXT: s_endpgm4779;4780; GFX1250-LABEL: amdgpu_cs_i1_sext:4781; GFX1250: ; %bb.0:4782; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 14783; GFX1250-NEXT: v_and_b32_e32 v0, 1, v04784; GFX1250-NEXT: global_store_b8 v[0:1], v0, off4785; GFX1250-NEXT: s_endpgm4786 store i1 %arg0, ptr addrspace(1) poison4787 ret void4788}4789 4790define amdgpu_cs void @amdgpu_cs_i1_zext(i1 zeroext %arg0) {4791; SI-LABEL: amdgpu_cs_i1_zext:4792; SI: ; %bb.0:4793; SI-NEXT: s_mov_b32 s3, 0xf0004794; SI-NEXT: s_mov_b32 s2, -14795; SI-NEXT: buffer_store_byte v0, off, s[0:3], 04796; SI-NEXT: s_endpgm4797;4798; VI-LABEL: amdgpu_cs_i1_zext:4799; VI: ; %bb.0:4800; VI-NEXT: flat_store_byte v[0:1], v04801; VI-NEXT: s_endpgm4802;4803; GFX11-LABEL: amdgpu_cs_i1_zext:4804; GFX11: ; %bb.0:4805; GFX11-NEXT: global_store_b8 v[0:1], v0, off4806; GFX11-NEXT: s_endpgm4807;4808; GFX1250-LABEL: amdgpu_cs_i1_zext:4809; GFX1250: ; %bb.0:4810; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 14811; GFX1250-NEXT: global_store_b8 v[0:1], v0, off4812; GFX1250-NEXT: s_endpgm4813 store i1 %arg0, ptr addrspace(1) poison4814 ret void4815}4816 4817attributes #0 = { nounwind noinline }4818;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:4819; GCN: {{.*}}4820