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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck --check-prefix=GFX803 %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX900 %s4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX1010 %s5; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefix=GFX1100 %s6 7define amdgpu_kernel void @test_kern_empty() local_unnamed_addr #0 {8; GFX803-LABEL: test_kern_empty:9; GFX803: ; %bb.0: ; %entry10; GFX803-NEXT: s_endpgm11;12; GFX900-LABEL: test_kern_empty:13; GFX900: ; %bb.0: ; %entry14; GFX900-NEXT: s_endpgm15;16; GFX1010-LABEL: test_kern_empty:17; GFX1010: ; %bb.0: ; %entry18; GFX1010-NEXT: s_endpgm19;20; GFX1100-LABEL: test_kern_empty:21; GFX1100: ; %bb.0: ; %entry22; GFX1100-NEXT: s_endpgm23entry:24 ret void25}26 27define amdgpu_kernel void @test_kern_stack() local_unnamed_addr #0 {28; GFX803-LABEL: test_kern_stack:29; GFX803: ; %bb.0: ; %entry30; GFX803-NEXT: s_add_u32 s0, s0, s1731; GFX803-NEXT: s_addc_u32 s1, s1, 032; GFX803-NEXT: v_mov_b32_e32 v0, 033; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], 034; GFX803-NEXT: s_waitcnt vmcnt(0)35; GFX803-NEXT: s_endpgm36;37; GFX900-LABEL: test_kern_stack:38; GFX900: ; %bb.0: ; %entry39; GFX900-NEXT: s_add_u32 s0, s0, s1740; GFX900-NEXT: s_addc_u32 s1, s1, 041; GFX900-NEXT: v_mov_b32_e32 v0, 042; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], 043; GFX900-NEXT: s_waitcnt vmcnt(0)44; GFX900-NEXT: s_endpgm45;46; GFX1010-LABEL: test_kern_stack:47; GFX1010: ; %bb.0: ; %entry48; GFX1010-NEXT: v_mov_b32_e32 v0, 049; GFX1010-NEXT: s_add_u32 s0, s0, s1750; GFX1010-NEXT: s_addc_u32 s1, s1, 051; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], 052; GFX1010-NEXT: s_waitcnt_vscnt null, 0x053; GFX1010-NEXT: s_endpgm54;55; GFX1100-LABEL: test_kern_stack:56; GFX1100: ; %bb.0: ; %entry57; GFX1100-NEXT: v_mov_b32_e32 v0, 058; GFX1100-NEXT: scratch_store_b32 off, v0, off dlc59; GFX1100-NEXT: s_waitcnt_vscnt null, 0x060; GFX1100-NEXT: s_endpgm61entry:62 %x = alloca i32, align 4, addrspace(5)63 store volatile i32 0, ptr addrspace(5) %x, align 464 ret void65}66 67define amdgpu_kernel void @test_kern_call() local_unnamed_addr #0 {68; GFX803-LABEL: test_kern_call:69; GFX803: ; %bb.0: ; %entry70; GFX803-NEXT: s_add_i32 s12, s12, s1771; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 872; GFX803-NEXT: s_add_u32 s0, s0, s1773; GFX803-NEXT: v_lshlrev_b32_e32 v1, 10, v174; GFX803-NEXT: s_addc_u32 s1, s1, 075; GFX803-NEXT: v_lshlrev_b32_e32 v2, 20, v276; GFX803-NEXT: v_or_b32_e32 v0, v0, v177; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s1378; GFX803-NEXT: s_mov_b32 s13, s1579; GFX803-NEXT: s_mov_b32 s12, s1480; GFX803-NEXT: s_getpc_b64 s[18:19]81; GFX803-NEXT: s_add_u32 s18, s18, ex@rel32@lo+482; GFX803-NEXT: s_addc_u32 s19, s19, ex@rel32@hi+1283; GFX803-NEXT: v_or_b32_e32 v31, v0, v284; GFX803-NEXT: s_mov_b32 s14, s1685; GFX803-NEXT: s_mov_b32 s32, 086; GFX803-NEXT: s_swappc_b64 s[30:31], s[18:19]87; GFX803-NEXT: s_endpgm88;89; GFX900-LABEL: test_kern_call:90; GFX900: ; %bb.0: ; %entry91; GFX900-NEXT: s_add_u32 flat_scratch_lo, s12, s1792; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s13, 093; GFX900-NEXT: s_add_u32 s0, s0, s1794; GFX900-NEXT: s_addc_u32 s1, s1, 095; GFX900-NEXT: v_lshlrev_b32_e32 v2, 20, v296; GFX900-NEXT: v_lshlrev_b32_e32 v1, 10, v197; GFX900-NEXT: s_mov_b32 s13, s1598; GFX900-NEXT: s_mov_b32 s12, s1499; GFX900-NEXT: s_getpc_b64 s[18:19]100; GFX900-NEXT: s_add_u32 s18, s18, ex@rel32@lo+4101; GFX900-NEXT: s_addc_u32 s19, s19, ex@rel32@hi+12102; GFX900-NEXT: v_or3_b32 v31, v0, v1, v2103; GFX900-NEXT: s_mov_b32 s14, s16104; GFX900-NEXT: s_mov_b32 s32, 0105; GFX900-NEXT: s_swappc_b64 s[30:31], s[18:19]106; GFX900-NEXT: s_endpgm107;108; GFX1010-LABEL: test_kern_call:109; GFX1010: ; %bb.0: ; %entry110; GFX1010-NEXT: s_add_u32 s12, s12, s17111; GFX1010-NEXT: s_mov_b32 s32, 0112; GFX1010-NEXT: s_addc_u32 s13, s13, 0113; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12114; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13115; GFX1010-NEXT: v_lshlrev_b32_e32 v2, 20, v2116; GFX1010-NEXT: v_lshlrev_b32_e32 v1, 10, v1117; GFX1010-NEXT: s_add_u32 s0, s0, s17118; GFX1010-NEXT: s_addc_u32 s1, s1, 0119; GFX1010-NEXT: s_mov_b32 s13, s15120; GFX1010-NEXT: s_mov_b32 s12, s14121; GFX1010-NEXT: v_or3_b32 v31, v0, v1, v2122; GFX1010-NEXT: s_getpc_b64 s[18:19]123; GFX1010-NEXT: s_add_u32 s18, s18, ex@rel32@lo+4124; GFX1010-NEXT: s_addc_u32 s19, s19, ex@rel32@hi+12125; GFX1010-NEXT: s_mov_b32 s14, s16126; GFX1010-NEXT: s_swappc_b64 s[30:31], s[18:19]127; GFX1010-NEXT: s_endpgm128;129; GFX1100-LABEL: test_kern_call:130; GFX1100: ; %bb.0: ; %entry131; GFX1100-NEXT: v_mov_b32_e32 v31, v0132; GFX1100-NEXT: s_mov_b32 s12, s13133; GFX1100-NEXT: s_mov_b64 s[10:11], s[6:7]134; GFX1100-NEXT: s_mov_b64 s[8:9], s[4:5]135; GFX1100-NEXT: s_getpc_b64 s[16:17]136; GFX1100-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4137; GFX1100-NEXT: s_addc_u32 s17, s17, ex@rel32@hi+12138; GFX1100-NEXT: s_mov_b64 s[4:5], s[0:1]139; GFX1100-NEXT: s_mov_b64 s[6:7], s[2:3]140; GFX1100-NEXT: s_mov_b32 s13, s14141; GFX1100-NEXT: s_mov_b32 s14, s15142; GFX1100-NEXT: s_mov_b32 s32, 0143; GFX1100-NEXT: s_swappc_b64 s[30:31], s[16:17]144; GFX1100-NEXT: s_endpgm145 146entry:147 tail call void @ex() #0148 ret void149}150 151define amdgpu_kernel void @test_kern_stack_and_call() local_unnamed_addr #0 {152; GFX803-LABEL: test_kern_stack_and_call:153; GFX803: ; %bb.0: ; %entry154; GFX803-NEXT: s_add_i32 s12, s12, s17155; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8156; GFX803-NEXT: s_add_u32 s0, s0, s17157; GFX803-NEXT: v_lshlrev_b32_e32 v1, 10, v1158; GFX803-NEXT: s_addc_u32 s1, s1, 0159; GFX803-NEXT: v_lshlrev_b32_e32 v2, 20, v2160; GFX803-NEXT: v_or_b32_e32 v0, v0, v1161; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13162; GFX803-NEXT: s_mov_b32 s13, s15163; GFX803-NEXT: s_mov_b32 s12, s14164; GFX803-NEXT: v_mov_b32_e32 v3, 0165; GFX803-NEXT: s_getpc_b64 s[18:19]166; GFX803-NEXT: s_add_u32 s18, s18, ex@rel32@lo+4167; GFX803-NEXT: s_addc_u32 s19, s19, ex@rel32@hi+12168; GFX803-NEXT: v_or_b32_e32 v31, v0, v2169; GFX803-NEXT: s_mov_b32 s14, s16170; GFX803-NEXT: s_movk_i32 s32, 0x400171; GFX803-NEXT: buffer_store_dword v3, off, s[0:3], 0172; GFX803-NEXT: s_waitcnt vmcnt(0)173; GFX803-NEXT: s_swappc_b64 s[30:31], s[18:19]174; GFX803-NEXT: s_endpgm175;176; GFX900-LABEL: test_kern_stack_and_call:177; GFX900: ; %bb.0: ; %entry178; GFX900-NEXT: s_add_u32 flat_scratch_lo, s12, s17179; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s13, 0180; GFX900-NEXT: s_add_u32 s0, s0, s17181; GFX900-NEXT: s_addc_u32 s1, s1, 0182; GFX900-NEXT: v_lshlrev_b32_e32 v2, 20, v2183; GFX900-NEXT: v_lshlrev_b32_e32 v1, 10, v1184; GFX900-NEXT: s_mov_b32 s13, s15185; GFX900-NEXT: s_mov_b32 s12, s14186; GFX900-NEXT: v_mov_b32_e32 v3, 0187; GFX900-NEXT: s_getpc_b64 s[18:19]188; GFX900-NEXT: s_add_u32 s18, s18, ex@rel32@lo+4189; GFX900-NEXT: s_addc_u32 s19, s19, ex@rel32@hi+12190; GFX900-NEXT: v_or3_b32 v31, v0, v1, v2191; GFX900-NEXT: s_mov_b32 s14, s16192; GFX900-NEXT: s_movk_i32 s32, 0x400193; GFX900-NEXT: buffer_store_dword v3, off, s[0:3], 0194; GFX900-NEXT: s_waitcnt vmcnt(0)195; GFX900-NEXT: s_swappc_b64 s[30:31], s[18:19]196; GFX900-NEXT: s_endpgm197;198; GFX1010-LABEL: test_kern_stack_and_call:199; GFX1010: ; %bb.0: ; %entry200; GFX1010-NEXT: s_add_u32 s12, s12, s17201; GFX1010-NEXT: s_movk_i32 s32, 0x200202; GFX1010-NEXT: s_addc_u32 s13, s13, 0203; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12204; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13205; GFX1010-NEXT: v_lshlrev_b32_e32 v2, 20, v2206; GFX1010-NEXT: v_lshlrev_b32_e32 v1, 10, v1207; GFX1010-NEXT: v_mov_b32_e32 v3, 0208; GFX1010-NEXT: s_add_u32 s0, s0, s17209; GFX1010-NEXT: s_addc_u32 s1, s1, 0210; GFX1010-NEXT: s_mov_b32 s13, s15211; GFX1010-NEXT: v_or3_b32 v31, v0, v1, v2212; GFX1010-NEXT: s_mov_b32 s12, s14213; GFX1010-NEXT: s_getpc_b64 s[18:19]214; GFX1010-NEXT: s_add_u32 s18, s18, ex@rel32@lo+4215; GFX1010-NEXT: s_addc_u32 s19, s19, ex@rel32@hi+12216; GFX1010-NEXT: s_mov_b32 s14, s16217; GFX1010-NEXT: buffer_store_dword v3, off, s[0:3], 0218; GFX1010-NEXT: s_waitcnt_vscnt null, 0x0219; GFX1010-NEXT: s_swappc_b64 s[30:31], s[18:19]220; GFX1010-NEXT: s_endpgm221;222; GFX1100-LABEL: test_kern_stack_and_call:223; GFX1100: ; %bb.0: ; %entry224; GFX1100-NEXT: v_mov_b32_e32 v1, 0225; GFX1100-NEXT: v_mov_b32_e32 v31, v0226; GFX1100-NEXT: s_mov_b32 s12, s13227; GFX1100-NEXT: s_mov_b64 s[10:11], s[6:7]228; GFX1100-NEXT: s_mov_b64 s[8:9], s[4:5]229; GFX1100-NEXT: s_getpc_b64 s[16:17]230; GFX1100-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4231; GFX1100-NEXT: s_addc_u32 s17, s17, ex@rel32@hi+12232; GFX1100-NEXT: s_mov_b64 s[4:5], s[0:1]233; GFX1100-NEXT: s_mov_b64 s[6:7], s[2:3]234; GFX1100-NEXT: s_mov_b32 s13, s14235; GFX1100-NEXT: s_mov_b32 s14, s15236; GFX1100-NEXT: s_mov_b32 s32, 16237; GFX1100-NEXT: scratch_store_b32 off, v1, off dlc238; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0239; GFX1100-NEXT: s_swappc_b64 s[30:31], s[16:17]240; GFX1100-NEXT: s_endpgm241 242entry:243 %x = alloca i32, align 4, addrspace(5)244 store volatile i32 0, ptr addrspace(5) %x, align 4245 tail call void @ex() #0246 ret void247}248 249define amdgpu_kernel void @test_force_fp_kern_empty() local_unnamed_addr #2 {250; GFX803-LABEL: test_force_fp_kern_empty:251; GFX803: ; %bb.0: ; %entry252; GFX803-NEXT: s_mov_b32 s33, 0253; GFX803-NEXT: s_endpgm254;255; GFX900-LABEL: test_force_fp_kern_empty:256; GFX900: ; %bb.0: ; %entry257; GFX900-NEXT: s_mov_b32 s33, 0258; GFX900-NEXT: s_endpgm259;260; GFX1010-LABEL: test_force_fp_kern_empty:261; GFX1010: ; %bb.0: ; %entry262; GFX1010-NEXT: s_mov_b32 s33, 0263; GFX1010-NEXT: s_endpgm264;265; GFX1100-LABEL: test_force_fp_kern_empty:266; GFX1100: ; %bb.0: ; %entry267; GFX1100-NEXT: s_mov_b32 s33, 0268; GFX1100-NEXT: s_endpgm269 270entry:271 ret void272}273 274define amdgpu_kernel void @test_force_fp_kern_stack() local_unnamed_addr #2 {275; GFX803-LABEL: test_force_fp_kern_stack:276; GFX803: ; %bb.0: ; %entry277; GFX803-NEXT: s_add_u32 s0, s0, s17278; GFX803-NEXT: s_mov_b32 s33, 0279; GFX803-NEXT: s_addc_u32 s1, s1, 0280; GFX803-NEXT: v_mov_b32_e32 v0, 0281; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], s33282; GFX803-NEXT: s_waitcnt vmcnt(0)283; GFX803-NEXT: s_endpgm284;285; GFX900-LABEL: test_force_fp_kern_stack:286; GFX900: ; %bb.0: ; %entry287; GFX900-NEXT: s_add_u32 s0, s0, s17288; GFX900-NEXT: s_mov_b32 s33, 0289; GFX900-NEXT: s_addc_u32 s1, s1, 0290; GFX900-NEXT: v_mov_b32_e32 v0, 0291; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s33292; GFX900-NEXT: s_waitcnt vmcnt(0)293; GFX900-NEXT: s_endpgm294;295; GFX1010-LABEL: test_force_fp_kern_stack:296; GFX1010: ; %bb.0: ; %entry297; GFX1010-NEXT: v_mov_b32_e32 v0, 0298; GFX1010-NEXT: s_add_u32 s0, s0, s17299; GFX1010-NEXT: s_mov_b32 s33, 0300; GFX1010-NEXT: s_addc_u32 s1, s1, 0301; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s33302; GFX1010-NEXT: s_waitcnt_vscnt null, 0x0303; GFX1010-NEXT: s_endpgm304;305; GFX1100-LABEL: test_force_fp_kern_stack:306; GFX1100: ; %bb.0: ; %entry307; GFX1100-NEXT: v_mov_b32_e32 v0, 0308; GFX1100-NEXT: s_mov_b32 s33, 0309; GFX1100-NEXT: scratch_store_b32 off, v0, s33 dlc310; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0311; GFX1100-NEXT: s_endpgm312entry:313 %x = alloca i32, align 4, addrspace(5)314 store volatile i32 0, ptr addrspace(5) %x, align 4315 ret void316}317 318define amdgpu_kernel void @test_force_fp_kern_call() local_unnamed_addr #2 {319; GFX803-LABEL: test_force_fp_kern_call:320; GFX803: ; %bb.0: ; %entry321; GFX803-NEXT: s_add_i32 s12, s12, s17322; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8323; GFX803-NEXT: s_add_u32 s0, s0, s17324; GFX803-NEXT: v_lshlrev_b32_e32 v1, 10, v1325; GFX803-NEXT: s_addc_u32 s1, s1, 0326; GFX803-NEXT: v_lshlrev_b32_e32 v2, 20, v2327; GFX803-NEXT: v_or_b32_e32 v0, v0, v1328; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13329; GFX803-NEXT: s_mov_b32 s13, s15330; GFX803-NEXT: s_mov_b32 s12, s14331; GFX803-NEXT: s_getpc_b64 s[18:19]332; GFX803-NEXT: s_add_u32 s18, s18, ex@rel32@lo+4333; GFX803-NEXT: s_addc_u32 s19, s19, ex@rel32@hi+12334; GFX803-NEXT: v_or_b32_e32 v31, v0, v2335; GFX803-NEXT: s_mov_b32 s14, s16336; GFX803-NEXT: s_mov_b32 s33, 0337; GFX803-NEXT: s_mov_b32 s32, 0338; GFX803-NEXT: s_swappc_b64 s[30:31], s[18:19]339; GFX803-NEXT: s_endpgm340;341; GFX900-LABEL: test_force_fp_kern_call:342; GFX900: ; %bb.0: ; %entry343; GFX900-NEXT: s_add_u32 flat_scratch_lo, s12, s17344; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s13, 0345; GFX900-NEXT: s_add_u32 s0, s0, s17346; GFX900-NEXT: s_addc_u32 s1, s1, 0347; GFX900-NEXT: v_lshlrev_b32_e32 v2, 20, v2348; GFX900-NEXT: v_lshlrev_b32_e32 v1, 10, v1349; GFX900-NEXT: s_mov_b32 s13, s15350; GFX900-NEXT: s_mov_b32 s12, s14351; GFX900-NEXT: s_getpc_b64 s[18:19]352; GFX900-NEXT: s_add_u32 s18, s18, ex@rel32@lo+4353; GFX900-NEXT: s_addc_u32 s19, s19, ex@rel32@hi+12354; GFX900-NEXT: v_or3_b32 v31, v0, v1, v2355; GFX900-NEXT: s_mov_b32 s14, s16356; GFX900-NEXT: s_mov_b32 s33, 0357; GFX900-NEXT: s_mov_b32 s32, 0358; GFX900-NEXT: s_swappc_b64 s[30:31], s[18:19]359; GFX900-NEXT: s_endpgm360;361; GFX1010-LABEL: test_force_fp_kern_call:362; GFX1010: ; %bb.0: ; %entry363; GFX1010-NEXT: s_add_u32 s12, s12, s17364; GFX1010-NEXT: s_mov_b32 s33, 0365; GFX1010-NEXT: s_mov_b32 s32, 0366; GFX1010-NEXT: s_addc_u32 s13, s13, 0367; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12368; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13369; GFX1010-NEXT: v_lshlrev_b32_e32 v2, 20, v2370; GFX1010-NEXT: v_lshlrev_b32_e32 v1, 10, v1371; GFX1010-NEXT: s_add_u32 s0, s0, s17372; GFX1010-NEXT: s_addc_u32 s1, s1, 0373; GFX1010-NEXT: s_mov_b32 s13, s15374; GFX1010-NEXT: s_mov_b32 s12, s14375; GFX1010-NEXT: v_or3_b32 v31, v0, v1, v2376; GFX1010-NEXT: s_getpc_b64 s[18:19]377; GFX1010-NEXT: s_add_u32 s18, s18, ex@rel32@lo+4378; GFX1010-NEXT: s_addc_u32 s19, s19, ex@rel32@hi+12379; GFX1010-NEXT: s_mov_b32 s14, s16380; GFX1010-NEXT: s_swappc_b64 s[30:31], s[18:19]381; GFX1010-NEXT: s_endpgm382;383; GFX1100-LABEL: test_force_fp_kern_call:384; GFX1100: ; %bb.0: ; %entry385; GFX1100-NEXT: v_mov_b32_e32 v31, v0386; GFX1100-NEXT: s_mov_b32 s12, s13387; GFX1100-NEXT: s_mov_b64 s[10:11], s[6:7]388; GFX1100-NEXT: s_mov_b64 s[8:9], s[4:5]389; GFX1100-NEXT: s_getpc_b64 s[16:17]390; GFX1100-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4391; GFX1100-NEXT: s_addc_u32 s17, s17, ex@rel32@hi+12392; GFX1100-NEXT: s_mov_b64 s[4:5], s[0:1]393; GFX1100-NEXT: s_mov_b64 s[6:7], s[2:3]394; GFX1100-NEXT: s_mov_b32 s13, s14395; GFX1100-NEXT: s_mov_b32 s14, s15396; GFX1100-NEXT: s_mov_b32 s33, 0397; GFX1100-NEXT: s_mov_b32 s32, 0398; GFX1100-NEXT: s_swappc_b64 s[30:31], s[16:17]399; GFX1100-NEXT: s_endpgm400; GFX1010-NEXT s_add_u32 s12, s12, s17401; GFX1010-NEXT s_mov_b32 s33, 0402; GFX1010-NEXT s_mov_b32 s32, 0403; GFX1010-NEXT s_addc_u32 s13, s13, 0404; GFX1010-NEXT s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12405; GFX1010-NEXT s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13406; GFX1010-NEXT v_lshlrev_b32_e32 v2, 20, v2407; GFX1010-NEXT v_lshlrev_b32_e32 v1, 10, v1408; GFX1010-NEXT s_add_u32 s0, s0, s17409; GFX1010-NEXT s_addc_u32 s1, s1, 0410; GFX1010-NEXT s_mov_b32 s12, s14411; GFX1010-NEXT s_mov_b32 s13, s15412; GFX1010-NEXT v_or3_b32 v31, v0, v1, v2413; GFX1010-NEXT s_mov_b32 s14, s16414; GFX1010-NEXT s_getpc_b64 s[18:19]415; GFX1010-NEXT s_add_u32 s18, s18, ex@rel32@lo+4416; GFX1010-NEXT s_addc_u32 s19, s19, ex@rel32@hi+12417; GFX1010-NEXT s_swappc_b64 s[30:31], s[18:19]418; GFX1010-NEXT s_endpgm419entry:420 tail call void @ex() #2421 ret void422}423 424define amdgpu_kernel void @test_force_fp_kern_stack_and_call() local_unnamed_addr #2 {425; GFX803-LABEL: test_force_fp_kern_stack_and_call:426; GFX803: ; %bb.0: ; %entry427; GFX803-NEXT: s_add_i32 s12, s12, s17428; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8429; GFX803-NEXT: s_add_u32 s0, s0, s17430; GFX803-NEXT: v_lshlrev_b32_e32 v1, 10, v1431; GFX803-NEXT: s_addc_u32 s1, s1, 0432; GFX803-NEXT: v_lshlrev_b32_e32 v2, 20, v2433; GFX803-NEXT: v_or_b32_e32 v0, v0, v1434; GFX803-NEXT: s_mov_b32 s33, 0435; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13436; GFX803-NEXT: s_mov_b32 s13, s15437; GFX803-NEXT: s_mov_b32 s12, s14438; GFX803-NEXT: v_mov_b32_e32 v3, 0439; GFX803-NEXT: s_getpc_b64 s[18:19]440; GFX803-NEXT: s_add_u32 s18, s18, ex@rel32@lo+4441; GFX803-NEXT: s_addc_u32 s19, s19, ex@rel32@hi+12442; GFX803-NEXT: v_or_b32_e32 v31, v0, v2443; GFX803-NEXT: s_mov_b32 s14, s16444; GFX803-NEXT: s_movk_i32 s32, 0x400445; GFX803-NEXT: buffer_store_dword v3, off, s[0:3], s33446; GFX803-NEXT: s_waitcnt vmcnt(0)447; GFX803-NEXT: s_swappc_b64 s[30:31], s[18:19]448; GFX803-NEXT: s_endpgm449;450; GFX900-LABEL: test_force_fp_kern_stack_and_call:451; GFX900: ; %bb.0: ; %entry452; GFX900-NEXT: s_add_u32 flat_scratch_lo, s12, s17453; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s13, 0454; GFX900-NEXT: s_add_u32 s0, s0, s17455; GFX900-NEXT: s_addc_u32 s1, s1, 0456; GFX900-NEXT: v_lshlrev_b32_e32 v2, 20, v2457; GFX900-NEXT: v_lshlrev_b32_e32 v1, 10, v1458; GFX900-NEXT: s_mov_b32 s33, 0459; GFX900-NEXT: s_mov_b32 s13, s15460; GFX900-NEXT: s_mov_b32 s12, s14461; GFX900-NEXT: v_mov_b32_e32 v3, 0462; GFX900-NEXT: s_getpc_b64 s[18:19]463; GFX900-NEXT: s_add_u32 s18, s18, ex@rel32@lo+4464; GFX900-NEXT: s_addc_u32 s19, s19, ex@rel32@hi+12465; GFX900-NEXT: v_or3_b32 v31, v0, v1, v2466; GFX900-NEXT: s_mov_b32 s14, s16467; GFX900-NEXT: s_movk_i32 s32, 0x400468; GFX900-NEXT: buffer_store_dword v3, off, s[0:3], s33469; GFX900-NEXT: s_waitcnt vmcnt(0)470; GFX900-NEXT: s_swappc_b64 s[30:31], s[18:19]471; GFX900-NEXT: s_endpgm472;473; GFX1010-LABEL: test_force_fp_kern_stack_and_call:474; GFX1010: ; %bb.0: ; %entry475; GFX1010-NEXT: s_add_u32 s12, s12, s17476; GFX1010-NEXT: s_mov_b32 s33, 0477; GFX1010-NEXT: s_movk_i32 s32, 0x200478; GFX1010-NEXT: s_addc_u32 s13, s13, 0479; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12480; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13481; GFX1010-NEXT: v_lshlrev_b32_e32 v2, 20, v2482; GFX1010-NEXT: v_lshlrev_b32_e32 v1, 10, v1483; GFX1010-NEXT: v_mov_b32_e32 v3, 0484; GFX1010-NEXT: s_add_u32 s0, s0, s17485; GFX1010-NEXT: s_addc_u32 s1, s1, 0486; GFX1010-NEXT: s_mov_b32 s13, s15487; GFX1010-NEXT: v_or3_b32 v31, v0, v1, v2488; GFX1010-NEXT: s_mov_b32 s12, s14489; GFX1010-NEXT: s_getpc_b64 s[18:19]490; GFX1010-NEXT: s_add_u32 s18, s18, ex@rel32@lo+4491; GFX1010-NEXT: s_addc_u32 s19, s19, ex@rel32@hi+12492; GFX1010-NEXT: s_mov_b32 s14, s16493; GFX1010-NEXT: buffer_store_dword v3, off, s[0:3], s33494; GFX1010-NEXT: s_waitcnt_vscnt null, 0x0495; GFX1010-NEXT: s_swappc_b64 s[30:31], s[18:19]496; GFX1010-NEXT: s_endpgm497;498; GFX1100-LABEL: test_force_fp_kern_stack_and_call:499; GFX1100: ; %bb.0: ; %entry500; GFX1100-NEXT: v_mov_b32_e32 v1, 0501; GFX1100-NEXT: v_mov_b32_e32 v31, v0502; GFX1100-NEXT: s_mov_b32 s33, 0503; GFX1100-NEXT: s_mov_b32 s12, s13504; GFX1100-NEXT: s_mov_b64 s[10:11], s[6:7]505; GFX1100-NEXT: s_mov_b64 s[8:9], s[4:5]506; GFX1100-NEXT: s_getpc_b64 s[16:17]507; GFX1100-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4508; GFX1100-NEXT: s_addc_u32 s17, s17, ex@rel32@hi+12509; GFX1100-NEXT: s_mov_b64 s[4:5], s[0:1]510; GFX1100-NEXT: s_mov_b64 s[6:7], s[2:3]511; GFX1100-NEXT: s_mov_b32 s13, s14512; GFX1100-NEXT: s_mov_b32 s14, s15513; GFX1100-NEXT: s_mov_b32 s32, 16514; GFX1100-NEXT: scratch_store_b32 off, v1, s33 dlc515; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0516; GFX1100-NEXT: s_swappc_b64 s[30:31], s[16:17]517; GFX1100-NEXT: s_endpgm518entry:519 %x = alloca i32, align 4, addrspace(5)520 store volatile i32 0, ptr addrspace(5) %x, align 4521 tail call void @ex() #2522 ret void523}524 525define amdgpu_kernel void @test_sgpr_offset_kernel() #1 {526; GFX803-LABEL: test_sgpr_offset_kernel:527; GFX803: ; %bb.0: ; %entry528; GFX803-NEXT: s_add_u32 s0, s0, s17529; GFX803-NEXT: s_addc_u32 s1, s1, 0530; GFX803-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 glc531; GFX803-NEXT: s_waitcnt vmcnt(0)532; GFX803-NEXT: s_mov_b32 s4, 0x40000533; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], s4 ; 4-byte Folded Spill534; GFX803-NEXT: ;;#ASMSTART535; GFX803-NEXT: ;;#ASMEND536; GFX803-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; 4-byte Folded Reload537; GFX803-NEXT: s_waitcnt vmcnt(0)538; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8539; GFX803-NEXT: s_waitcnt vmcnt(0)540; GFX803-NEXT: s_endpgm541;542; GFX900-LABEL: test_sgpr_offset_kernel:543; GFX900: ; %bb.0: ; %entry544; GFX900-NEXT: s_add_u32 s0, s0, s17545; GFX900-NEXT: s_addc_u32 s1, s1, 0546; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 glc547; GFX900-NEXT: s_waitcnt vmcnt(0)548; GFX900-NEXT: s_mov_b32 s4, 0x40000549; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s4 ; 4-byte Folded Spill550; GFX900-NEXT: ;;#ASMSTART551; GFX900-NEXT: ;;#ASMEND552; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; 4-byte Folded Reload553; GFX900-NEXT: s_waitcnt vmcnt(0)554; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8555; GFX900-NEXT: s_waitcnt vmcnt(0)556; GFX900-NEXT: s_endpgm557;558; GFX1010-LABEL: test_sgpr_offset_kernel:559; GFX1010: ; %bb.0: ; %entry560; GFX1010-NEXT: s_add_u32 s0, s0, s17561; GFX1010-NEXT: s_addc_u32 s1, s1, 0562; GFX1010-NEXT: s_mov_b32 s4, 0x20000563; GFX1010-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 glc dlc564; GFX1010-NEXT: s_waitcnt vmcnt(0)565; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s4 ; 4-byte Folded Spill566; GFX1010-NEXT: ;;#ASMSTART567; GFX1010-NEXT: ;;#ASMEND568; GFX1010-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; 4-byte Folded Reload569; GFX1010-NEXT: s_waitcnt vmcnt(0)570; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8571; GFX1010-NEXT: s_waitcnt_vscnt null, 0x0572; GFX1010-NEXT: s_endpgm573;574; GFX1100-LABEL: test_sgpr_offset_kernel:575; GFX1100: ; %bb.0: ; %entry576; GFX1100-NEXT: scratch_load_b32 v0, off, off offset:8 glc dlc577; GFX1100-NEXT: s_waitcnt vmcnt(0)578; GFX1100-NEXT: s_movk_i32 s0, 0x1000579; GFX1100-NEXT: scratch_store_b32 off, v0, s0 ; 4-byte Folded Spill580; GFX1100-NEXT: ;;#ASMSTART581; GFX1100-NEXT: ;;#ASMEND582; GFX1100-NEXT: scratch_load_b32 v0, off, s0 ; 4-byte Folded Reload583; GFX1100-NEXT: s_waitcnt vmcnt(0)584; GFX1100-NEXT: scratch_store_b32 off, v0, off offset:8 dlc585; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0586; GFX1100-NEXT: s_endpgm587entry:588 ; Occupy 4096 bytes of scratch, so the offset of the spill of %a does not589 ; fit in the instruction, and has to live in the SGPR offset.590 %alloca = alloca i8, i32 4092, align 4, addrspace(5)591 592 %aptr = getelementptr i32, ptr addrspace(5) %alloca, i32 1593 ; 0x40000 / 64 = 4096 (for wave64)594 ; CHECK: s_add_u32 s6, s7, 0x40000595 ; CHECK: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s6 ; 4-byte Folded Spill596 %a = load volatile i32, ptr addrspace(5) %aptr597 598 ; Force %a to spill599 call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()600 601 %outptr = getelementptr i32, ptr addrspace(5) %alloca, i32 1602 store volatile i32 %a, ptr addrspace(5) %outptr603 604 ret void605}606 607declare hidden void @ex() local_unnamed_addr #0608 609attributes #0 = { nounwind }610attributes #1 = { nounwind "amdgpu-num-vgpr"="8" }611attributes #2 = { nounwind "frame-pointer"="all" }612 613