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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=OPT %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=GCN %s4 5; Make sure we match the addressing mode offset of csub intrinsics across blocks.6 7define amdgpu_kernel void @test_sink_small_offset_global_atomic_csub_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {8; OPT-LABEL: @test_sink_small_offset_global_atomic_csub_i32(9; OPT-NEXT: entry:10; OPT-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #[[ATTR3:[0-9]+]]11; OPT-NEXT: [[CMP:%.*]] = icmp eq i32 [[TID]], 012; OPT-NEXT: br i1 [[CMP]], label [[ENDIF:%.*]], label [[IF:%.*]]13; OPT: if:14; OPT-NEXT: [[IN_GEP:%.*]] = getelementptr i32, ptr addrspace(1) [[IN:%.*]], i32 715; OPT-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.global.atomic.csub.p1(ptr addrspace(1) [[IN_GEP]], i32 2)16; OPT-NEXT: br label [[ENDIF]]17; OPT: endif:18; OPT-NEXT: [[X:%.*]] = phi i32 [ [[VAL]], [[IF]] ], [ 0, [[ENTRY:%.*]] ]19; OPT-NEXT: [[OUT_GEP:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT:%.*]], i32 99999920; OPT-NEXT: store i32 [[X]], ptr addrspace(1) [[OUT_GEP]], align 421; OPT-NEXT: br label [[DONE:%.*]]22; OPT: done:23; OPT-NEXT: ret void24;25; GCN-LABEL: test_sink_small_offset_global_atomic_csub_i32:26; GCN: ; %bb.0: ; %entry27; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x028; GCN-NEXT: v_mbcnt_lo_u32_b32 v1, -1, 029; GCN-NEXT: v_mov_b32_e32 v0, 030; GCN-NEXT: s_mov_b32 s4, exec_lo31; GCN-NEXT: v_cmpx_ne_u32_e32 0, v132; GCN-NEXT: s_cbranch_execz .LBB0_233; GCN-NEXT: ; %bb.1: ; %if34; GCN-NEXT: v_mov_b32_e32 v0, 035; GCN-NEXT: v_mov_b32_e32 v1, 236; GCN-NEXT: s_waitcnt lgkmcnt(0)37; GCN-NEXT: global_atomic_csub v0, v0, v1, s[2:3] offset:28 glc38; GCN-NEXT: .LBB0_2: ; %endif39; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s440; GCN-NEXT: v_mov_b32_e32 v1, 0x3d080041; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)42; GCN-NEXT: global_store_dword v1, v0, s[0:1] offset:25243; GCN-NEXT: s_endpgm44entry:45 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #046 %cmp = icmp eq i32 %tid, 047 br i1 %cmp, label %endif, label %if48 49if:50 %in.gep = getelementptr i32, ptr addrspace(1) %in, i32 751 %val = call i32 @llvm.amdgcn.global.atomic.csub.p1(ptr addrspace(1) %in.gep, i32 2)52 br label %endif53 54endif:55 %x = phi i32 [ %val, %if ], [ 0, %entry ]56 %out.gep = getelementptr i32, ptr addrspace(1) %out, i32 99999957 store i32 %x, ptr addrspace(1) %out.gep58 br label %done59 60done:61 ret void62}63 64declare i32 @llvm.amdgcn.global.atomic.csub.p1(ptr addrspace(1) nocapture, i32) #065declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #166 67attributes #0 = { argmemonly nounwind }68attributes #1 = { nounwind readnone willreturn }69attributes #2 = { argmemonly nounwind willreturn }70