375 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s -check-prefixes=GFX6789,GFX678,GFX689,GFX67,GFX63; RUN: llc -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck %s -check-prefixes=GFX6789,GFX678,GFX67,GFX74; RUN: llc -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck %s -check-prefixes=GFX6789,GFX678,GFX689,GFX895; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefixes=GFX6789,GFX689,GFX89,GFX96; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s -check-prefixes=GFX127 8define amdgpu_cs void @test_sink_smem_offset_400(ptr addrspace(4) inreg %ptr, i32 inreg %val) {9; GFX67-LABEL: test_sink_smem_offset_400:10; GFX67: ; %bb.0: ; %entry11; GFX67-NEXT: .LBB0_1: ; %loop12; GFX67-NEXT: ; =>This Inner Loop Header: Depth=113; GFX67-NEXT: s_waitcnt lgkmcnt(0)14; GFX67-NEXT: s_load_dword s3, s[0:1], 0x6415; GFX67-NEXT: s_add_i32 s2, s2, -116; GFX67-NEXT: s_cmp_lg_u32 s2, 017; GFX67-NEXT: s_cbranch_scc1 .LBB0_118; GFX67-NEXT: ; %bb.2: ; %end19; GFX67-NEXT: s_endpgm20;21; GFX89-LABEL: test_sink_smem_offset_400:22; GFX89: ; %bb.0: ; %entry23; GFX89-NEXT: .LBB0_1: ; %loop24; GFX89-NEXT: ; =>This Inner Loop Header: Depth=125; GFX89-NEXT: s_waitcnt lgkmcnt(0)26; GFX89-NEXT: s_load_dword s3, s[0:1], 0x19027; GFX89-NEXT: s_add_i32 s2, s2, -128; GFX89-NEXT: s_cmp_lg_u32 s2, 029; GFX89-NEXT: s_cbranch_scc1 .LBB0_130; GFX89-NEXT: ; %bb.2: ; %end31; GFX89-NEXT: s_endpgm32;33; GFX12-LABEL: test_sink_smem_offset_400:34; GFX12: ; %bb.0: ; %entry35; GFX12-NEXT: .LBB0_1: ; %loop36; GFX12-NEXT: ; =>This Inner Loop Header: Depth=137; GFX12-NEXT: s_wait_kmcnt 0x038; GFX12-NEXT: s_load_b32 s3, s[0:1], 0x19039; GFX12-NEXT: s_add_co_i32 s2, s2, -140; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)41; GFX12-NEXT: s_cmp_lg_u32 s2, 042; GFX12-NEXT: s_cbranch_scc1 .LBB0_143; GFX12-NEXT: ; %bb.2: ; %end44; GFX12-NEXT: s_endpgm45entry:46 %gep = getelementptr i8, ptr addrspace(4) %ptr, i64 40047 br label %loop48 49loop:50 %count = phi i32 [ %dec, %loop ], [ %val, %entry ]51 %dec = sub i32 %count, 152 %load = load volatile i32, ptr addrspace(4) %gep53 %cond = icmp eq i32 %dec, 054 br i1 %cond, label %end, label %loop55 56end:57 ret void58}59 60define amdgpu_cs void @test_sink_smem_offset_4000(ptr addrspace(4) inreg %ptr, i32 inreg %val) {61; GFX6-LABEL: test_sink_smem_offset_4000:62; GFX6: ; %bb.0: ; %entry63; GFX6-NEXT: s_add_u32 s0, s0, 0xfa064; GFX6-NEXT: s_addc_u32 s1, s1, 065; GFX6-NEXT: .LBB1_1: ; %loop66; GFX6-NEXT: ; =>This Inner Loop Header: Depth=167; GFX6-NEXT: s_waitcnt lgkmcnt(0)68; GFX6-NEXT: s_load_dword s3, s[0:1], 0x069; GFX6-NEXT: s_add_i32 s2, s2, -170; GFX6-NEXT: s_cmp_lg_u32 s2, 071; GFX6-NEXT: s_cbranch_scc1 .LBB1_172; GFX6-NEXT: ; %bb.2: ; %end73; GFX6-NEXT: s_endpgm74;75; GFX7-LABEL: test_sink_smem_offset_4000:76; GFX7: ; %bb.0: ; %entry77; GFX7-NEXT: .LBB1_1: ; %loop78; GFX7-NEXT: ; =>This Inner Loop Header: Depth=179; GFX7-NEXT: s_waitcnt lgkmcnt(0)80; GFX7-NEXT: s_load_dword s3, s[0:1], 0x3e881; GFX7-NEXT: s_add_i32 s2, s2, -182; GFX7-NEXT: s_cmp_lg_u32 s2, 083; GFX7-NEXT: s_cbranch_scc1 .LBB1_184; GFX7-NEXT: ; %bb.2: ; %end85; GFX7-NEXT: s_endpgm86;87; GFX89-LABEL: test_sink_smem_offset_4000:88; GFX89: ; %bb.0: ; %entry89; GFX89-NEXT: .LBB1_1: ; %loop90; GFX89-NEXT: ; =>This Inner Loop Header: Depth=191; GFX89-NEXT: s_waitcnt lgkmcnt(0)92; GFX89-NEXT: s_load_dword s3, s[0:1], 0xfa093; GFX89-NEXT: s_add_i32 s2, s2, -194; GFX89-NEXT: s_cmp_lg_u32 s2, 095; GFX89-NEXT: s_cbranch_scc1 .LBB1_196; GFX89-NEXT: ; %bb.2: ; %end97; GFX89-NEXT: s_endpgm98;99; GFX12-LABEL: test_sink_smem_offset_4000:100; GFX12: ; %bb.0: ; %entry101; GFX12-NEXT: .LBB1_1: ; %loop102; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1103; GFX12-NEXT: s_wait_kmcnt 0x0104; GFX12-NEXT: s_load_b32 s3, s[0:1], 0xfa0105; GFX12-NEXT: s_add_co_i32 s2, s2, -1106; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)107; GFX12-NEXT: s_cmp_lg_u32 s2, 0108; GFX12-NEXT: s_cbranch_scc1 .LBB1_1109; GFX12-NEXT: ; %bb.2: ; %end110; GFX12-NEXT: s_endpgm111entry:112 %gep = getelementptr i8, ptr addrspace(4) %ptr, i64 4000113 br label %loop114 115loop:116 %count = phi i32 [ %dec, %loop ], [ %val, %entry ]117 %dec = sub i32 %count, 1118 %load = load volatile i32, ptr addrspace(4) %gep119 %cond = icmp eq i32 %dec, 0120 br i1 %cond, label %end, label %loop121 122end:123 ret void124}125 126define amdgpu_cs void @test_sink_smem_offset_4000000(ptr addrspace(4) inreg %ptr, i32 inreg %val) {127; GFX689-LABEL: test_sink_smem_offset_4000000:128; GFX689: ; %bb.0: ; %entry129; GFX689-NEXT: s_add_u32 s0, s0, 0x3d0900130; GFX689-NEXT: s_addc_u32 s1, s1, 0131; GFX689-NEXT: .LBB2_1: ; %loop132; GFX689-NEXT: ; =>This Inner Loop Header: Depth=1133; GFX689-NEXT: s_waitcnt lgkmcnt(0)134; GFX689-NEXT: s_load_dword s3, s[0:1], 0x0135; GFX689-NEXT: s_add_i32 s2, s2, -1136; GFX689-NEXT: s_cmp_lg_u32 s2, 0137; GFX689-NEXT: s_cbranch_scc1 .LBB2_1138; GFX689-NEXT: ; %bb.2: ; %end139; GFX689-NEXT: s_endpgm140;141; GFX7-LABEL: test_sink_smem_offset_4000000:142; GFX7: ; %bb.0: ; %entry143; GFX7-NEXT: .LBB2_1: ; %loop144; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1145; GFX7-NEXT: s_waitcnt lgkmcnt(0)146; GFX7-NEXT: s_load_dword s3, s[0:1], 0xf4240147; GFX7-NEXT: s_add_i32 s2, s2, -1148; GFX7-NEXT: s_cmp_lg_u32 s2, 0149; GFX7-NEXT: s_cbranch_scc1 .LBB2_1150; GFX7-NEXT: ; %bb.2: ; %end151; GFX7-NEXT: s_endpgm152;153; GFX12-LABEL: test_sink_smem_offset_4000000:154; GFX12: ; %bb.0: ; %entry155; GFX12-NEXT: .LBB2_1: ; %loop156; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1157; GFX12-NEXT: s_wait_kmcnt 0x0158; GFX12-NEXT: s_load_b32 s3, s[0:1], 0x3d0900159; GFX12-NEXT: s_add_co_i32 s2, s2, -1160; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)161; GFX12-NEXT: s_cmp_lg_u32 s2, 0162; GFX12-NEXT: s_cbranch_scc1 .LBB2_1163; GFX12-NEXT: ; %bb.2: ; %end164; GFX12-NEXT: s_endpgm165entry:166 %gep = getelementptr i8, ptr addrspace(4) %ptr, i64 4000000167 br label %loop168 169loop:170 %count = phi i32 [ %dec, %loop ], [ %val, %entry ]171 %dec = sub i32 %count, 1172 %load = load volatile i32, ptr addrspace(4) %gep173 %cond = icmp eq i32 %dec, 0174 br i1 %cond, label %end, label %loop175 176end:177 ret void178}179 180define amdgpu_cs void @test_sink_smem_offset_40000000(ptr addrspace(4) inreg %ptr, i32 inreg %val) {181; GFX689-LABEL: test_sink_smem_offset_40000000:182; GFX689: ; %bb.0: ; %entry183; GFX689-NEXT: s_add_u32 s0, s0, 0x2625a00184; GFX689-NEXT: s_addc_u32 s1, s1, 0185; GFX689-NEXT: .LBB3_1: ; %loop186; GFX689-NEXT: ; =>This Inner Loop Header: Depth=1187; GFX689-NEXT: s_waitcnt lgkmcnt(0)188; GFX689-NEXT: s_load_dword s3, s[0:1], 0x0189; GFX689-NEXT: s_add_i32 s2, s2, -1190; GFX689-NEXT: s_cmp_lg_u32 s2, 0191; GFX689-NEXT: s_cbranch_scc1 .LBB3_1192; GFX689-NEXT: ; %bb.2: ; %end193; GFX689-NEXT: s_endpgm194;195; GFX7-LABEL: test_sink_smem_offset_40000000:196; GFX7: ; %bb.0: ; %entry197; GFX7-NEXT: .LBB3_1: ; %loop198; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1199; GFX7-NEXT: s_waitcnt lgkmcnt(0)200; GFX7-NEXT: s_load_dword s3, s[0:1], 0x989680201; GFX7-NEXT: s_add_i32 s2, s2, -1202; GFX7-NEXT: s_cmp_lg_u32 s2, 0203; GFX7-NEXT: s_cbranch_scc1 .LBB3_1204; GFX7-NEXT: ; %bb.2: ; %end205; GFX7-NEXT: s_endpgm206;207; GFX12-LABEL: test_sink_smem_offset_40000000:208; GFX12: ; %bb.0: ; %entry209; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], 0x2625a00210; GFX12-NEXT: .LBB3_1: ; %loop211; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1212; GFX12-NEXT: s_wait_kmcnt 0x0213; GFX12-NEXT: s_load_b32 s3, s[0:1], 0x0214; GFX12-NEXT: s_add_co_i32 s2, s2, -1215; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)216; GFX12-NEXT: s_cmp_lg_u32 s2, 0217; GFX12-NEXT: s_cbranch_scc1 .LBB3_1218; GFX12-NEXT: ; %bb.2: ; %end219; GFX12-NEXT: s_endpgm220entry:221 %gep = getelementptr i8, ptr addrspace(4) %ptr, i64 40000000222 br label %loop223 224loop:225 %count = phi i32 [ %dec, %loop ], [ %val, %entry ]226 %dec = sub i32 %count, 1227 %load = load volatile i32, ptr addrspace(4) %gep228 %cond = icmp eq i32 %dec, 0229 br i1 %cond, label %end, label %loop230 231end:232 ret void233}234 235define amdgpu_cs void @test_sink_smem_offset_40000000000(ptr addrspace(4) inreg %ptr, i32 inreg %val) {236; GFX6789-LABEL: test_sink_smem_offset_40000000000:237; GFX6789: ; %bb.0: ; %entry238; GFX6789-NEXT: s_add_u32 s0, s0, 0x502f9000239; GFX6789-NEXT: s_addc_u32 s1, s1, 9240; GFX6789-NEXT: .LBB4_1: ; %loop241; GFX6789-NEXT: ; =>This Inner Loop Header: Depth=1242; GFX6789-NEXT: s_waitcnt lgkmcnt(0)243; GFX6789-NEXT: s_load_dword s3, s[0:1], 0x0244; GFX6789-NEXT: s_add_i32 s2, s2, -1245; GFX6789-NEXT: s_cmp_lg_u32 s2, 0246; GFX6789-NEXT: s_cbranch_scc1 .LBB4_1247; GFX6789-NEXT: ; %bb.2: ; %end248; GFX6789-NEXT: s_endpgm249;250; GFX12-LABEL: test_sink_smem_offset_40000000000:251; GFX12: ; %bb.0: ; %entry252; GFX12-NEXT: s_mov_b32 s4, 0x502f9000253; GFX12-NEXT: s_mov_b32 s5, 9254; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)255; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]256; GFX12-NEXT: .LBB4_1: ; %loop257; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1258; GFX12-NEXT: s_wait_kmcnt 0x0259; GFX12-NEXT: s_load_b32 s3, s[0:1], 0x0260; GFX12-NEXT: s_add_co_i32 s2, s2, -1261; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)262; GFX12-NEXT: s_cmp_lg_u32 s2, 0263; GFX12-NEXT: s_cbranch_scc1 .LBB4_1264; GFX12-NEXT: ; %bb.2: ; %end265; GFX12-NEXT: s_endpgm266entry:267 %gep = getelementptr i8, ptr addrspace(4) %ptr, i64 40000000000268 br label %loop269 270loop:271 %count = phi i32 [ %dec, %loop ], [ %val, %entry ]272 %dec = sub i32 %count, 1273 %load = load volatile i32, ptr addrspace(4) %gep274 %cond = icmp eq i32 %dec, 0275 br i1 %cond, label %end, label %loop276 277end:278 ret void279}280 281define amdgpu_cs void @test_sink_smem_offset_neg400(ptr addrspace(4) inreg %ptr, i32 inreg %val) {282; GFX6789-LABEL: test_sink_smem_offset_neg400:283; GFX6789: ; %bb.0: ; %entry284; GFX6789-NEXT: s_add_u32 s0, s0, 0xfffffe70285; GFX6789-NEXT: s_addc_u32 s1, s1, -1286; GFX6789-NEXT: .LBB5_1: ; %loop287; GFX6789-NEXT: ; =>This Inner Loop Header: Depth=1288; GFX6789-NEXT: s_waitcnt lgkmcnt(0)289; GFX6789-NEXT: s_load_dword s3, s[0:1], 0x0290; GFX6789-NEXT: s_add_i32 s2, s2, -1291; GFX6789-NEXT: s_cmp_lg_u32 s2, 0292; GFX6789-NEXT: s_cbranch_scc1 .LBB5_1293; GFX6789-NEXT: ; %bb.2: ; %end294; GFX6789-NEXT: s_endpgm295;296; GFX12-LABEL: test_sink_smem_offset_neg400:297; GFX12: ; %bb.0: ; %entry298; GFX12-NEXT: s_movk_i32 s4, 0xfe70299; GFX12-NEXT: s_mov_b32 s5, -1300; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)301; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]302; GFX12-NEXT: .LBB5_1: ; %loop303; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1304; GFX12-NEXT: s_wait_kmcnt 0x0305; GFX12-NEXT: s_load_b32 s3, s[0:1], 0x0306; GFX12-NEXT: s_add_co_i32 s2, s2, -1307; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)308; GFX12-NEXT: s_cmp_lg_u32 s2, 0309; GFX12-NEXT: s_cbranch_scc1 .LBB5_1310; GFX12-NEXT: ; %bb.2: ; %end311; GFX12-NEXT: s_endpgm312entry:313 %gep = getelementptr i8, ptr addrspace(4) %ptr, i64 -400314 br label %loop315 316loop:317 %count = phi i32 [ %dec, %loop ], [ %val, %entry ]318 %dec = sub i32 %count, 1319 %load = load volatile i32, ptr addrspace(4) %gep320 %cond = icmp eq i32 %dec, 0321 br i1 %cond, label %end, label %loop322 323end:324 ret void325}326 327; Same for address space 6, constant 32-bit.328define amdgpu_cs void @test_sink_smem_offset_neg400_32bit(ptr addrspace(6) inreg %ptr, i32 inreg %val) {329; GFX6789-LABEL: test_sink_smem_offset_neg400_32bit:330; GFX6789: ; %bb.0: ; %entry331; GFX6789-NEXT: s_add_i32 s2, s0, 0xfffffe70332; GFX6789-NEXT: s_mov_b32 s3, 0333; GFX6789-NEXT: .LBB6_1: ; %loop334; GFX6789-NEXT: ; =>This Inner Loop Header: Depth=1335; GFX6789-NEXT: s_waitcnt lgkmcnt(0)336; GFX6789-NEXT: s_load_dword s0, s[2:3], 0x0337; GFX6789-NEXT: s_add_i32 s1, s1, -1338; GFX6789-NEXT: s_cmp_lg_u32 s1, 0339; GFX6789-NEXT: s_cbranch_scc1 .LBB6_1340; GFX6789-NEXT: ; %bb.2: ; %end341; GFX6789-NEXT: s_endpgm342;343; GFX12-LABEL: test_sink_smem_offset_neg400_32bit:344; GFX12: ; %bb.0: ; %entry345; GFX12-NEXT: s_add_co_i32 s2, s0, 0xfffffe70346; GFX12-NEXT: s_mov_b32 s3, 0347; GFX12-NEXT: .LBB6_1: ; %loop348; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1349; GFX12-NEXT: s_wait_kmcnt 0x0350; GFX12-NEXT: s_load_b32 s0, s[2:3], 0x0351; GFX12-NEXT: s_add_co_i32 s1, s1, -1352; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)353; GFX12-NEXT: s_cmp_lg_u32 s1, 0354; GFX12-NEXT: s_cbranch_scc1 .LBB6_1355; GFX12-NEXT: ; %bb.2: ; %end356; GFX12-NEXT: s_endpgm357entry:358 %gep = getelementptr i8, ptr addrspace(6) %ptr, i64 -400359 br label %loop360 361loop:362 %count = phi i32 [ %dec, %loop ], [ %val, %entry ]363 %dec = sub i32 %count, 1364 %load = load volatile i32, ptr addrspace(6) %gep365 %cond = icmp eq i32 %dec, 0366 br i1 %cond, label %end, label %loop367 368end:369 ret void370}371 372;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:373; GFX678: {{.*}}374; GFX9: {{.*}}375