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1; RUN: opt -S -mtriple=amdgcn-- -codegenprepare < %s | FileCheck -check-prefix=OPT %s2; RUN: opt -S -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -codegenprepare < %s | FileCheck -check-prefix=OPT %s3; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s4; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN %s5 6; This particular case will actually be worse in terms of code size7; from sinking into both.8 9; OPT-LABEL: @sink_ubfe_i32(10; OPT: entry:11; OPT-NEXT: br i112 13; OPT: bb0:14; OPT: %0 = lshr i32 %arg1, 815; OPT-NEXT: %val0 = and i32 %0, 25516; OPT: br label17 18; OPT: bb1:19; OPT: %1 = lshr i32 %arg1, 820; OPT-NEXT: %val1 = and i32 %1, 12721; OPT: br label22 23; OPT: ret:24; OPT: store25; OPT: ret26 27 28; GCN-LABEL: {{^}}sink_ubfe_i32:29; GCN-NOT: lshr30; GCN: s_cbranch_scc{{[0-1]}}31 32; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x7000833; GCN: .LBB0_3:34; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x8000835 36; GCN: buffer_store_dword37; GCN: s_endpgm38define amdgpu_kernel void @sink_ubfe_i32(ptr addrspace(1) %out, i32 %arg1, i1 %arg) #0 {39entry:40 %shr = lshr i32 %arg1, 841 br i1 %arg, label %bb0, label %bb142 43bb0:44 %val0 = and i32 %shr, 25545 store volatile i32 0, ptr addrspace(1) poison46 br label %ret47 48bb1:49 %val1 = and i32 %shr, 12750 store volatile i32 0, ptr addrspace(1) poison51 br label %ret52 53ret:54 %phi = phi i32 [ %val0, %bb0 ], [ %val1, %bb1 ]55 store i32 %phi, ptr addrspace(1) %out56 ret void57}58 59; OPT-LABEL: @sink_sbfe_i32(60; OPT: entry:61; OPT-NEXT: br i162 63; OPT: bb0:64; OPT: %0 = ashr i32 %arg1, 865; OPT-NEXT: %val0 = and i32 %0, 25566; OPT: br label67 68; OPT: bb1:69; OPT: %1 = ashr i32 %arg1, 870; OPT-NEXT: %val1 = and i32 %1, 12771; OPT: br label72 73; OPT: ret:74; OPT: store75; OPT: ret76 77; GCN-LABEL: {{^}}sink_sbfe_i32:78define amdgpu_kernel void @sink_sbfe_i32(ptr addrspace(1) %out, i32 %arg1, i1 %arg) #0 {79entry:80 %shr = ashr i32 %arg1, 881 br i1 %arg, label %bb0, label %bb182 83bb0:84 %val0 = and i32 %shr, 25585 store volatile i32 0, ptr addrspace(1) poison86 br label %ret87 88bb1:89 %val1 = and i32 %shr, 12790 store volatile i32 0, ptr addrspace(1) poison91 br label %ret92 93ret:94 %phi = phi i32 [ %val0, %bb0 ], [ %val1, %bb1 ]95 store i32 %phi, ptr addrspace(1) %out96 ret void97}98 99 100; OPT-LABEL: @sink_ubfe_i16(101; OPT: entry:102; OPT-NEXT: icmp103; OPT-NEXT: br i1104 105; OPT: bb0:106; OPT: [[LSHR0:%[0-9]+]] = lshr i16 %arg1, 4107; OPT-NEXT: %val0 = and i16 [[LSHR0]], 255108; OPT: br label109 110; OPT: bb1:111; OPT: [[LSHR1:%[0-9]+]] = lshr i16 %arg1, 4112; OPT-NEXT: %val1 = and i16 [[LSHR1]], 127113; OPT: br label114 115; OPT: ret:116; OPT: store117; OPT: ret118 119; GCN-LABEL: {{^}}sink_ubfe_i16:120; GCN-NOT: lshr121; GCN: s_cbranch_scc{{[0-1]}}122 123; GCN: ; %bb.1:124; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x70004125 126; GCN: .LBB2_2:127; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80004128 129; GCN: buffer_store_short130; GCN: s_endpgm131define amdgpu_kernel void @sink_ubfe_i16(ptr addrspace(1) %out, i16 %arg1, [8 x i32], i32 %arg2) #0 {132entry:133 %shr = lshr i16 %arg1, 4134 %cond = icmp eq i32 %arg2, 0135 br i1 %cond, label %bb0, label %bb1136 137bb0:138 %val0 = and i16 %shr, 255139 store volatile i16 0, ptr addrspace(1) poison140 br label %ret141 142bb1:143 %val1 = and i16 %shr, 127144 store volatile i16 0, ptr addrspace(1) poison145 br label %ret146 147ret:148 %phi = phi i16 [ %val0, %bb0 ], [ %val1, %bb1 ]149 store i16 %phi, ptr addrspace(1) %out150 ret void151}152 153; We don't really want to sink this one since it isn't reducible to a154; 32-bit BFE on one half of the integer.155 156; OPT-LABEL: @sink_ubfe_i64_span_midpoint(157; OPT: entry:158; OPT-NOT: lshr159; OPT: br i1160 161; OPT: bb0:162; OPT: %0 = lshr i64 %arg1, 30163; OPT-NEXT: %val0 = and i64 %0, 255164 165; OPT: bb1:166; OPT: %1 = lshr i64 %arg1, 30167; OPT-NEXT: %val1 = and i64 %1, 127168 169; OPT: ret:170; OPT: store171; OPT: ret172 173; GCN-LABEL: {{^}}sink_ubfe_i64_span_midpoint:174 175; GCN: s_cbranch_scc{{[0-1]}} .LBB3_2176; GCN: s_lshr_b64 s[[[LO:[0-9]+]]:[[HI:[0-9]+]]], s[[[LO2:[0-9]+]]:[[HI2:[0-9]+]]], 30177; GCN: s_and_b32 s{{[0-9]+}}, s[[LO]], 0x7f178 179; GCN: .LBB3_3:180; GCN: s_lshr_b64 s[[[LO3:[0-9]+]]:[[HI3:[0-9]+]]], s[[[LO4:[0-9]+]]:[[HI4:[0-9]+]]], 30181; GCN: s_and_b32 s{{[0-9]+}}, s[[LO3]], 0xff182 183; GCN: buffer_store_dwordx2184define amdgpu_kernel void @sink_ubfe_i64_span_midpoint(ptr addrspace(1) %out, i64 %arg1, i1 %arg) #0 {185entry:186 %shr = lshr i64 %arg1, 30187 br i1 %arg, label %bb0, label %bb1188 189bb0:190 %val0 = and i64 %shr, 255191 store volatile i32 0, ptr addrspace(1) poison192 br label %ret193 194bb1:195 %val1 = and i64 %shr, 127196 store volatile i32 0, ptr addrspace(1) poison197 br label %ret198 199ret:200 %phi = phi i64 [ %val0, %bb0 ], [ %val1, %bb1 ]201 store i64 %phi, ptr addrspace(1) %out202 ret void203}204 205; OPT-LABEL: @sink_ubfe_i64_low32(206; OPT: entry:207; OPT-NOT: lshr208; OPT: br i1209 210; OPT: bb0:211; OPT: %0 = lshr i64 %arg1, 15212; OPT-NEXT: %val0 = and i64 %0, 255213 214; OPT: bb1:215; OPT: %1 = lshr i64 %arg1, 15216; OPT-NEXT: %val1 = and i64 %1, 127217 218; OPT: ret:219; OPT: store220; OPT: ret221 222; GCN-LABEL: {{^}}sink_ubfe_i64_low32:223 224; GCN: s_cbranch_scc{{[0-1]}} .LBB4_2225 226; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x7000f227 228; GCN: .LBB4_3:229; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x8000f230 231; GCN: buffer_store_dwordx2232define amdgpu_kernel void @sink_ubfe_i64_low32(ptr addrspace(1) %out, i64 %arg1, i1 %arg) #0 {233entry:234 %shr = lshr i64 %arg1, 15235 br i1 %arg, label %bb0, label %bb1236 237bb0:238 %val0 = and i64 %shr, 255239 store volatile i32 0, ptr addrspace(1) poison240 br label %ret241 242bb1:243 %val1 = and i64 %shr, 127244 store volatile i32 0, ptr addrspace(1) poison245 br label %ret246 247ret:248 %phi = phi i64 [ %val0, %bb0 ], [ %val1, %bb1 ]249 store i64 %phi, ptr addrspace(1) %out250 ret void251}252 253; OPT-LABEL: @sink_ubfe_i64_high32(254; OPT: entry:255; OPT-NOT: lshr256; OPT: br i1257 258; OPT: bb0:259; OPT: %0 = lshr i64 %arg1, 35260; OPT-NEXT: %val0 = and i64 %0, 255261 262; OPT: bb1:263; OPT: %1 = lshr i64 %arg1, 35264; OPT-NEXT: %val1 = and i64 %1, 127265 266; OPT: ret:267; OPT: store268; OPT: ret269 270; GCN-LABEL: {{^}}sink_ubfe_i64_high32:271; GCN: s_cbranch_scc{{[0-1]}} .LBB5_2272; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x70003273 274; GCN: .LBB5_3:275; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80003276 277; GCN: buffer_store_dwordx2278define amdgpu_kernel void @sink_ubfe_i64_high32(ptr addrspace(1) %out, i64 %arg1, i1 %arg) #0 {279entry:280 %shr = lshr i64 %arg1, 35281 br i1 %arg, label %bb0, label %bb1282 283bb0:284 %val0 = and i64 %shr, 255285 store volatile i32 0, ptr addrspace(1) poison286 br label %ret287 288bb1:289 %val1 = and i64 %shr, 127290 store volatile i32 0, ptr addrspace(1) poison291 br label %ret292 293ret:294 %phi = phi i64 [ %val0, %bb0 ], [ %val1, %bb1 ]295 store i64 %phi, ptr addrspace(1) %out296 ret void297}298 299attributes #0 = { nounwind }300