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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-xnack -debug-only=machine-scheduler < %s 2> %t | FileCheck --enable-var-scope --check-prefix=GFX9 %s3; RUN: FileCheck --enable-var-scope --check-prefix=DBG %s < %t4; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -debug-only=machine-scheduler < %s 2> %t | FileCheck --enable-var-scope --check-prefix=GFX10 %s5; RUN: FileCheck --enable-var-scope --check-prefix=DBG %s < %t6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -debug-only=machine-scheduler < %s 2> %t | FileCheck --enable-var-scope --check-prefix=GFX11 %s7; RUN: FileCheck --enable-var-scope --check-prefixes=DBG,DBG11 %s < %t8; REQUIRES: asserts9 10; FIXME: Verifier error with xnack enabled.11 12; DBG-LABEL: cluster_load_cluster_store:13 14; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(16)15; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(4)16; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(4)17; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(4)18; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(4)19 20; DBG: Cluster ld/st SU([[L1:[0-9]+]]) - SU([[L2:[0-9]+]])21; DBG: Cluster ld/st SU([[L2]]) - SU([[L3:[0-9]+]])22; DBG: Cluster ld/st SU([[L3]]) - SU([[L4:[0-9]+]])23 24; DBG11: Cluster ld/st SU([[S1:[0-9]+]]) - SU([[S2:[0-9]+]])25; DBG11: Cluster ld/st SU([[S2]]) - SU([[S3:[0-9]+]])26; DBG11: Cluster ld/st SU([[S3]]) - SU([[S4:[0-9]+]])27 28; DBG-NOT: Cluster ld/st29 30define amdgpu_kernel void @cluster_load_cluster_store(ptr noalias %lb, ptr noalias %sb) {31; GFX9-LABEL: cluster_load_cluster_store:32; GFX9: ; %bb.0: ; %bb33; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2434; GFX9-NEXT: s_waitcnt lgkmcnt(0)35; GFX9-NEXT: v_mov_b32_e32 v0, s036; GFX9-NEXT: v_mov_b32_e32 v1, s137; GFX9-NEXT: flat_load_dword v2, v[0:1]38; GFX9-NEXT: flat_load_dword v3, v[0:1] offset:839; GFX9-NEXT: flat_load_dword v4, v[0:1] offset:1640; GFX9-NEXT: flat_load_dword v5, v[0:1] offset:2441; GFX9-NEXT: v_mov_b32_e32 v0, s242; GFX9-NEXT: v_mov_b32_e32 v1, s343; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)44; GFX9-NEXT: flat_store_dword v[0:1], v245; GFX9-NEXT: flat_store_dword v[0:1], v3 offset:846; GFX9-NEXT: flat_store_dword v[0:1], v4 offset:1647; GFX9-NEXT: flat_store_dword v[0:1], v5 offset:2448; GFX9-NEXT: s_endpgm49;50; GFX10-LABEL: cluster_load_cluster_store:51; GFX10: ; %bb.0: ; %bb52; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2453; GFX10-NEXT: s_waitcnt lgkmcnt(0)54; GFX10-NEXT: s_add_u32 s4, s0, 855; GFX10-NEXT: s_addc_u32 s5, s1, 056; GFX10-NEXT: s_add_u32 s6, s0, 1657; GFX10-NEXT: v_mov_b32_e32 v0, s058; GFX10-NEXT: s_addc_u32 s7, s1, 059; GFX10-NEXT: v_mov_b32_e32 v1, s160; GFX10-NEXT: s_add_u32 s0, s0, 2461; GFX10-NEXT: v_mov_b32_e32 v2, s462; GFX10-NEXT: s_addc_u32 s1, s1, 063; GFX10-NEXT: v_mov_b32_e32 v3, s564; GFX10-NEXT: v_mov_b32_e32 v4, s665; GFX10-NEXT: v_mov_b32_e32 v5, s766; GFX10-NEXT: v_mov_b32_e32 v7, s167; GFX10-NEXT: v_mov_b32_e32 v6, s068; GFX10-NEXT: s_clause 0x369; GFX10-NEXT: flat_load_dword v8, v[0:1]70; GFX10-NEXT: flat_load_dword v9, v[2:3]71; GFX10-NEXT: flat_load_dword v10, v[4:5]72; GFX10-NEXT: flat_load_dword v11, v[6:7]73; GFX10-NEXT: s_add_u32 s0, s2, 874; GFX10-NEXT: s_addc_u32 s1, s3, 075; GFX10-NEXT: v_mov_b32_e32 v0, s276; GFX10-NEXT: v_mov_b32_e32 v3, s177; GFX10-NEXT: v_mov_b32_e32 v2, s078; GFX10-NEXT: s_add_u32 s0, s2, 1679; GFX10-NEXT: s_addc_u32 s1, s3, 080; GFX10-NEXT: v_mov_b32_e32 v1, s381; GFX10-NEXT: s_add_u32 s2, s2, 2482; GFX10-NEXT: s_addc_u32 s3, s3, 083; GFX10-NEXT: v_mov_b32_e32 v5, s184; GFX10-NEXT: v_mov_b32_e32 v4, s085; GFX10-NEXT: v_mov_b32_e32 v7, s386; GFX10-NEXT: v_mov_b32_e32 v6, s287; GFX10-NEXT: s_waitcnt vmcnt(3) lgkmcnt(3)88; GFX10-NEXT: flat_store_dword v[0:1], v889; GFX10-NEXT: s_waitcnt vmcnt(2) lgkmcnt(3)90; GFX10-NEXT: flat_store_dword v[2:3], v991; GFX10-NEXT: s_waitcnt vmcnt(1) lgkmcnt(3)92; GFX10-NEXT: flat_store_dword v[4:5], v1093; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(3)94; GFX10-NEXT: flat_store_dword v[6:7], v1195; GFX10-NEXT: s_endpgm96;97; GFX11-LABEL: cluster_load_cluster_store:98; GFX11: ; %bb.0: ; %bb99; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24100; GFX11-NEXT: s_waitcnt lgkmcnt(0)101; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1102; GFX11-NEXT: s_clause 0x3103; GFX11-NEXT: flat_load_b32 v2, v[0:1]104; GFX11-NEXT: flat_load_b32 v3, v[0:1] offset:8105; GFX11-NEXT: flat_load_b32 v4, v[0:1] offset:16106; GFX11-NEXT: flat_load_b32 v5, v[0:1] offset:24107; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3108; GFX11-NEXT: s_waitcnt vmcnt(3) lgkmcnt(3)109; GFX11-NEXT: flat_store_b32 v[0:1], v2110; GFX11-NEXT: s_waitcnt vmcnt(2) lgkmcnt(3)111; GFX11-NEXT: flat_store_b32 v[0:1], v3 offset:8112; GFX11-NEXT: s_waitcnt vmcnt(1) lgkmcnt(3)113; GFX11-NEXT: flat_store_b32 v[0:1], v4 offset:16114; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(3)115; GFX11-NEXT: flat_store_b32 v[0:1], v5 offset:24116; GFX11-NEXT: s_endpgm117bb:118 %ld0 = load i32, ptr %lb119 %la1 = getelementptr inbounds i32, ptr %lb, i32 2120 %ld1 = load i32, ptr %la1121 %la2 = getelementptr inbounds i32, ptr %lb, i32 4122 %ld2 = load i32, ptr %la2123 %la3 = getelementptr inbounds i32, ptr %lb, i32 6124 %ld3 = load i32, ptr %la3125 126 store i32 %ld0, ptr %sb127 %sa1 = getelementptr inbounds i32, ptr %sb, i32 2128 store i32 %ld1, ptr %sa1129 %sa2 = getelementptr inbounds i32, ptr %sb, i32 4130 store i32 %ld2, ptr %sa2131 %sa3 = getelementptr inbounds i32, ptr %sb, i32 6132 store i32 %ld3, ptr %sa3133 134 ret void135}136 137; DBG-LABEL: cluster_load_valu_cluster_store:138 139; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(16)140; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(4)141; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(4)142; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(4)143; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(4)144 145; DBG: Cluster ld/st SU([[L1:[0-9]+]]) - SU([[L2:[0-9]+]])146; DBG: Cluster ld/st SU([[L2]]) - SU([[L3:[0-9]+]])147; DBG: Cluster ld/st SU([[L3]]) - SU([[L4:[0-9]+]])148 149; DBG11: Cluster ld/st SU([[S1:[0-9]+]]) - SU([[S2:[0-9]+]])150; DBG11: Cluster ld/st SU([[S2]]) - SU([[S3:[0-9]+]])151; DBG11: Cluster ld/st SU([[S3]]) - SU([[S4:[0-9]+]])152 153; DBG-NOT: Cluster ld/st154 155define amdgpu_kernel void @cluster_load_valu_cluster_store(ptr noalias %lb, ptr noalias %sb) {156; GFX9-LABEL: cluster_load_valu_cluster_store:157; GFX9: ; %bb.0: ; %bb158; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24159; GFX9-NEXT: s_waitcnt lgkmcnt(0)160; GFX9-NEXT: v_mov_b32_e32 v0, s0161; GFX9-NEXT: v_mov_b32_e32 v1, s1162; GFX9-NEXT: flat_load_dword v2, v[0:1]163; GFX9-NEXT: flat_load_dword v3, v[0:1] offset:8164; GFX9-NEXT: flat_load_dword v4, v[0:1] offset:16165; GFX9-NEXT: flat_load_dword v5, v[0:1] offset:24166; GFX9-NEXT: v_mov_b32_e32 v0, s2167; GFX9-NEXT: v_mov_b32_e32 v1, s3168; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)169; GFX9-NEXT: flat_store_dword v[0:1], v2170; GFX9-NEXT: v_add_u32_e32 v2, 1, v3171; GFX9-NEXT: flat_store_dword v[0:1], v4 offset:16172; GFX9-NEXT: flat_store_dword v[0:1], v2 offset:8173; GFX9-NEXT: flat_store_dword v[0:1], v5 offset:24174; GFX9-NEXT: s_endpgm175;176; GFX10-LABEL: cluster_load_valu_cluster_store:177; GFX10: ; %bb.0: ; %bb178; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24179; GFX10-NEXT: s_waitcnt lgkmcnt(0)180; GFX10-NEXT: s_add_u32 s4, s0, 8181; GFX10-NEXT: s_addc_u32 s5, s1, 0182; GFX10-NEXT: v_mov_b32_e32 v2, s4183; GFX10-NEXT: s_add_u32 s6, s0, 16184; GFX10-NEXT: v_mov_b32_e32 v3, s5185; GFX10-NEXT: v_mov_b32_e32 v0, s0186; GFX10-NEXT: s_addc_u32 s7, s1, 0187; GFX10-NEXT: v_mov_b32_e32 v1, s1188; GFX10-NEXT: s_add_u32 s0, s0, 24189; GFX10-NEXT: s_addc_u32 s1, s1, 0190; GFX10-NEXT: v_mov_b32_e32 v4, s6191; GFX10-NEXT: v_mov_b32_e32 v5, s7192; GFX10-NEXT: flat_load_dword v6, v[2:3]193; GFX10-NEXT: v_mov_b32_e32 v3, s1194; GFX10-NEXT: v_mov_b32_e32 v2, s0195; GFX10-NEXT: s_clause 0x2196; GFX10-NEXT: flat_load_dword v8, v[0:1]197; GFX10-NEXT: flat_load_dword v9, v[4:5]198; GFX10-NEXT: flat_load_dword v10, v[2:3]199; GFX10-NEXT: s_add_u32 s0, s2, 8200; GFX10-NEXT: s_addc_u32 s1, s3, 0201; GFX10-NEXT: s_add_u32 s4, s2, 16202; GFX10-NEXT: v_mov_b32_e32 v3, s1203; GFX10-NEXT: s_addc_u32 s5, s3, 0204; GFX10-NEXT: v_mov_b32_e32 v0, s2205; GFX10-NEXT: v_mov_b32_e32 v2, s0206; GFX10-NEXT: s_add_u32 s0, s2, 24207; GFX10-NEXT: v_mov_b32_e32 v1, s3208; GFX10-NEXT: v_mov_b32_e32 v4, s4209; GFX10-NEXT: s_addc_u32 s1, s3, 0210; GFX10-NEXT: v_mov_b32_e32 v5, s5211; GFX10-NEXT: s_waitcnt vmcnt(3) lgkmcnt(3)212; GFX10-NEXT: v_add_nc_u32_e32 v11, 1, v6213; GFX10-NEXT: v_mov_b32_e32 v7, s1214; GFX10-NEXT: v_mov_b32_e32 v6, s0215; GFX10-NEXT: s_waitcnt vmcnt(2) lgkmcnt(2)216; GFX10-NEXT: flat_store_dword v[0:1], v8217; GFX10-NEXT: s_waitcnt vmcnt(1) lgkmcnt(2)218; GFX10-NEXT: flat_store_dword v[4:5], v9219; GFX10-NEXT: flat_store_dword v[2:3], v11220; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(3)221; GFX10-NEXT: flat_store_dword v[6:7], v10222; GFX10-NEXT: s_endpgm223;224; GFX11-LABEL: cluster_load_valu_cluster_store:225; GFX11: ; %bb.0: ; %bb226; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24227; GFX11-NEXT: s_waitcnt lgkmcnt(0)228; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1229; GFX11-NEXT: s_clause 0x3230; GFX11-NEXT: flat_load_b32 v2, v[0:1] offset:8231; GFX11-NEXT: flat_load_b32 v3, v[0:1]232; GFX11-NEXT: flat_load_b32 v4, v[0:1] offset:16233; GFX11-NEXT: flat_load_b32 v5, v[0:1] offset:24234; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3235; GFX11-NEXT: s_waitcnt vmcnt(3) lgkmcnt(3)236; GFX11-NEXT: v_add_nc_u32_e32 v2, 1, v2237; GFX11-NEXT: s_waitcnt vmcnt(2) lgkmcnt(2)238; GFX11-NEXT: s_clause 0x1239; GFX11-NEXT: flat_store_b32 v[0:1], v3240; GFX11-NEXT: flat_store_b32 v[0:1], v2 offset:8241; GFX11-NEXT: s_waitcnt vmcnt(1) lgkmcnt(3)242; GFX11-NEXT: flat_store_b32 v[0:1], v4 offset:16243; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(3)244; GFX11-NEXT: flat_store_b32 v[0:1], v5 offset:24245; GFX11-NEXT: s_endpgm246bb:247 %ld0 = load i32, ptr %lb248 %la1 = getelementptr inbounds i32, ptr %lb, i32 2249 %ld1 = load i32, ptr %la1250 %la2 = getelementptr inbounds i32, ptr %lb, i32 4251 %ld2 = load i32, ptr %la2252 %la3 = getelementptr inbounds i32, ptr %lb, i32 6253 %ld3 = load i32, ptr %la3254 255 store i32 %ld0, ptr %sb256 %sa1 = getelementptr inbounds i32, ptr %sb, i32 2257 %add = add i32 %ld1, 1258 store i32 %add, ptr %sa1259 %sa2 = getelementptr inbounds i32, ptr %sb, i32 4260 store i32 %ld2, ptr %sa2261 %sa3 = getelementptr inbounds i32, ptr %sb, i32 6262 store i32 %ld3, ptr %sa3263 264 ret void265}266 267; Cluster loads from the same texture with different coordinates268; DBG-LABEL: cluster_image_load:269; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(16)270; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(16)271; DBG: {{^}}Cluster ld/st [[SU1:SU\([0-9]+\)]] - [[SU2:SU\([0-9]+\)]]272; DBG: {{^}}[[SU1]]: {{.*}} IMAGE_LOAD273; DBG: {{^}}[[SU2]]: {{.*}} IMAGE_LOAD274define amdgpu_ps void @cluster_image_load(<8 x i32> inreg %src, <8 x i32> inreg %dst, i32 %x, i32 %y) {275; GFX9-LABEL: cluster_image_load:276; GFX9: ; %bb.0: ; %entry277; GFX9-NEXT: v_add_u32_e32 v2, 1, v0278; GFX9-NEXT: v_add_u32_e32 v3, 1, v1279; GFX9-NEXT: v_add_u32_e32 v6, 2, v0280; GFX9-NEXT: v_add_u32_e32 v7, 2, v1281; GFX9-NEXT: image_load v[2:5], v[2:3], s[0:7] dmask:0xf unorm282; GFX9-NEXT: image_load v[6:9], v[6:7], s[0:7] dmask:0xf unorm283; GFX9-NEXT: s_waitcnt vmcnt(0)284; GFX9-NEXT: v_add_f32_e32 v5, v5, v9285; GFX9-NEXT: v_add_f32_e32 v4, v4, v8286; GFX9-NEXT: v_add_f32_e32 v3, v3, v7287; GFX9-NEXT: v_add_f32_e32 v2, v2, v6288; GFX9-NEXT: image_store v[2:5], v[0:1], s[8:15] dmask:0xf unorm289; GFX9-NEXT: s_endpgm290;291; GFX10-LABEL: cluster_image_load:292; GFX10: ; %bb.0: ; %entry293; GFX10-NEXT: v_add_nc_u32_e32 v10, 1, v0294; GFX10-NEXT: v_add_nc_u32_e32 v11, 1, v1295; GFX10-NEXT: v_add_nc_u32_e32 v12, 2, v0296; GFX10-NEXT: v_add_nc_u32_e32 v13, 2, v1297; GFX10-NEXT: s_clause 0x1298; GFX10-NEXT: image_load v[2:5], v[10:11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm299; GFX10-NEXT: image_load v[6:9], v[12:13], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm300; GFX10-NEXT: s_waitcnt vmcnt(0)301; GFX10-NEXT: v_add_f32_e32 v5, v5, v9302; GFX10-NEXT: v_add_f32_e32 v4, v4, v8303; GFX10-NEXT: v_add_f32_e32 v3, v3, v7304; GFX10-NEXT: v_add_f32_e32 v2, v2, v6305; GFX10-NEXT: image_store v[2:5], v[0:1], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm306; GFX10-NEXT: s_endpgm307;308; GFX11-LABEL: cluster_image_load:309; GFX11: ; %bb.0: ; %entry310; GFX11-NEXT: v_add_nc_u32_e32 v2, 1, v0311; GFX11-NEXT: v_add_nc_u32_e32 v3, 1, v1312; GFX11-NEXT: v_add_nc_u32_e32 v6, 2, v0313; GFX11-NEXT: v_add_nc_u32_e32 v7, 2, v1314; GFX11-NEXT: s_clause 0x1315; GFX11-NEXT: image_load v[2:5], v[2:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm316; GFX11-NEXT: image_load v[6:9], v[6:7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm317; GFX11-NEXT: s_waitcnt vmcnt(0)318; GFX11-NEXT: v_dual_add_f32 v5, v5, v9 :: v_dual_add_f32 v4, v4, v8319; GFX11-NEXT: v_dual_add_f32 v3, v3, v7 :: v_dual_add_f32 v2, v2, v6320; GFX11-NEXT: image_store v[2:5], v[0:1], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm321; GFX11-NEXT: s_endpgm322entry:323 %x1 = add i32 %x, 1324 %y1 = add i32 %y, 1325 %val1 = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %x1, i32 %y1, <8 x i32> %src, i32 0, i32 0)326 %x2 = add i32 %x, 2327 %y2 = add i32 %y, 2328 %val2 = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %x2, i32 %y2, <8 x i32> %src, i32 0, i32 0)329 %val = fadd fast <4 x float> %val1, %val2330 call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)331 ret void332}333 334; Don't cluster loads from different textures335; DBG-LABEL: no_cluster_image_load:336; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(16)337; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(16)338; DBG-NOT: {{^}}Cluster ld/st339define amdgpu_ps void @no_cluster_image_load(<8 x i32> inreg %src1, <8 x i32> inreg %src2, <8 x i32> inreg %dst, i32 %x, i32 %y) {340; GFX9-LABEL: no_cluster_image_load:341; GFX9: ; %bb.0: ; %entry342; GFX9-NEXT: v_mov_b32_e32 v2, 0343; GFX9-NEXT: image_load_mip v[3:6], v[0:2], s[0:7] dmask:0xf unorm344; GFX9-NEXT: image_load_mip v[7:10], v[0:2], s[8:15] dmask:0xf unorm345; GFX9-NEXT: s_waitcnt vmcnt(0)346; GFX9-NEXT: v_add_f32_e32 v6, v6, v10347; GFX9-NEXT: v_add_f32_e32 v5, v5, v9348; GFX9-NEXT: v_add_f32_e32 v4, v4, v8349; GFX9-NEXT: v_add_f32_e32 v3, v3, v7350; GFX9-NEXT: image_store v[3:6], v[0:1], s[16:23] dmask:0xf unorm351; GFX9-NEXT: s_endpgm352;353; GFX10-LABEL: no_cluster_image_load:354; GFX10: ; %bb.0: ; %entry355; GFX10-NEXT: v_mov_b32_e32 v10, 0356; GFX10-NEXT: image_load_mip v[2:5], [v0, v1, v10], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm357; GFX10-NEXT: image_load_mip v[6:9], [v0, v1, v10], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm358; GFX10-NEXT: s_waitcnt vmcnt(0)359; GFX10-NEXT: v_add_f32_e32 v5, v5, v9360; GFX10-NEXT: v_add_f32_e32 v4, v4, v8361; GFX10-NEXT: v_add_f32_e32 v3, v3, v7362; GFX10-NEXT: v_add_f32_e32 v2, v2, v6363; GFX10-NEXT: image_store v[2:5], v[0:1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D unorm364; GFX10-NEXT: s_endpgm365;366; GFX11-LABEL: no_cluster_image_load:367; GFX11: ; %bb.0: ; %entry368; GFX11-NEXT: v_mov_b32_e32 v6, 0369; GFX11-NEXT: image_load_mip v[2:5], [v0, v1, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm370; GFX11-NEXT: image_load_mip v[6:9], [v0, v1, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm371; GFX11-NEXT: s_waitcnt vmcnt(0)372; GFX11-NEXT: v_dual_add_f32 v5, v5, v9 :: v_dual_add_f32 v4, v4, v8373; GFX11-NEXT: v_dual_add_f32 v3, v3, v7 :: v_dual_add_f32 v2, v2, v6374; GFX11-NEXT: image_store v[2:5], v[0:1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D unorm375; GFX11-NEXT: s_endpgm376entry:377 %val1 = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %x, i32 %y, i32 0, <8 x i32> %src1, i32 0, i32 0)378 %val2 = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %x, i32 %y, i32 0, <8 x i32> %src2, i32 0, i32 0)379 %val = fadd fast <4 x float> %val1, %val2380 call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)381 ret void382}383 384; Cluster loads from the same texture and sampler with different coordinates385; DBG-LABEL: cluster_image_sample:386; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(16)387; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: LocationSize::precise(16)388; DBG: {{^}}Cluster ld/st [[SU1:SU\([0-9]+\)]] - [[SU2:SU\([0-9]+\)]]389; DBG: {{^}}[[SU1]]: {{.*}} IMAGE_SAMPLE390; DBG: {{^}}[[SU2]]: {{.*}} IMAGE_SAMPLE391define amdgpu_ps void @cluster_image_sample(<8 x i32> inreg %src, <4 x i32> inreg %smp, <8 x i32> inreg %dst, i32 %x, i32 %y) {392; GFX9-LABEL: cluster_image_sample:393; GFX9: ; %bb.0: ; %entry394; GFX9-NEXT: v_cvt_f32_i32_e32 v2, v0395; GFX9-NEXT: v_cvt_f32_i32_e32 v3, v1396; GFX9-NEXT: v_mov_b32_e32 v4, 1.0397; GFX9-NEXT: v_mov_b32_e32 v10, 0398; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v2399; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v3400; GFX9-NEXT: v_mov_b32_e32 v11, v10401; GFX9-NEXT: v_mov_b32_e32 v12, v10402; GFX9-NEXT: v_mov_b32_e32 v13, v10403; GFX9-NEXT: v_add_f32_e32 v2, 2.0, v2404; GFX9-NEXT: v_add_f32_e32 v3, 2.0, v3405; GFX9-NEXT: v_mov_b32_e32 v5, v4406; GFX9-NEXT: v_mov_b32_e32 v6, v4407; GFX9-NEXT: v_mov_b32_e32 v7, v4408; GFX9-NEXT: image_sample_d v[8:11], v[8:13], s[0:7], s[8:11] dmask:0xf409; GFX9-NEXT: image_sample_d v[2:5], v[2:7], s[0:7], s[8:11] dmask:0xf410; GFX9-NEXT: s_waitcnt vmcnt(0)411; GFX9-NEXT: v_add_f32_e32 v5, v11, v5412; GFX9-NEXT: v_add_f32_e32 v4, v10, v4413; GFX9-NEXT: v_add_f32_e32 v3, v9, v3414; GFX9-NEXT: v_add_f32_e32 v2, v8, v2415; GFX9-NEXT: image_store v[2:5], v[0:1], s[12:19] dmask:0xf unorm416; GFX9-NEXT: s_endpgm417;418; GFX10-LABEL: cluster_image_sample:419; GFX10: ; %bb.0: ; %entry420; GFX10-NEXT: v_cvt_f32_i32_e32 v8, v0421; GFX10-NEXT: v_cvt_f32_i32_e32 v9, v1422; GFX10-NEXT: v_mov_b32_e32 v4, 0423; GFX10-NEXT: v_mov_b32_e32 v10, 1.0424; GFX10-NEXT: v_add_f32_e32 v2, 1.0, v8425; GFX10-NEXT: v_add_f32_e32 v3, 1.0, v9426; GFX10-NEXT: v_mov_b32_e32 v5, v4427; GFX10-NEXT: v_mov_b32_e32 v6, v4428; GFX10-NEXT: v_mov_b32_e32 v7, v4429; GFX10-NEXT: v_add_f32_e32 v8, 2.0, v8430; GFX10-NEXT: v_add_f32_e32 v9, 2.0, v9431; GFX10-NEXT: v_mov_b32_e32 v11, v10432; GFX10-NEXT: v_mov_b32_e32 v12, v10433; GFX10-NEXT: v_mov_b32_e32 v13, v10434; GFX10-NEXT: s_clause 0x1435; GFX10-NEXT: image_sample_d v[14:17], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D436; GFX10-NEXT: image_sample_d v[18:21], v[8:13], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D437; GFX10-NEXT: s_waitcnt vmcnt(0)438; GFX10-NEXT: v_add_f32_e32 v5, v17, v21439; GFX10-NEXT: v_add_f32_e32 v4, v16, v20440; GFX10-NEXT: v_add_f32_e32 v3, v15, v19441; GFX10-NEXT: v_add_f32_e32 v2, v14, v18442; GFX10-NEXT: image_store v[2:5], v[0:1], s[12:19] dmask:0xf dim:SQ_RSRC_IMG_2D unorm443; GFX10-NEXT: s_endpgm444;445; GFX11-LABEL: cluster_image_sample:446; GFX11: ; %bb.0: ; %entry447; GFX11-NEXT: v_cvt_f32_i32_e32 v4, v0448; GFX11-NEXT: v_cvt_f32_i32_e32 v5, v1449; GFX11-NEXT: v_mov_b32_e32 v2, 0450; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)451; GFX11-NEXT: v_dual_mov_b32 v6, 1.0 :: v_dual_add_f32 v11, 2.0, v5452; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v5 :: v_dual_add_f32 v8, 1.0, v4453; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)454; GFX11-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_add_f32 v10, 2.0, v4455; GFX11-NEXT: v_mov_b32_e32 v7, v6456; GFX11-NEXT: s_clause 0x1457; GFX11-NEXT: image_sample_d v[2:5], [v8, v9, v2, v2, v[2:3]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D458; GFX11-NEXT: image_sample_d v[6:9], [v10, v11, v6, v6, v[6:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D459; GFX11-NEXT: s_waitcnt vmcnt(0)460; GFX11-NEXT: v_dual_add_f32 v5, v5, v9 :: v_dual_add_f32 v4, v4, v8461; GFX11-NEXT: v_dual_add_f32 v3, v3, v7 :: v_dual_add_f32 v2, v2, v6462; GFX11-NEXT: image_store v[2:5], v[0:1], s[12:19] dmask:0xf dim:SQ_RSRC_IMG_2D unorm463; GFX11-NEXT: s_endpgm464entry:465 %s = sitofp i32 %x to float466 %t = sitofp i32 %y to float467 %s1 = fadd float %s, 1.0468 %t1 = fadd float %t, 1.0469 %val1 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32 15, float %s1, float %t1, float 0.0, float 0.0, float 0.0, float 0.0, <8 x i32> %src, <4 x i32> %smp, i1 false, i32 0, i32 0)470 %s2 = fadd float %s, 2.0471 %t2 = fadd float %t, 2.0472 %val2 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32 15, float %s2, float %t2, float 1.0, float 1.0, float 1.0, float 1.0, <8 x i32> %src, <4 x i32> %smp, i1 false, i32 0, i32 0)473 %val = fadd fast <4 x float> %val1, %val2474 call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)475 ret void476}477 478declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg)479declare <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg)480declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32)481declare void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg)482