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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 62# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=register-coalescer -o - %s | FileCheck %s3 4# The register budget for this function does not permit using 1024-bit5# registers. The coalescer should not introduce a 1024-bit virtual6# register which will fail to allocate.7 8--- |9 define void @no_introduce_vreg_1024() #0 {10 ret void11 }12 13 attributes #0 = { "amdgpu-waves-per-eu"="10,10" }14...15---16name: no_introduce_vreg_102417tracksRegLiveness: true18machineFunctionInfo:19 occupancy: 1020body: |21 bb.0:22 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr723 24 ; CHECK-LABEL: name: no_introduce_vreg_102425 ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr726 ; CHECK-NEXT: {{ $}}27 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr728 ; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub9:vreg_512 = COPY [[COPY]].sub029 ; CHECK-NEXT: SI_RETURN implicit [[COPY1]]30 %0:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr731 undef %1.sub9:vreg_512 = COPY %0.sub032 SI_RETURN implicit %133 34...35