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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=gfx803 -run-pass register-coalescer -verify-machineinstrs -o - %s | FileCheck %s3 4# Register coalescer is going to eliminate %2:sgpr_32 = COPY %1.sub0 from bb.15# by joining %2 and %1.sub0 into %0.sub0 register. Check that when this happen6# the implicit intialization of %0.sub0 in the bb.2 have undef flag7# for the MIR to be valid.8 9---10name: coalescing_makes_lane_undefined11tracksRegLiveness: true12body: |13 ; CHECK-LABEL: name: coalescing_makes_lane_undefined14 ; CHECK: bb.0:15 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)16 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit undef $scc18 ; CHECK-NEXT: {{ $}}19 ; CHECK-NEXT: bb.1:20 ; CHECK-NEXT: successors: %bb.3(0x80000000)21 ; CHECK-NEXT: {{ $}}22 ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 123 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 224 ; CHECK-NEXT: S_BRANCH %bb.325 ; CHECK-NEXT: {{ $}}26 ; CHECK-NEXT: bb.2:27 ; CHECK-NEXT: successors: %bb.3(0x80000000)28 ; CHECK-NEXT: {{ $}}29 ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = IMPLICIT_DEF30 ; CHECK-NEXT: {{ $}}31 ; CHECK-NEXT: bb.3:32 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]].sub033 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]34 bb.0:35 successors: %bb.1, %bb.236 S_CBRANCH_SCC0 %bb.2, implicit undef $scc37 38 bb.1:39 successors: %bb.340 undef %1.sub0:sgpr_64 = S_MOV_B32 141 %1.sub1:sgpr_64 = S_MOV_B32 242 %2:sgpr_32 = COPY %1.sub0 ; copy to be joined43 S_BRANCH %bb.344 45 bb.2:46 successors: %bb.347 %2:sgpr_32 = IMPLICIT_DEF48 undef %1.sub0:sgpr_64 = IMPLICIT_DEF49 %1.sub1:sgpr_64 = IMPLICIT_DEF50 51 bb.3:52 S_NOP 0, implicit killed %253 S_NOP 0, implicit killed %154 55...56