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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX1010 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck --check-prefix=GFX1100 %s4 5; Test that unused lanes in the s_xor result are masked out with v_cndmask.6 7define i32 @combine_add_zext_xor(i32 inreg %cond) {8; GFX1010-LABEL: combine_add_zext_xor:9; GFX1010: ; %bb.0: ; %.entry10; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11; GFX1010-NEXT: s_cmp_lg_u32 s16, 012; GFX1010-NEXT: v_mov_b32_e32 v1, 013; GFX1010-NEXT: s_cselect_b32 s4, -1, 014; GFX1010-NEXT: v_cndmask_b32_e64 v0, 0, 1, s415; GFX1010-NEXT: v_cmp_ne_u32_e64 s4, 1, v016; GFX1010-NEXT: s_branch .LBB0_217; GFX1010-NEXT: .LBB0_1: ; %bb918; GFX1010-NEXT: ; in Loop: Header=BB0_2 Depth=119; GFX1010-NEXT: s_xor_b32 s5, s5, -120; GFX1010-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfffffbe6, v121; GFX1010-NEXT: v_cndmask_b32_e64 v0, 0, 1, s522; GFX1010-NEXT: v_add_nc_u32_e32 v2, v1, v023; GFX1010-NEXT: v_mov_b32_e32 v1, v224; GFX1010-NEXT: s_cbranch_vccz .LBB0_425; GFX1010-NEXT: .LBB0_2: ; %.a26; GFX1010-NEXT: ; =>This Inner Loop Header: Depth=127; GFX1010-NEXT: s_and_b32 vcc_lo, exec_lo, s428; GFX1010-NEXT: ; implicit-def: $sgpr529; GFX1010-NEXT: s_cbranch_vccnz .LBB0_130; GFX1010-NEXT: ; %bb.3: ; %bb31; GFX1010-NEXT: ; in Loop: Header=BB0_2 Depth=132; GFX1010-NEXT: buffer_load_dword v0, v1, s[4:7], 64 offen glc33; GFX1010-NEXT: s_waitcnt vmcnt(0)34; GFX1010-NEXT: v_cmp_eq_u32_e64 s5, 0, v035; GFX1010-NEXT: s_branch .LBB0_136; GFX1010-NEXT: .LBB0_4: ; %.exit37; GFX1010-NEXT: s_setpc_b64 s[30:31]38;39; GFX1100-LABEL: combine_add_zext_xor:40; GFX1100: ; %bb.0: ; %.entry41; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)42; GFX1100-NEXT: s_cmp_lg_u32 s0, 043; GFX1100-NEXT: v_mov_b32_e32 v1, 044; GFX1100-NEXT: s_cselect_b32 s0, -1, 045; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)46; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 1, s047; GFX1100-NEXT: v_cmp_ne_u32_e64 s0, 1, v048; GFX1100-NEXT: s_branch .LBB0_249; GFX1100-NEXT: .LBB0_1: ; %bb950; GFX1100-NEXT: ; in Loop: Header=BB0_2 Depth=151; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)52; GFX1100-NEXT: s_xor_b32 s1, s1, -153; GFX1100-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfffffbe6, v154; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 1, s155; GFX1100-NEXT: v_add_nc_u32_e32 v2, v1, v056; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)57; GFX1100-NEXT: v_mov_b32_e32 v1, v258; GFX1100-NEXT: s_cbranch_vccz .LBB0_459; GFX1100-NEXT: .LBB0_2: ; %.a60; GFX1100-NEXT: ; =>This Inner Loop Header: Depth=161; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)62; GFX1100-NEXT: s_and_b32 vcc_lo, exec_lo, s063; GFX1100-NEXT: ; implicit-def: $sgpr164; GFX1100-NEXT: s_cbranch_vccnz .LBB0_165; GFX1100-NEXT: ; %bb.3: ; %bb66; GFX1100-NEXT: ; in Loop: Header=BB0_2 Depth=167; GFX1100-NEXT: buffer_load_b32 v0, v1, s[0:3], 64 offen glc68; GFX1100-NEXT: s_waitcnt vmcnt(0)69; GFX1100-NEXT: v_cmp_eq_u32_e64 s1, 0, v070; GFX1100-NEXT: s_branch .LBB0_171; GFX1100-NEXT: .LBB0_4: ; %.exit72; GFX1100-NEXT: s_setpc_b64 s[30:31]73.entry:74 br label %.a75 76.a: ; preds = %bb9, %.entry77 %.2 = phi i32 [ 0, %.entry ], [ %i11, %bb9 ]78 %cmp = icmp eq i32 %cond, 079 br i1 %cmp, label %bb9, label %bb80 81bb: ; preds = %.a82 %.i3 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) poison, i32 %.2, i32 64, i32 1)83 %i5 = icmp eq i32 %.i3, 084 br label %bb985 86bb9: ; preds = %bb, %.a87 %.2.0.in.in = phi i1 [ %i5, %bb ], [ poison, %.a ]88 %.2.0.in = xor i1 %.2.0.in.in, true89 %.2.0 = zext i1 %.2.0.in to i3290 %i11 = add i32 %.2, %.2.091 %i12 = icmp sgt i32 %.2, -105092 br i1 %i12, label %.a, label %.exit93 94.exit: ; preds = %bb995 ret i32 %.2.096}97 98; Test that unused lanes in the s_xor result are masked out with v_cndmask.99 100define i32 @combine_sub_zext_xor(i32 inreg %cond) {101; GFX1010-LABEL: combine_sub_zext_xor:102; GFX1010: ; %bb.0: ; %.entry103; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)104; GFX1010-NEXT: s_cmp_lg_u32 s16, 0105; GFX1010-NEXT: v_mov_b32_e32 v1, 0106; GFX1010-NEXT: s_cselect_b32 s4, -1, 0107; GFX1010-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4108; GFX1010-NEXT: v_cmp_ne_u32_e64 s4, 1, v0109; GFX1010-NEXT: s_branch .LBB1_2110; GFX1010-NEXT: .LBB1_1: ; %bb9111; GFX1010-NEXT: ; in Loop: Header=BB1_2 Depth=1112; GFX1010-NEXT: s_xor_b32 s5, s5, -1113; GFX1010-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfffffbe6, v1114; GFX1010-NEXT: v_cndmask_b32_e64 v0, 0, 1, s5115; GFX1010-NEXT: v_sub_nc_u32_e32 v2, v1, v0116; GFX1010-NEXT: v_mov_b32_e32 v1, v2117; GFX1010-NEXT: s_cbranch_vccz .LBB1_4118; GFX1010-NEXT: .LBB1_2: ; %.a119; GFX1010-NEXT: ; =>This Inner Loop Header: Depth=1120; GFX1010-NEXT: s_and_b32 vcc_lo, exec_lo, s4121; GFX1010-NEXT: ; implicit-def: $sgpr5122; GFX1010-NEXT: s_cbranch_vccnz .LBB1_1123; GFX1010-NEXT: ; %bb.3: ; %bb124; GFX1010-NEXT: ; in Loop: Header=BB1_2 Depth=1125; GFX1010-NEXT: buffer_load_dword v0, v1, s[4:7], 64 offen glc126; GFX1010-NEXT: s_waitcnt vmcnt(0)127; GFX1010-NEXT: v_cmp_eq_u32_e64 s5, 0, v0128; GFX1010-NEXT: s_branch .LBB1_1129; GFX1010-NEXT: .LBB1_4: ; %.exit130; GFX1010-NEXT: s_setpc_b64 s[30:31]131;132; GFX1100-LABEL: combine_sub_zext_xor:133; GFX1100: ; %bb.0: ; %.entry134; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)135; GFX1100-NEXT: s_cmp_lg_u32 s0, 0136; GFX1100-NEXT: v_mov_b32_e32 v1, 0137; GFX1100-NEXT: s_cselect_b32 s0, -1, 0138; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)139; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0140; GFX1100-NEXT: v_cmp_ne_u32_e64 s0, 1, v0141; GFX1100-NEXT: s_branch .LBB1_2142; GFX1100-NEXT: .LBB1_1: ; %bb9143; GFX1100-NEXT: ; in Loop: Header=BB1_2 Depth=1144; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)145; GFX1100-NEXT: s_xor_b32 s1, s1, -1146; GFX1100-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfffffbe6, v1147; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1148; GFX1100-NEXT: v_sub_nc_u32_e32 v2, v1, v0149; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)150; GFX1100-NEXT: v_mov_b32_e32 v1, v2151; GFX1100-NEXT: s_cbranch_vccz .LBB1_4152; GFX1100-NEXT: .LBB1_2: ; %.a153; GFX1100-NEXT: ; =>This Inner Loop Header: Depth=1154; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)155; GFX1100-NEXT: s_and_b32 vcc_lo, exec_lo, s0156; GFX1100-NEXT: ; implicit-def: $sgpr1157; GFX1100-NEXT: s_cbranch_vccnz .LBB1_1158; GFX1100-NEXT: ; %bb.3: ; %bb159; GFX1100-NEXT: ; in Loop: Header=BB1_2 Depth=1160; GFX1100-NEXT: buffer_load_b32 v0, v1, s[0:3], 64 offen glc161; GFX1100-NEXT: s_waitcnt vmcnt(0)162; GFX1100-NEXT: v_cmp_eq_u32_e64 s1, 0, v0163; GFX1100-NEXT: s_branch .LBB1_1164; GFX1100-NEXT: .LBB1_4: ; %.exit165; GFX1100-NEXT: s_setpc_b64 s[30:31]166.entry:167 br label %.a168 169.a: ; preds = %bb9, %.entry170 %.2 = phi i32 [ 0, %.entry ], [ %i11, %bb9 ]171 %cmp = icmp eq i32 %cond, 0172 br i1 %cmp, label %bb9, label %bb173 174bb: ; preds = %.a175 %.i3 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) poison, i32 %.2, i32 64, i32 1)176 %i5 = icmp eq i32 %.i3, 0177 br label %bb9178 179bb9: ; preds = %bb, %.a180 %.2.0.in.in = phi i1 [ %i5, %bb ], [ poison, %.a ]181 %.2.0.in = xor i1 %.2.0.in.in, true182 %.2.0 = zext i1 %.2.0.in to i32183 %i11 = sub i32 %.2, %.2.0184 %i12 = icmp sgt i32 %.2, -1050185 br i1 %i12, label %.a, label %.exit186 187.exit: ; preds = %bb9188 ret i32 %.2.0189}190 191; Test that unused lanes in the s_or result are masked out with v_cndmask.192 193define i32 @combine_add_zext_or(i32 inreg %cond) {194; GFX1010-LABEL: combine_add_zext_or:195; GFX1010: ; %bb.0: ; %.entry196; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)197; GFX1010-NEXT: s_cmp_lg_u32 s16, 0198; GFX1010-NEXT: s_mov_b32 s5, 0199; GFX1010-NEXT: s_cselect_b32 s4, -1, 0200; GFX1010-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4201; GFX1010-NEXT: v_cmp_ne_u32_e64 s4, 1, v0202; GFX1010-NEXT: s_branch .LBB2_2203; GFX1010-NEXT: .LBB2_1: ; %bb9204; GFX1010-NEXT: ; in Loop: Header=BB2_2 Depth=1205; GFX1010-NEXT: s_cmpk_gt_i32 s5, 0xfbe6206; GFX1010-NEXT: s_cselect_b32 s7, -1, 0207; GFX1010-NEXT: s_add_i32 s5, s5, 1208; GFX1010-NEXT: s_and_b32 vcc_lo, exec_lo, s7209; GFX1010-NEXT: s_cbranch_vccz .LBB2_4210; GFX1010-NEXT: .LBB2_2: ; %.a211; GFX1010-NEXT: ; =>This Inner Loop Header: Depth=1212; GFX1010-NEXT: s_and_b32 vcc_lo, exec_lo, s4213; GFX1010-NEXT: ; implicit-def: $sgpr6214; GFX1010-NEXT: s_cbranch_vccnz .LBB2_1215; GFX1010-NEXT: ; %bb.3: ; %bb216; GFX1010-NEXT: ; in Loop: Header=BB2_2 Depth=1217; GFX1010-NEXT: v_mov_b32_e32 v0, s5218; GFX1010-NEXT: buffer_load_dword v0, v0, s[4:7], 64 offen glc219; GFX1010-NEXT: s_waitcnt vmcnt(0)220; GFX1010-NEXT: v_cmp_eq_u32_e64 s6, 0, v0221; GFX1010-NEXT: s_branch .LBB2_1222; GFX1010-NEXT: .LBB2_4: ; %.exit223; GFX1010-NEXT: s_or_b32 s4, s6, s7224; GFX1010-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4225; GFX1010-NEXT: s_setpc_b64 s[30:31]226;227; GFX1100-LABEL: combine_add_zext_or:228; GFX1100: ; %bb.0: ; %.entry229; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)230; GFX1100-NEXT: s_cmp_lg_u32 s0, 0231; GFX1100-NEXT: s_mov_b32 s1, 0232; GFX1100-NEXT: s_cselect_b32 s0, -1, 0233; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)234; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0235; GFX1100-NEXT: v_cmp_ne_u32_e64 s0, 1, v0236; GFX1100-NEXT: s_branch .LBB2_2237; GFX1100-NEXT: .LBB2_1: ; %bb9238; GFX1100-NEXT: ; in Loop: Header=BB2_2 Depth=1239; GFX1100-NEXT: s_cmpk_gt_i32 s1, 0xfbe6240; GFX1100-NEXT: s_cselect_b32 s3, -1, 0241; GFX1100-NEXT: s_add_i32 s1, s1, 1242; GFX1100-NEXT: s_and_b32 vcc_lo, exec_lo, s3243; GFX1100-NEXT: s_cbranch_vccz .LBB2_4244; GFX1100-NEXT: .LBB2_2: ; %.a245; GFX1100-NEXT: ; =>This Inner Loop Header: Depth=1246; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)247; GFX1100-NEXT: s_and_b32 vcc_lo, exec_lo, s0248; GFX1100-NEXT: ; implicit-def: $sgpr2249; GFX1100-NEXT: s_cbranch_vccnz .LBB2_1250; GFX1100-NEXT: ; %bb.3: ; %bb251; GFX1100-NEXT: ; in Loop: Header=BB2_2 Depth=1252; GFX1100-NEXT: v_mov_b32_e32 v0, s1253; GFX1100-NEXT: buffer_load_b32 v0, v0, s[0:3], 64 offen glc254; GFX1100-NEXT: s_waitcnt vmcnt(0)255; GFX1100-NEXT: v_cmp_eq_u32_e64 s2, 0, v0256; GFX1100-NEXT: s_branch .LBB2_1257; GFX1100-NEXT: .LBB2_4: ; %.exit258; GFX1100-NEXT: s_or_b32 s0, s2, s3259; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)260; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0261; GFX1100-NEXT: s_setpc_b64 s[30:31]262.entry:263 br label %.a264 265.a: ; preds = %bb9, %.entry266 %.2 = phi i32 [ 0, %.entry ], [ %i11, %bb9 ]267 %cmp = icmp eq i32 %cond, 0268 br i1 %cmp, label %bb9, label %bb269 270bb: ; preds = %.a271 %.i3 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) poison, i32 %.2, i32 64, i32 1)272 %i5 = icmp eq i32 %.i3, 0273 br label %bb9274 275bb9: ; preds = %bb, %.a276 %.2.0.in.in = phi i1 [ %i5, %bb ], [ poison, %.a ]277 %t = icmp sgt i32 %.2, -1050278 %.2.0.in = or i1 %.2.0.in.in, %t279 %.2.0 = zext i1 %.2.0.in to i32280 %i11 = add i32 %.2, %.2.0281 %i12 = icmp sgt i32 %.2, -1050282 br i1 %i12, label %.a, label %.exit283 284.exit: ; preds = %bb9285 ret i32 %.2.0286}287 288; Test that unused lanes in the s_or result are masked out with v_cndmask.289 290define i32 @combine_sub_zext_or(i32 inreg %cond) {291; GFX1010-LABEL: combine_sub_zext_or:292; GFX1010: ; %bb.0: ; %.entry293; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)294; GFX1010-NEXT: s_cmp_lg_u32 s16, 0295; GFX1010-NEXT: s_mov_b32 s5, 0296; GFX1010-NEXT: s_cselect_b32 s4, -1, 0297; GFX1010-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4298; GFX1010-NEXT: v_cmp_ne_u32_e64 s4, 1, v0299; GFX1010-NEXT: s_branch .LBB3_2300; GFX1010-NEXT: .LBB3_1: ; %bb9301; GFX1010-NEXT: ; in Loop: Header=BB3_2 Depth=1302; GFX1010-NEXT: s_cmpk_gt_i32 s5, 0xfbe6303; GFX1010-NEXT: s_cselect_b32 s7, -1, 0304; GFX1010-NEXT: s_add_i32 s5, s5, -1305; GFX1010-NEXT: s_and_b32 vcc_lo, exec_lo, s7306; GFX1010-NEXT: s_cbranch_vccz .LBB3_4307; GFX1010-NEXT: .LBB3_2: ; %.a308; GFX1010-NEXT: ; =>This Inner Loop Header: Depth=1309; GFX1010-NEXT: s_and_b32 vcc_lo, exec_lo, s4310; GFX1010-NEXT: ; implicit-def: $sgpr6311; GFX1010-NEXT: s_cbranch_vccnz .LBB3_1312; GFX1010-NEXT: ; %bb.3: ; %bb313; GFX1010-NEXT: ; in Loop: Header=BB3_2 Depth=1314; GFX1010-NEXT: v_mov_b32_e32 v0, s5315; GFX1010-NEXT: buffer_load_dword v0, v0, s[4:7], 64 offen glc316; GFX1010-NEXT: s_waitcnt vmcnt(0)317; GFX1010-NEXT: v_cmp_eq_u32_e64 s6, 0, v0318; GFX1010-NEXT: s_branch .LBB3_1319; GFX1010-NEXT: .LBB3_4: ; %.exit320; GFX1010-NEXT: s_or_b32 s4, s6, s7321; GFX1010-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4322; GFX1010-NEXT: s_setpc_b64 s[30:31]323;324; GFX1100-LABEL: combine_sub_zext_or:325; GFX1100: ; %bb.0: ; %.entry326; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)327; GFX1100-NEXT: s_cmp_lg_u32 s0, 0328; GFX1100-NEXT: s_mov_b32 s1, 0329; GFX1100-NEXT: s_cselect_b32 s0, -1, 0330; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)331; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0332; GFX1100-NEXT: v_cmp_ne_u32_e64 s0, 1, v0333; GFX1100-NEXT: s_branch .LBB3_2334; GFX1100-NEXT: .LBB3_1: ; %bb9335; GFX1100-NEXT: ; in Loop: Header=BB3_2 Depth=1336; GFX1100-NEXT: s_cmpk_gt_i32 s1, 0xfbe6337; GFX1100-NEXT: s_cselect_b32 s3, -1, 0338; GFX1100-NEXT: s_add_i32 s1, s1, -1339; GFX1100-NEXT: s_and_b32 vcc_lo, exec_lo, s3340; GFX1100-NEXT: s_cbranch_vccz .LBB3_4341; GFX1100-NEXT: .LBB3_2: ; %.a342; GFX1100-NEXT: ; =>This Inner Loop Header: Depth=1343; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)344; GFX1100-NEXT: s_and_b32 vcc_lo, exec_lo, s0345; GFX1100-NEXT: ; implicit-def: $sgpr2346; GFX1100-NEXT: s_cbranch_vccnz .LBB3_1347; GFX1100-NEXT: ; %bb.3: ; %bb348; GFX1100-NEXT: ; in Loop: Header=BB3_2 Depth=1349; GFX1100-NEXT: v_mov_b32_e32 v0, s1350; GFX1100-NEXT: buffer_load_b32 v0, v0, s[0:3], 64 offen glc351; GFX1100-NEXT: s_waitcnt vmcnt(0)352; GFX1100-NEXT: v_cmp_eq_u32_e64 s2, 0, v0353; GFX1100-NEXT: s_branch .LBB3_1354; GFX1100-NEXT: .LBB3_4: ; %.exit355; GFX1100-NEXT: s_or_b32 s0, s2, s3356; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)357; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0358; GFX1100-NEXT: s_setpc_b64 s[30:31]359.entry:360 br label %.a361 362.a: ; preds = %bb9, %.entry363 %.2 = phi i32 [ 0, %.entry ], [ %i11, %bb9 ]364 %cmp = icmp eq i32 %cond, 0365 br i1 %cmp, label %bb9, label %bb366 367bb: ; preds = %.a368 %.i3 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) poison, i32 %.2, i32 64, i32 1)369 %i5 = icmp eq i32 %.i3, 0370 br label %bb9371 372bb9: ; preds = %bb, %.a373 %.2.0.in.in = phi i1 [ %i5, %bb ], [ poison, %.a ]374 %t = icmp sgt i32 %.2, -1050375 %.2.0.in = or i1 %.2.0.in.in, %t376 %.2.0 = zext i1 %.2.0.in to i32377 %i11 = sub i32 %.2, %.2.0378 %i12 = icmp sgt i32 %.2, -1050379 br i1 %i12, label %.a, label %.exit380 381.exit: ; preds = %bb9382 ret i32 %.2.0383}384 385; Test that unused lanes in the s_and result are masked out with v_cndmask.386 387define i32 @combine_add_zext_and(i32 inreg %cond) {388; GFX1010-LABEL: combine_add_zext_and:389; GFX1010: ; %bb.0: ; %.entry390; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)391; GFX1010-NEXT: s_cmp_lg_u32 s16, 0392; GFX1010-NEXT: v_mov_b32_e32 v1, 0393; GFX1010-NEXT: s_cselect_b32 s4, -1, 0394; GFX1010-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4395; GFX1010-NEXT: v_cmp_ne_u32_e64 s4, 1, v0396; GFX1010-NEXT: s_branch .LBB4_2397; GFX1010-NEXT: .LBB4_1: ; %bb9398; GFX1010-NEXT: ; in Loop: Header=BB4_2 Depth=1399; GFX1010-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfffffbe6, v1400; GFX1010-NEXT: s_and_b32 s5, s5, vcc_lo401; GFX1010-NEXT: v_cndmask_b32_e64 v0, 0, 1, s5402; GFX1010-NEXT: v_add_nc_u32_e32 v1, v1, v0403; GFX1010-NEXT: s_cbranch_vccz .LBB4_4404; GFX1010-NEXT: .LBB4_2: ; %.a405; GFX1010-NEXT: ; =>This Inner Loop Header: Depth=1406; GFX1010-NEXT: s_and_b32 vcc_lo, exec_lo, s4407; GFX1010-NEXT: ; implicit-def: $sgpr5408; GFX1010-NEXT: s_cbranch_vccnz .LBB4_1409; GFX1010-NEXT: ; %bb.3: ; %bb410; GFX1010-NEXT: ; in Loop: Header=BB4_2 Depth=1411; GFX1010-NEXT: buffer_load_dword v0, v1, s[4:7], 64 offen glc412; GFX1010-NEXT: s_waitcnt vmcnt(0)413; GFX1010-NEXT: v_cmp_eq_u32_e64 s5, 0, v0414; GFX1010-NEXT: s_branch .LBB4_1415; GFX1010-NEXT: .LBB4_4: ; %.exit416; GFX1010-NEXT: s_setpc_b64 s[30:31]417;418; GFX1100-LABEL: combine_add_zext_and:419; GFX1100: ; %bb.0: ; %.entry420; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)421; GFX1100-NEXT: s_cmp_lg_u32 s0, 0422; GFX1100-NEXT: v_mov_b32_e32 v1, 0423; GFX1100-NEXT: s_cselect_b32 s0, -1, 0424; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)425; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0426; GFX1100-NEXT: v_cmp_ne_u32_e64 s0, 1, v0427; GFX1100-NEXT: s_branch .LBB4_2428; GFX1100-NEXT: .LBB4_1: ; %bb9429; GFX1100-NEXT: ; in Loop: Header=BB4_2 Depth=1430; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)431; GFX1100-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfffffbe6, v1432; GFX1100-NEXT: s_and_b32 s1, s1, vcc_lo433; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)434; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1435; GFX1100-NEXT: v_add_nc_u32_e32 v1, v1, v0436; GFX1100-NEXT: s_cbranch_vccz .LBB4_4437; GFX1100-NEXT: .LBB4_2: ; %.a438; GFX1100-NEXT: ; =>This Inner Loop Header: Depth=1439; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)440; GFX1100-NEXT: s_and_b32 vcc_lo, exec_lo, s0441; GFX1100-NEXT: ; implicit-def: $sgpr1442; GFX1100-NEXT: s_cbranch_vccnz .LBB4_1443; GFX1100-NEXT: ; %bb.3: ; %bb444; GFX1100-NEXT: ; in Loop: Header=BB4_2 Depth=1445; GFX1100-NEXT: buffer_load_b32 v0, v1, s[0:3], 64 offen glc446; GFX1100-NEXT: s_waitcnt vmcnt(0)447; GFX1100-NEXT: v_cmp_eq_u32_e64 s1, 0, v0448; GFX1100-NEXT: s_branch .LBB4_1449; GFX1100-NEXT: .LBB4_4: ; %.exit450; GFX1100-NEXT: s_setpc_b64 s[30:31]451.entry:452 br label %.a453 454.a: ; preds = %bb9, %.entry455 %.2 = phi i32 [ 0, %.entry ], [ %i11, %bb9 ]456 %cmp = icmp eq i32 %cond, 0457 br i1 %cmp, label %bb9, label %bb458 459bb: ; preds = %.a460 %.i3 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) poison, i32 %.2, i32 64, i32 1)461 %i5 = icmp eq i32 %.i3, 0462 br label %bb9463 464bb9: ; preds = %bb, %.a465 %.2.0.in.in = phi i1 [ %i5, %bb ], [ poison, %.a ]466 %t = icmp sgt i32 %.2, -1050467 %.2.0.in = and i1 %.2.0.in.in, %t468 %.2.0 = zext i1 %.2.0.in to i32469 %i11 = add i32 %.2, %.2.0470 %i12 = icmp sgt i32 %.2, -1050471 br i1 %i12, label %.a, label %.exit472 473.exit: ; preds = %bb9474 ret i32 %.2.0475}476 477; Test that unused lanes in the s_and result are masked out with v_cndmask.478 479define i32 @combine_sub_zext_and(i32 inreg %cond) {480; GFX1010-LABEL: combine_sub_zext_and:481; GFX1010: ; %bb.0: ; %.entry482; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)483; GFX1010-NEXT: s_cmp_lg_u32 s16, 0484; GFX1010-NEXT: v_mov_b32_e32 v1, 0485; GFX1010-NEXT: s_cselect_b32 s4, -1, 0486; GFX1010-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4487; GFX1010-NEXT: v_cmp_ne_u32_e64 s4, 1, v0488; GFX1010-NEXT: s_branch .LBB5_2489; GFX1010-NEXT: .LBB5_1: ; %bb9490; GFX1010-NEXT: ; in Loop: Header=BB5_2 Depth=1491; GFX1010-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfffffbe6, v1492; GFX1010-NEXT: s_and_b32 s5, s5, vcc_lo493; GFX1010-NEXT: v_cndmask_b32_e64 v0, 0, 1, s5494; GFX1010-NEXT: v_sub_nc_u32_e32 v1, v1, v0495; GFX1010-NEXT: s_cbranch_vccz .LBB5_4496; GFX1010-NEXT: .LBB5_2: ; %.a497; GFX1010-NEXT: ; =>This Inner Loop Header: Depth=1498; GFX1010-NEXT: s_and_b32 vcc_lo, exec_lo, s4499; GFX1010-NEXT: ; implicit-def: $sgpr5500; GFX1010-NEXT: s_cbranch_vccnz .LBB5_1501; GFX1010-NEXT: ; %bb.3: ; %bb502; GFX1010-NEXT: ; in Loop: Header=BB5_2 Depth=1503; GFX1010-NEXT: buffer_load_dword v0, v1, s[4:7], 64 offen glc504; GFX1010-NEXT: s_waitcnt vmcnt(0)505; GFX1010-NEXT: v_cmp_eq_u32_e64 s5, 0, v0506; GFX1010-NEXT: s_branch .LBB5_1507; GFX1010-NEXT: .LBB5_4: ; %.exit508; GFX1010-NEXT: s_setpc_b64 s[30:31]509;510; GFX1100-LABEL: combine_sub_zext_and:511; GFX1100: ; %bb.0: ; %.entry512; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)513; GFX1100-NEXT: s_cmp_lg_u32 s0, 0514; GFX1100-NEXT: v_mov_b32_e32 v1, 0515; GFX1100-NEXT: s_cselect_b32 s0, -1, 0516; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)517; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0518; GFX1100-NEXT: v_cmp_ne_u32_e64 s0, 1, v0519; GFX1100-NEXT: s_branch .LBB5_2520; GFX1100-NEXT: .LBB5_1: ; %bb9521; GFX1100-NEXT: ; in Loop: Header=BB5_2 Depth=1522; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)523; GFX1100-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfffffbe6, v1524; GFX1100-NEXT: s_and_b32 s1, s1, vcc_lo525; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)526; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1527; GFX1100-NEXT: v_sub_nc_u32_e32 v1, v1, v0528; GFX1100-NEXT: s_cbranch_vccz .LBB5_4529; GFX1100-NEXT: .LBB5_2: ; %.a530; GFX1100-NEXT: ; =>This Inner Loop Header: Depth=1531; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)532; GFX1100-NEXT: s_and_b32 vcc_lo, exec_lo, s0533; GFX1100-NEXT: ; implicit-def: $sgpr1534; GFX1100-NEXT: s_cbranch_vccnz .LBB5_1535; GFX1100-NEXT: ; %bb.3: ; %bb536; GFX1100-NEXT: ; in Loop: Header=BB5_2 Depth=1537; GFX1100-NEXT: buffer_load_b32 v0, v1, s[0:3], 64 offen glc538; GFX1100-NEXT: s_waitcnt vmcnt(0)539; GFX1100-NEXT: v_cmp_eq_u32_e64 s1, 0, v0540; GFX1100-NEXT: s_branch .LBB5_1541; GFX1100-NEXT: .LBB5_4: ; %.exit542; GFX1100-NEXT: s_setpc_b64 s[30:31]543.entry:544 br label %.a545 546.a: ; preds = %bb9, %.entry547 %.2 = phi i32 [ 0, %.entry ], [ %i11, %bb9 ]548 %cmp = icmp eq i32 %cond, 0549 br i1 %cmp, label %bb9, label %bb550 551bb: ; preds = %.a552 %.i3 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) poison, i32 %.2, i32 64, i32 1)553 %i5 = icmp eq i32 %.i3, 0554 br label %bb9555 556bb9: ; preds = %bb, %.a557 %.2.0.in.in = phi i1 [ %i5, %bb ], [ poison, %.a ]558 %t = icmp sgt i32 %.2, -1050559 %.2.0.in = and i1 %.2.0.in.in, %t560 %.2.0 = zext i1 %.2.0.in to i32561 %i11 = sub i32 %.2, %.2.0562 %i12 = icmp sgt i32 %.2, -1050563 br i1 %i12, label %.a, label %.exit564 565.exit: ; preds = %bb9566 ret i32 %.2.0567}568 569 570; Function Attrs: nounwind readonly willreturn571declare i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) nocapture, i32, i32, i32 immarg) #0572 573attributes #0 = { nounwind willreturn memory(argmem: read) }574 575