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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s3 4define amdgpu_kernel void @and_i1_sext_bool(ptr addrspace(1) nocapture %arg) {5; GCN-LABEL: and_i1_sext_bool:6; GCN: ; %bb.0: ; %bb7; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x98; GCN-NEXT: s_mov_b32 s3, 0xf0009; GCN-NEXT: s_mov_b32 s2, 010; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v011; GCN-NEXT: v_mov_b32_e32 v3, 012; GCN-NEXT: s_waitcnt lgkmcnt(0)13; GCN-NEXT: buffer_load_dword v4, v[2:3], s[0:3], 0 addr6414; GCN-NEXT: v_cmp_gt_u32_e32 vcc, v0, v115; GCN-NEXT: s_waitcnt vmcnt(0)16; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc17; GCN-NEXT: buffer_store_dword v0, v[2:3], s[0:3], 0 addr6418; GCN-NEXT: s_endpgm19bb:20 %x = tail call i32 @llvm.amdgcn.workitem.id.x()21 %y = tail call i32 @llvm.amdgcn.workitem.id.y()22 %gep = getelementptr inbounds i32, ptr addrspace(1) %arg, i32 %x23 %v = load i32, ptr addrspace(1) %gep, align 424 %cmp = icmp ugt i32 %x, %y25 %ext = sext i1 %cmp to i3226 %and = and i32 %v, %ext27 store i32 %and, ptr addrspace(1) %gep, align 428 ret void29}30 31define i32 @and_sext_bool_fcmp(float %x, i32 %y) {32; GCN-LABEL: and_sext_bool_fcmp:33; GCN: ; %bb.0:34; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)35; GCN-NEXT: v_cmp_eq_f32_e32 vcc, 0, v036; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc37; GCN-NEXT: s_setpc_b64 s[30:31]38 %cmp = fcmp oeq float %x, 0.039 %sext = sext i1 %cmp to i3240 %and = and i32 %sext, %y41 ret i32 %and42}43 44define i32 @and_sext_bool_fpclass(float %x, i32 %y) {45; GCN-LABEL: and_sext_bool_fpclass:46; GCN: ; %bb.0:47; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)48; GCN-NEXT: v_mov_b32_e32 v2, 0x7b49; GCN-NEXT: v_cmp_class_f32_e32 vcc, v0, v250; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc51; GCN-NEXT: s_setpc_b64 s[30:31]52 %class = call i1 @llvm.is.fpclass(float %x, i32 123)53 %sext = sext i1 %class to i3254 %and = and i32 %sext, %y55 ret i32 %and56}57 58define i32 @and_sext_bool_uadd_w_overflow(i32 %x, i32 %y) {59; GCN-LABEL: and_sext_bool_uadd_w_overflow:60; GCN: ; %bb.0:61; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)62; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v163; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc64; GCN-NEXT: s_setpc_b64 s[30:31]65 %uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %x, i32 %y)66 %carry = extractvalue { i32, i1 } %uadd, 167 %sext = sext i1 %carry to i3268 %and = and i32 %sext, %y69 ret i32 %and70}71 72define i32 @and_sext_bool_usub_w_overflow(i32 %x, i32 %y) {73; GCN-LABEL: and_sext_bool_usub_w_overflow:74; GCN: ; %bb.0:75; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)76; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v177; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc78; GCN-NEXT: s_setpc_b64 s[30:31]79 %uadd = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %x, i32 %y)80 %carry = extractvalue { i32, i1 } %uadd, 181 %sext = sext i1 %carry to i3282 %and = and i32 %sext, %y83 ret i32 %and84}85 86define i32 @and_sext_bool_sadd_w_overflow(i32 %x, i32 %y) {87; GCN-LABEL: and_sext_bool_sadd_w_overflow:88; GCN: ; %bb.0:89; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)90; GCN-NEXT: v_cmp_gt_i32_e32 vcc, 0, v191; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v0, v192; GCN-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v093; GCN-NEXT: s_xor_b64 vcc, vcc, s[4:5]94; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc95; GCN-NEXT: s_setpc_b64 s[30:31]96 %uadd = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %x, i32 %y)97 %carry = extractvalue { i32, i1 } %uadd, 198 %sext = sext i1 %carry to i3299 %and = and i32 %sext, %y100 ret i32 %and101}102 103define i32 @and_sext_bool_ssub_w_overflow(i32 %x, i32 %y) {104; GCN-LABEL: and_sext_bool_ssub_w_overflow:105; GCN: ; %bb.0:106; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)107; GCN-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1108; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v0, v1109; GCN-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0110; GCN-NEXT: s_xor_b64 vcc, vcc, s[4:5]111; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc112; GCN-NEXT: s_setpc_b64 s[30:31]113 %uadd = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %x, i32 %y)114 %carry = extractvalue { i32, i1 } %uadd, 1115 %sext = sext i1 %carry to i32116 %and = and i32 %sext, %y117 ret i32 %and118}119 120define i32 @and_sext_bool_smul_w_overflow(i32 %x, i32 %y) {121; GCN-LABEL: and_sext_bool_smul_w_overflow:122; GCN: ; %bb.0:123; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)124; GCN-NEXT: v_mul_hi_i32 v2, v0, v1125; GCN-NEXT: v_mul_lo_u32 v0, v0, v1126; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v0127; GCN-NEXT: v_cmp_ne_u32_e32 vcc, v2, v0128; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc129; GCN-NEXT: s_setpc_b64 s[30:31]130 %uadd = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %x, i32 %y)131 %carry = extractvalue { i32, i1 } %uadd, 1132 %sext = sext i1 %carry to i32133 %and = and i32 %sext, %y134 ret i32 %and135}136 137define i32 @and_sext_bool_umul_w_overflow(i32 %x, i32 %y) {138; GCN-LABEL: and_sext_bool_umul_w_overflow:139; GCN: ; %bb.0:140; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)141; GCN-NEXT: v_mul_hi_u32 v0, v0, v1142; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0143; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc144; GCN-NEXT: s_setpc_b64 s[30:31]145 %uadd = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)146 %carry = extractvalue { i32, i1 } %uadd, 1147 %sext = sext i1 %carry to i32148 %and = and i32 %sext, %y149 ret i32 %and150}151 152 153declare i32 @llvm.amdgcn.workitem.id.x() #0154 155declare i32 @llvm.amdgcn.workitem.id.y() #0156 157attributes #0 = { nounwind readnone speculatable }158