256 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck -check-prefix=GCN %s3 4define amdgpu_kernel void @vectorLoadCombine(ptr %in, ptr %out) {5; GCN-LABEL: vectorLoadCombine:6; GCN: ; %bb.0: ; %entry7; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x248; GCN-NEXT: s_waitcnt lgkmcnt(0)9; GCN-NEXT: v_mov_b32_e32 v0, s010; GCN-NEXT: v_mov_b32_e32 v1, s111; GCN-NEXT: flat_load_dword v2, v[0:1]12; GCN-NEXT: v_mov_b32_e32 v0, s213; GCN-NEXT: v_mov_b32_e32 v1, s314; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)15; GCN-NEXT: flat_store_dword v[0:1], v216; GCN-NEXT: s_endpgm17entry:18 %0 = load <4 x i8>, ptr %in, align 419 %1 = extractelement <4 x i8> %0, i32 020 %2 = extractelement <4 x i8> %0, i32 121 %3 = extractelement <4 x i8> %0, i32 222 %4 = extractelement <4 x i8> %0, i32 323 %zext0 = zext i8 %1 to i3224 %zext1 = zext i8 %2 to i3225 %shift1 = shl nuw nsw i32 %zext1, 826 %insert1 = or i32 %shift1, %zext027 %zext2 = zext i8 %3 to i3228 %shift2 = shl nuw nsw i32 %zext2, 1629 %insert2 = or i32 %insert1, %shift230 %zext3 = zext i8 %4 to i3231 %shift3 = shl nuw i32 %zext3, 2432 %insert3 = or i32 %insert2, %shift333 store i32 %insert3, ptr %out34 ret void35}36 37define amdgpu_kernel void @vectorLoadShuffle(ptr %in, ptr %out) {38; GCN-LABEL: vectorLoadShuffle:39; GCN: ; %bb.0: ; %entry40; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2441; GCN-NEXT: s_waitcnt lgkmcnt(0)42; GCN-NEXT: v_mov_b32_e32 v0, s043; GCN-NEXT: v_mov_b32_e32 v1, s144; GCN-NEXT: flat_load_dword v2, v[0:1]45; GCN-NEXT: s_mov_b32 s0, 0x705060446; GCN-NEXT: v_mov_b32_e32 v0, s247; GCN-NEXT: v_mov_b32_e32 v1, s348; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)49; GCN-NEXT: v_perm_b32 v2, v2, v2, s050; GCN-NEXT: flat_store_dword v[0:1], v251; GCN-NEXT: s_endpgm52entry:53 %0 = load <4 x i8>, ptr %in, align 454 %1 = extractelement <4 x i8> %0, i32 055 %2 = extractelement <4 x i8> %0, i32 156 %3 = extractelement <4 x i8> %0, i32 257 %4 = extractelement <4 x i8> %0, i32 358 %zext0 = zext i8 %1 to i3259 %zext1 = zext i8 %3 to i3260 %shift1 = shl nuw nsw i32 %zext1, 861 %insert1 = or i32 %shift1, %zext062 %zext2 = zext i8 %2 to i3263 %shift2 = shl nuw nsw i32 %zext2, 1664 %insert2 = or i32 %insert1, %shift265 %zext3 = zext i8 %4 to i3266 %shift3 = shl nuw i32 %zext3, 2467 %insert3 = or i32 %insert2, %shift368 store i32 %insert3, ptr %out69 ret void70}71define i32 @load_2xi16_combine(ptr addrspace(1) %p) #0 {72; GCN-LABEL: load_2xi16_combine:73; GCN: ; %bb.0:74; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)75; GCN-NEXT: global_load_dword v0, v[0:1], off76; GCN-NEXT: s_waitcnt vmcnt(0)77; GCN-NEXT: s_setpc_b64 s[30:31]78 %gep.p = getelementptr i16, ptr addrspace(1) %p, i32 179 %p.0 = load i16, ptr addrspace(1) %p, align 480 %p.1 = load i16, ptr addrspace(1) %gep.p, align 481 %zext.0 = zext i16 %p.0 to i3282 %zext.1 = zext i16 %p.1 to i3283 %shl.1 = shl i32 %zext.1, 1684 %or = or i32 %zext.0, %shl.185 ret i32 %or86}87 88define i32 @load_2xi16_noncombine(ptr addrspace(1) %p) #0 {89; GCN-LABEL: load_2xi16_noncombine:90; GCN: ; %bb.0:91; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)92; GCN-NEXT: global_load_ushort v2, v[0:1], off93; GCN-NEXT: global_load_ushort v3, v[0:1], off offset:494; GCN-NEXT: s_waitcnt vmcnt(0)95; GCN-NEXT: v_lshl_or_b32 v0, v3, 16, v296; GCN-NEXT: s_setpc_b64 s[30:31]97 %gep.p = getelementptr i16, ptr addrspace(1) %p, i32 298 %p.0 = load i16, ptr addrspace(1) %p, align 499 %p.1 = load i16, ptr addrspace(1) %gep.p, align 4100 %zext.0 = zext i16 %p.0 to i32101 %zext.1 = zext i16 %p.1 to i32102 %shl.1 = shl i32 %zext.1, 16103 %or = or i32 %zext.0, %shl.1104 ret i32 %or105}106 107define i64 @load_2xi32_combine(ptr addrspace(1) %p) #0 {108; GCN-LABEL: load_2xi32_combine:109; GCN: ; %bb.0:110; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)111; GCN-NEXT: global_load_dwordx2 v[0:1], v[0:1], off112; GCN-NEXT: s_waitcnt vmcnt(0)113; GCN-NEXT: s_setpc_b64 s[30:31]114 %gep.p = getelementptr i32, ptr addrspace(1) %p, i32 1115 %p.0 = load i32, ptr addrspace(1) %p, align 4116 %p.1 = load i32, ptr addrspace(1) %gep.p, align 4117 %zext.0 = zext i32 %p.0 to i64118 %zext.1 = zext i32 %p.1 to i64119 %shl.1 = shl i64 %zext.1, 32120 %or = or i64 %zext.0, %shl.1121 ret i64 %or122}123 124define i64 @load_2xi32_noncombine(ptr addrspace(1) %p) #0 {125; GCN-LABEL: load_2xi32_noncombine:126; GCN: ; %bb.0:127; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)128; GCN-NEXT: global_load_dword v2, v[0:1], off129; GCN-NEXT: global_load_dword v3, v[0:1], off offset:8130; GCN-NEXT: s_waitcnt vmcnt(1)131; GCN-NEXT: v_mov_b32_e32 v0, v2132; GCN-NEXT: s_waitcnt vmcnt(0)133; GCN-NEXT: v_mov_b32_e32 v1, v3134; GCN-NEXT: s_setpc_b64 s[30:31]135 %gep.p = getelementptr i32, ptr addrspace(1) %p, i32 2136 %p.0 = load i32, ptr addrspace(1) %p, align 4137 %p.1 = load i32, ptr addrspace(1) %gep.p, align 4138 %zext.0 = zext i32 %p.0 to i64139 %zext.1 = zext i32 %p.1 to i64140 %shl.1 = shl i64 %zext.1, 32141 %or = or i64 %zext.0, %shl.1142 ret i64 %or143}144 145define i64 @load_4xi16_combine(ptr addrspace(1) %p) #0 {146; GCN-LABEL: load_4xi16_combine:147; GCN: ; %bb.0:148; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)149; GCN-NEXT: global_load_dwordx2 v[0:1], v[0:1], off150; GCN-NEXT: s_waitcnt vmcnt(0)151; GCN-NEXT: s_setpc_b64 s[30:31]152 %gep.p = getelementptr i16, ptr addrspace(1) %p, i32 1153 %gep.2p = getelementptr i16, ptr addrspace(1) %p, i32 2154 %gep.3p = getelementptr i16, ptr addrspace(1) %p, i32 3155 %p.0 = load i16, ptr addrspace(1) %p, align 4156 %p.1 = load i16, ptr addrspace(1) %gep.p, align 4157 %p.2 = load i16, ptr addrspace(1) %gep.2p, align 4158 %p.3 = load i16, ptr addrspace(1) %gep.3p, align 4159 %zext.0 = zext i16 %p.0 to i64160 %zext.1 = zext i16 %p.1 to i64161 %zext.2 = zext i16 %p.2 to i64162 %zext.3 = zext i16 %p.3 to i64163 %shl.1 = shl i64 %zext.1, 16164 %or.1 = or i64 %zext.0, %shl.1165 %shl.2 = shl i64 %zext.2, 32166 %or.2 = or i64 %or.1, %shl.2167 %shl.3 = shl i64 %zext.3, 48168 %or.3 = or i64 %or.2, %shl.3169 ret i64 %or.3170}171 172 173define i64 @load_4xi16_noncombine(ptr addrspace(1) %p) #0 {174; GCN-LABEL: load_4xi16_noncombine:175; GCN: ; %bb.0:176; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)177; GCN-NEXT: global_load_dwordx2 v[2:3], v[0:1], off178; GCN-NEXT: s_mov_b32 s4, 0xffff179; GCN-NEXT: s_waitcnt vmcnt(0)180; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v2181; GCN-NEXT: v_bfi_b32 v0, s4, v2, v3182; GCN-NEXT: v_or_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD183; GCN-NEXT: s_setpc_b64 s[30:31]184 %gep.p = getelementptr i16, ptr addrspace(1) %p, i32 3185 %gep.2p = getelementptr i16, ptr addrspace(1) %p, i32 2186 %gep.3p = getelementptr i16, ptr addrspace(1) %p, i32 1187 %p.0 = load i16, ptr addrspace(1) %p, align 4188 %p.1 = load i16, ptr addrspace(1) %gep.p, align 4189 %p.2 = load i16, ptr addrspace(1) %gep.2p, align 4190 %p.3 = load i16, ptr addrspace(1) %gep.3p, align 4191 %zext.0 = zext i16 %p.0 to i64192 %zext.1 = zext i16 %p.1 to i64193 %zext.2 = zext i16 %p.2 to i64194 %zext.3 = zext i16 %p.3 to i64195 %shl.1 = shl i64 %zext.1, 16196 %or.1 = or i64 %zext.0, %shl.1197 %shl.2 = shl i64 %zext.2, 32198 %or.2 = or i64 %or.1, %shl.2199 %shl.3 = shl i64 %zext.3, 48200 %or.3 = or i64 %or.2, %shl.3201 ret i64 %or.3202}203 204define i64 @load_3xi16_combine(ptr addrspace(1) %p) #0 {205; GCN-LABEL: load_3xi16_combine:206; GCN: ; %bb.0:207; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)208; GCN-NEXT: global_load_dword v2, v[0:1], off209; GCN-NEXT: global_load_ushort v3, v[0:1], off offset:4210; GCN-NEXT: s_waitcnt vmcnt(1)211; GCN-NEXT: v_mov_b32_e32 v0, v2212; GCN-NEXT: s_waitcnt vmcnt(0)213; GCN-NEXT: v_mov_b32_e32 v1, v3214; GCN-NEXT: s_setpc_b64 s[30:31]215 %gep.p = getelementptr i16, ptr addrspace(1) %p, i32 1216 %gep.2p = getelementptr i16, ptr addrspace(1) %p, i32 2217 %p.0 = load i16, ptr addrspace(1) %p, align 4218 %p.1 = load i16, ptr addrspace(1) %gep.p, align 4219 %p.2 = load i16, ptr addrspace(1) %gep.2p, align 4220 %zext.0 = zext i16 %p.0 to i64221 %zext.1 = zext i16 %p.1 to i64222 %zext.2 = zext i16 %p.2 to i64223 %shl.1 = shl i64 %zext.1, 16224 %or.1 = or i64 %zext.0, %shl.1225 %shl.2 = shl i64 %zext.2, 32226 %or.2 = or i64 %or.1, %shl.2227 ret i64 %or.2228}229 230define i64 @load_3xi16_noncombine(ptr addrspace(1) %p) #0 {231; GCN-LABEL: load_3xi16_noncombine:232; GCN: ; %bb.0:233; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)234; GCN-NEXT: global_load_ushort v2, v[0:1], off235; GCN-NEXT: global_load_dword v3, v[0:1], off offset:4236; GCN-NEXT: s_mov_b32 s4, 0x3020504237; GCN-NEXT: s_waitcnt vmcnt(0)238; GCN-NEXT: v_perm_b32 v0, v2, v3, s4239; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v3240; GCN-NEXT: s_setpc_b64 s[30:31]241 %gep.p = getelementptr i16, ptr addrspace(1) %p, i32 3242 %gep.2p = getelementptr i16, ptr addrspace(1) %p, i32 2243 %p.0 = load i16, ptr addrspace(1) %p, align 4244 %p.1 = load i16, ptr addrspace(1) %gep.p, align 4245 %p.2 = load i16, ptr addrspace(1) %gep.2p, align 4246 %zext.0 = zext i16 %p.0 to i64247 %zext.1 = zext i16 %p.1 to i64248 %zext.2 = zext i16 %p.2 to i64249 %shl.1 = shl i64 %zext.1, 16250 %or.1 = or i64 %zext.0, %shl.1251 %shl.2 = shl i64 %zext.2, 32252 %or.2 = or i64 %or.1, %shl.2253 ret i64 %or.2254}255 256