3392 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck %s -check-prefixes=GCN,GFX11,GFX11-TRUE163; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck %s -check-prefixes=GCN,GFX11,GFX11-FAKE164; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -enable-no-nans-fp-math < %s | FileCheck %s -check-prefixes=GCN,GFX11NONANS,GCN-TRUE16,GFX11NONANS-TRUE165; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -enable-no-nans-fp-math < %s | FileCheck %s -check-prefixes=GCN,GFX11NONANS,GCN-FAKE16,GFX11NONANS-FAKE166 7; The tests check the following optimization of DAGCombiner:8; CMP(A,C)||CMP(B,C) => CMP(MIN/MAX(A,B), C)9; CMP(A,C)&&CMP(B,C) => CMP(MIN/MAX(A,B), C)10 11define i1 @test1(i32 %arg1, i32 %arg2) {12; GCN-LABEL: test1:13; GCN: ; %bb.0:14; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15; GCN-NEXT: v_min_i32_e32 v0, v0, v116; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0x3e8, v017; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo18; GCN-NEXT: s_setpc_b64 s[30:31]19 %cmp1 = icmp slt i32 %arg1, 100020 %cmp2 = icmp slt i32 %arg2, 100021 %or = or i1 %cmp1, %cmp222 ret i1 %or23}24 25define i1 @test2(i32 %arg1, i32 %arg2) {26; GCN-LABEL: test2:27; GCN: ; %bb.0:28; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)29; GCN-NEXT: v_min_u32_e32 v0, v0, v130; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x3e8, v031; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo32; GCN-NEXT: s_setpc_b64 s[30:31]33 %cmp1 = icmp ult i32 %arg1, 100034 %cmp2 = icmp ult i32 %arg2, 100035 %or = or i1 %cmp1, %cmp236 ret i1 %or37}38 39define i1 @test3(i32 %arg1, i32 %arg2) {40; GCN-LABEL: test3:41; GCN: ; %bb.0:42; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)43; GCN-NEXT: v_min_i32_e32 v0, v0, v144; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0x3e9, v045; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo46; GCN-NEXT: s_setpc_b64 s[30:31]47 %cmp1 = icmp sle i32 %arg1, 100048 %cmp2 = icmp sle i32 %arg2, 100049 %or = or i1 %cmp1, %cmp250 ret i1 %or51}52 53define i1 @test4(i32 %arg1, i32 %arg2) {54; GCN-LABEL: test4:55; GCN: ; %bb.0:56; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)57; GCN-NEXT: v_min_u32_e32 v0, v0, v158; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x3e9, v059; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo60; GCN-NEXT: s_setpc_b64 s[30:31]61 %cmp1 = icmp ule i32 %arg1, 100062 %cmp2 = icmp ule i32 %arg2, 100063 %or = or i1 %cmp1, %cmp264 ret i1 %or65}66 67define i1 @test5(i32 %arg1, i32 %arg2) {68; GCN-LABEL: test5:69; GCN: ; %bb.0:70; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)71; GCN-NEXT: v_max_i32_e32 v0, v0, v172; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0x3e8, v073; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo74; GCN-NEXT: s_setpc_b64 s[30:31]75 %cmp1 = icmp sgt i32 %arg1, 100076 %cmp2 = icmp sgt i32 %arg2, 100077 %or = or i1 %cmp1, %cmp278 ret i1 %or79}80 81define i1 @test6(i32 %arg1, i32 %arg2) {82; GCN-LABEL: test6:83; GCN: ; %bb.0:84; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)85; GCN-NEXT: v_max_u32_e32 v0, v0, v186; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3e8, v087; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo88; GCN-NEXT: s_setpc_b64 s[30:31]89 %cmp1 = icmp ugt i32 %arg1, 100090 %cmp2 = icmp ugt i32 %arg2, 100091 %or = or i1 %cmp1, %cmp292 ret i1 %or93}94 95define i1 @test7(i32 %arg1, i32 %arg2) {96; GCN-LABEL: test7:97; GCN: ; %bb.0:98; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)99; GCN-NEXT: v_max_i32_e32 v0, v0, v1100; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0x3e7, v0101; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo102; GCN-NEXT: s_setpc_b64 s[30:31]103 %cmp1 = icmp sge i32 %arg1, 1000104 %cmp2 = icmp sge i32 %arg2, 1000105 %or = or i1 %cmp1, %cmp2106 ret i1 %or107}108 109define i1 @test8(i32 %arg1, i32 %arg2) {110; GCN-LABEL: test8:111; GCN: ; %bb.0:112; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)113; GCN-NEXT: v_max_u32_e32 v0, v0, v1114; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3e7, v0115; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo116; GCN-NEXT: s_setpc_b64 s[30:31]117 %cmp1 = icmp uge i32 %arg1, 1000118 %cmp2 = icmp uge i32 %arg2, 1000119 %or = or i1 %cmp1, %cmp2120 ret i1 %or121}122 123define i1 @test9(i32 %arg1, i32 %arg2, i32 %arg3) {124; GCN-LABEL: test9:125; GCN: ; %bb.0:126; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)127; GCN-NEXT: v_min_i32_e32 v0, v0, v1128; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2129; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo130; GCN-NEXT: s_setpc_b64 s[30:31]131 %cmp1 = icmp slt i32 %arg1, %arg3132 %cmp2 = icmp slt i32 %arg2, %arg3133 %or = or i1 %cmp1, %cmp2134 ret i1 %or135}136 137define i1 @test10(i32 %arg1, i32 %arg2, i32 %arg3) {138; GCN-LABEL: test10:139; GCN: ; %bb.0:140; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)141; GCN-NEXT: v_min_u32_e32 v0, v0, v1142; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2143; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo144; GCN-NEXT: s_setpc_b64 s[30:31]145 %cmp1 = icmp ult i32 %arg1, %arg3146 %cmp2 = icmp ult i32 %arg2, %arg3147 %or = or i1 %cmp1, %cmp2148 ret i1 %or149}150 151define i1 @test11(i32 %arg1, i32 %arg2, i32 %arg3) {152; GCN-LABEL: test11:153; GCN: ; %bb.0:154; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)155; GCN-NEXT: v_min_i32_e32 v0, v0, v1156; GCN-NEXT: v_cmp_le_i32_e32 vcc_lo, v0, v2157; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo158; GCN-NEXT: s_setpc_b64 s[30:31]159 %cmp1 = icmp sle i32 %arg1, %arg3160 %cmp2 = icmp sle i32 %arg2, %arg3161 %or = or i1 %cmp1, %cmp2162 ret i1 %or163}164 165define i1 @test12(i32 %arg1, i32 %arg2, i32 %arg3) {166; GCN-LABEL: test12:167; GCN: ; %bb.0:168; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)169; GCN-NEXT: v_min_u32_e32 v0, v0, v1170; GCN-NEXT: v_cmp_le_u32_e32 vcc_lo, v0, v2171; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo172; GCN-NEXT: s_setpc_b64 s[30:31]173 %cmp1 = icmp ule i32 %arg1, %arg3174 %cmp2 = icmp ule i32 %arg2, %arg3175 %or = or i1 %cmp1, %cmp2176 ret i1 %or177}178 179define i1 @test13(i32 %arg1, i32 %arg2, i32 %arg3) {180; GCN-LABEL: test13:181; GCN: ; %bb.0:182; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)183; GCN-NEXT: v_max_i32_e32 v0, v0, v1184; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2185; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo186; GCN-NEXT: s_setpc_b64 s[30:31]187 %cmp1 = icmp sgt i32 %arg1, %arg3188 %cmp2 = icmp sgt i32 %arg2, %arg3189 %or = or i1 %cmp1, %cmp2190 ret i1 %or191}192 193define i1 @test14(i32 %arg1, i32 %arg2, i32 %arg3) {194; GCN-LABEL: test14:195; GCN: ; %bb.0:196; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)197; GCN-NEXT: v_max_u32_e32 v0, v0, v1198; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v2199; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo200; GCN-NEXT: s_setpc_b64 s[30:31]201 %cmp1 = icmp ugt i32 %arg1, %arg3202 %cmp2 = icmp ugt i32 %arg2, %arg3203 %or = or i1 %cmp1, %cmp2204 ret i1 %or205}206 207define i1 @test15(i32 %arg1, i32 %arg2, i32 %arg3) {208; GCN-LABEL: test15:209; GCN: ; %bb.0:210; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)211; GCN-NEXT: v_max_i32_e32 v0, v0, v1212; GCN-NEXT: v_cmp_ge_i32_e32 vcc_lo, v0, v2213; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo214; GCN-NEXT: s_setpc_b64 s[30:31]215 %cmp1 = icmp sge i32 %arg1, %arg3216 %cmp2 = icmp sge i32 %arg2, %arg3217 %or = or i1 %cmp1, %cmp2218 ret i1 %or219}220 221define i1 @test16(i32 %arg1, i32 %arg2, i32 %arg3) {222; GCN-LABEL: test16:223; GCN: ; %bb.0:224; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)225; GCN-NEXT: v_max_u32_e32 v0, v0, v1226; GCN-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v2227; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo228; GCN-NEXT: s_setpc_b64 s[30:31]229 %cmp1 = icmp uge i32 %arg1, %arg3230 %cmp2 = icmp uge i32 %arg2, %arg3231 %or = or i1 %cmp1, %cmp2232 ret i1 %or233}234 235define i1 @test17(i32 %arg1, i32 %arg2) {236; GCN-LABEL: test17:237; GCN: ; %bb.0:238; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)239; GCN-NEXT: v_max_i32_e32 v0, v0, v1240; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0x3e8, v0241; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo242; GCN-NEXT: s_setpc_b64 s[30:31]243 %cmp1 = icmp slt i32 %arg1, 1000244 %cmp2 = icmp slt i32 %arg2, 1000245 %and = and i1 %cmp1, %cmp2246 ret i1 %and247}248 249define i1 @test18(i32 %arg1, i32 %arg2) {250; GCN-LABEL: test18:251; GCN: ; %bb.0:252; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)253; GCN-NEXT: v_max_u32_e32 v0, v0, v1254; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x3e8, v0255; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo256; GCN-NEXT: s_setpc_b64 s[30:31]257 %cmp1 = icmp ult i32 %arg1, 1000258 %cmp2 = icmp ult i32 %arg2, 1000259 %and = and i1 %cmp1, %cmp2260 ret i1 %and261}262 263define i1 @test19(i32 %arg1, i32 %arg2) {264; GCN-LABEL: test19:265; GCN: ; %bb.0:266; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)267; GCN-NEXT: v_max_i32_e32 v0, v0, v1268; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0x3e9, v0269; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo270; GCN-NEXT: s_setpc_b64 s[30:31]271 %cmp1 = icmp sle i32 %arg1, 1000272 %cmp2 = icmp sle i32 %arg2, 1000273 %and = and i1 %cmp1, %cmp2274 ret i1 %and275}276 277define i1 @test20(i32 %arg1, i32 %arg2) {278; GCN-LABEL: test20:279; GCN: ; %bb.0:280; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)281; GCN-NEXT: v_max_u32_e32 v0, v0, v1282; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x3e9, v0283; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo284; GCN-NEXT: s_setpc_b64 s[30:31]285 %cmp1 = icmp ule i32 %arg1, 1000286 %cmp2 = icmp ule i32 %arg2, 1000287 %and = and i1 %cmp1, %cmp2288 ret i1 %and289}290 291define i1 @test21(i32 %arg1, i32 %arg2) {292; GCN-LABEL: test21:293; GCN: ; %bb.0:294; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)295; GCN-NEXT: v_min_i32_e32 v0, v0, v1296; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0x3e8, v0297; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo298; GCN-NEXT: s_setpc_b64 s[30:31]299 %cmp1 = icmp sgt i32 %arg1, 1000300 %cmp2 = icmp sgt i32 %arg2, 1000301 %and = and i1 %cmp1, %cmp2302 ret i1 %and303}304 305define i1 @test22(i32 %arg1, i32 %arg2) {306; GCN-LABEL: test22:307; GCN: ; %bb.0:308; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)309; GCN-NEXT: v_min_u32_e32 v0, v0, v1310; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3e8, v0311; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo312; GCN-NEXT: s_setpc_b64 s[30:31]313 %cmp1 = icmp ugt i32 %arg1, 1000314 %cmp2 = icmp ugt i32 %arg2, 1000315 %and = and i1 %cmp1, %cmp2316 ret i1 %and317}318 319define i1 @test23(i32 %arg1, i32 %arg2) {320; GCN-LABEL: test23:321; GCN: ; %bb.0:322; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)323; GCN-NEXT: v_min_i32_e32 v0, v0, v1324; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0x3e7, v0325; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo326; GCN-NEXT: s_setpc_b64 s[30:31]327 %cmp1 = icmp sge i32 %arg1, 1000328 %cmp2 = icmp sge i32 %arg2, 1000329 %and = and i1 %cmp1, %cmp2330 ret i1 %and331}332 333define i1 @test24(i32 %arg1, i32 %arg2) {334; GCN-LABEL: test24:335; GCN: ; %bb.0:336; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)337; GCN-NEXT: v_min_u32_e32 v0, v0, v1338; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3e7, v0339; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo340; GCN-NEXT: s_setpc_b64 s[30:31]341 %cmp1 = icmp uge i32 %arg1, 1000342 %cmp2 = icmp uge i32 %arg2, 1000343 %and = and i1 %cmp1, %cmp2344 ret i1 %and345}346 347define i1 @test25(i32 %arg1, i32 %arg2, i32 %arg3) {348; GCN-LABEL: test25:349; GCN: ; %bb.0:350; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)351; GCN-NEXT: v_max_i32_e32 v0, v0, v1352; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2353; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo354; GCN-NEXT: s_setpc_b64 s[30:31]355 %cmp1 = icmp slt i32 %arg1, %arg3356 %cmp2 = icmp slt i32 %arg2, %arg3357 %and = and i1 %cmp1, %cmp2358 ret i1 %and359}360 361define i1 @test26(i32 %arg1, i32 %arg2, i32 %arg3) {362; GCN-LABEL: test26:363; GCN: ; %bb.0:364; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)365; GCN-NEXT: v_max_u32_e32 v0, v0, v1366; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2367; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo368; GCN-NEXT: s_setpc_b64 s[30:31]369 %cmp1 = icmp ult i32 %arg1, %arg3370 %cmp2 = icmp ult i32 %arg2, %arg3371 %and = and i1 %cmp1, %cmp2372 ret i1 %and373}374 375define i1 @test27(i32 %arg1, i32 %arg2, i32 %arg3) {376; GCN-LABEL: test27:377; GCN: ; %bb.0:378; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)379; GCN-NEXT: v_max_i32_e32 v0, v0, v1380; GCN-NEXT: v_cmp_le_i32_e32 vcc_lo, v0, v2381; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo382; GCN-NEXT: s_setpc_b64 s[30:31]383 %cmp1 = icmp sle i32 %arg1, %arg3384 %cmp2 = icmp sle i32 %arg2, %arg3385 %and = and i1 %cmp1, %cmp2386 ret i1 %and387}388 389define i1 @test28(i32 %arg1, i32 %arg2, i32 %arg3) {390; GCN-LABEL: test28:391; GCN: ; %bb.0:392; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)393; GCN-NEXT: v_max_u32_e32 v0, v0, v1394; GCN-NEXT: v_cmp_le_u32_e32 vcc_lo, v0, v2395; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo396; GCN-NEXT: s_setpc_b64 s[30:31]397 %cmp1 = icmp ule i32 %arg1, %arg3398 %cmp2 = icmp ule i32 %arg2, %arg3399 %and = and i1 %cmp1, %cmp2400 ret i1 %and401}402 403define i1 @test29(i32 %arg1, i32 %arg2, i32 %arg3) {404; GCN-LABEL: test29:405; GCN: ; %bb.0:406; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)407; GCN-NEXT: v_min_i32_e32 v0, v0, v1408; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2409; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo410; GCN-NEXT: s_setpc_b64 s[30:31]411 %cmp1 = icmp sgt i32 %arg1, %arg3412 %cmp2 = icmp sgt i32 %arg2, %arg3413 %and = and i1 %cmp1, %cmp2414 ret i1 %and415}416 417define i1 @test30(i32 %arg1, i32 %arg2, i32 %arg3) {418; GCN-LABEL: test30:419; GCN: ; %bb.0:420; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)421; GCN-NEXT: v_min_u32_e32 v0, v0, v1422; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v2423; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo424; GCN-NEXT: s_setpc_b64 s[30:31]425 %cmp1 = icmp ugt i32 %arg1, %arg3426 %cmp2 = icmp ugt i32 %arg2, %arg3427 %and = and i1 %cmp1, %cmp2428 ret i1 %and429}430 431define i1 @test31(i32 %arg1, i32 %arg2, i32 %arg3) {432; GCN-LABEL: test31:433; GCN: ; %bb.0:434; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)435; GCN-NEXT: v_min_i32_e32 v0, v0, v1436; GCN-NEXT: v_cmp_ge_i32_e32 vcc_lo, v0, v2437; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo438; GCN-NEXT: s_setpc_b64 s[30:31]439 %cmp1 = icmp sge i32 %arg1, %arg3440 %cmp2 = icmp sge i32 %arg2, %arg3441 %and = and i1 %cmp1, %cmp2442 ret i1 %and443}444 445define i1 @test32(i32 %arg1, i32 %arg2, i32 %arg3) {446; GCN-LABEL: test32:447; GCN: ; %bb.0:448; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)449; GCN-NEXT: v_min_u32_e32 v0, v0, v1450; GCN-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v2451; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo452; GCN-NEXT: s_setpc_b64 s[30:31]453 %cmp1 = icmp uge i32 %arg1, %arg3454 %cmp2 = icmp uge i32 %arg2, %arg3455 %and = and i1 %cmp1, %cmp2456 ret i1 %and457}458 459define i1 @test33(i32 %arg1, i32 %arg2) {460; GCN-LABEL: test33:461; GCN: ; %bb.0:462; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)463; GCN-NEXT: v_max_i32_e32 v1, 0x3e8, v1464; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, v1, v0465; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo466; GCN-NEXT: s_setpc_b64 s[30:31]467 %cmp1 = icmp slt i32 %arg1, %arg2468 %cmp2 = icmp slt i32 %arg1, 1000469 %or = or i1 %cmp1, %cmp2470 ret i1 %or471}472 473define amdgpu_gfx void @test34(i32 inreg %arg1, i32 inreg %arg2) {474; GCN-LABEL: test34:475; GCN: ; %bb.0:476; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)477; GCN-NEXT: s_min_i32 s0, s4, s5478; GCN-NEXT: v_mov_b32_e32 v0, 0479; GCN-NEXT: s_cmpk_lt_i32 s0, 0x3e9480; GCN-NEXT: v_mov_b32_e32 v1, 0481; GCN-NEXT: s_cselect_b32 s0, -1, 0482; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0483; GCN-NEXT: global_store_b8 v[0:1], v2, off dlc484; GCN-NEXT: s_waitcnt_vscnt null, 0x0485; GCN-NEXT: s_setpc_b64 s[30:31]486 %cmp1 = icmp sle i32 %arg1, 1000487 %cmp2 = icmp sle i32 %arg2, 1000488 %or = or i1 %cmp1, %cmp2489 store volatile i1 %or, ptr addrspace(1) null490 ret void491}492 493define amdgpu_gfx void @test35(i32 inreg %arg1, i32 inreg %arg2) {494; GCN-LABEL: test35:495; GCN: ; %bb.0:496; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)497; GCN-NEXT: s_max_i32 s0, s4, s5498; GCN-NEXT: v_mov_b32_e32 v0, 0499; GCN-NEXT: s_cmpk_gt_i32 s0, 0x3e8500; GCN-NEXT: v_mov_b32_e32 v1, 0501; GCN-NEXT: s_cselect_b32 s0, -1, 0502; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0503; GCN-NEXT: global_store_b8 v[0:1], v2, off dlc504; GCN-NEXT: s_waitcnt_vscnt null, 0x0505; GCN-NEXT: s_setpc_b64 s[30:31]506 %cmp1 = icmp sgt i32 %arg1, 1000507 %cmp2 = icmp sgt i32 %arg2, 1000508 %or = or i1 %cmp1, %cmp2509 store volatile i1 %or, ptr addrspace(1) null510 ret void511}512 513define amdgpu_gfx void @test36(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3) {514; GCN-LABEL: test36:515; GCN: ; %bb.0:516; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)517; GCN-NEXT: s_min_u32 s0, s4, s5518; GCN-NEXT: v_mov_b32_e32 v0, 0519; GCN-NEXT: s_cmp_lt_u32 s0, s6520; GCN-NEXT: v_mov_b32_e32 v1, 0521; GCN-NEXT: s_cselect_b32 s0, -1, 0522; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0523; GCN-NEXT: global_store_b8 v[0:1], v2, off dlc524; GCN-NEXT: s_waitcnt_vscnt null, 0x0525; GCN-NEXT: s_setpc_b64 s[30:31]526 %cmp1 = icmp ult i32 %arg1, %arg3527 %cmp2 = icmp ult i32 %arg2, %arg3528 %or = or i1 %cmp1, %cmp2529 store volatile i1 %or, ptr addrspace(1) null530 ret void531}532 533define amdgpu_gfx void @test37(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3) {534; GCN-LABEL: test37:535; GCN: ; %bb.0:536; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)537; GCN-NEXT: s_max_i32 s0, s4, s5538; GCN-NEXT: v_mov_b32_e32 v0, 0539; GCN-NEXT: s_cmp_ge_i32 s0, s6540; GCN-NEXT: v_mov_b32_e32 v1, 0541; GCN-NEXT: s_cselect_b32 s0, -1, 0542; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0543; GCN-NEXT: global_store_b8 v[0:1], v2, off dlc544; GCN-NEXT: s_waitcnt_vscnt null, 0x0545; GCN-NEXT: s_setpc_b64 s[30:31]546 %cmp1 = icmp sge i32 %arg1, %arg3547 %cmp2 = icmp sge i32 %arg2, %arg3548 %or = or i1 %cmp1, %cmp2549 store volatile i1 %or, ptr addrspace(1) null550 ret void551}552 553define amdgpu_gfx void @test38(i32 inreg %arg1, i32 inreg %arg2) {554; GCN-LABEL: test38:555; GCN: ; %bb.0:556; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)557; GCN-NEXT: s_max_u32 s0, s4, s5558; GCN-NEXT: v_mov_b32_e32 v0, 0559; GCN-NEXT: s_cmpk_lt_u32 s0, 0x3e9560; GCN-NEXT: v_mov_b32_e32 v1, 0561; GCN-NEXT: s_cselect_b32 s0, -1, 0562; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0563; GCN-NEXT: global_store_b8 v[0:1], v2, off dlc564; GCN-NEXT: s_waitcnt_vscnt null, 0x0565; GCN-NEXT: s_setpc_b64 s[30:31]566 %cmp1 = icmp ule i32 %arg1, 1000567 %cmp2 = icmp ule i32 %arg2, 1000568 %and = and i1 %cmp1, %cmp2569 store volatile i1 %and, ptr addrspace(1) null570 ret void571}572 573define amdgpu_gfx void @test39(i32 inreg %arg1, i32 inreg %arg2) {574; GCN-LABEL: test39:575; GCN: ; %bb.0:576; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)577; GCN-NEXT: s_min_i32 s0, s4, s5578; GCN-NEXT: v_mov_b32_e32 v0, 0579; GCN-NEXT: s_cmpk_gt_i32 s0, 0x3e7580; GCN-NEXT: v_mov_b32_e32 v1, 0581; GCN-NEXT: s_cselect_b32 s0, -1, 0582; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0583; GCN-NEXT: global_store_b8 v[0:1], v2, off dlc584; GCN-NEXT: s_waitcnt_vscnt null, 0x0585; GCN-NEXT: s_setpc_b64 s[30:31]586 %cmp1 = icmp sge i32 %arg1, 1000587 %cmp2 = icmp sge i32 %arg2, 1000588 %and = and i1 %cmp1, %cmp2589 store volatile i1 %and, ptr addrspace(1) null590 ret void591}592 593define amdgpu_gfx void @test40(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3) {594; GCN-LABEL: test40:595; GCN: ; %bb.0:596; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)597; GCN-NEXT: s_max_i32 s0, s4, s5598; GCN-NEXT: v_mov_b32_e32 v0, 0599; GCN-NEXT: s_cmp_le_i32 s0, s6600; GCN-NEXT: v_mov_b32_e32 v1, 0601; GCN-NEXT: s_cselect_b32 s0, -1, 0602; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0603; GCN-NEXT: global_store_b8 v[0:1], v2, off dlc604; GCN-NEXT: s_waitcnt_vscnt null, 0x0605; GCN-NEXT: s_setpc_b64 s[30:31]606 %cmp1 = icmp sle i32 %arg1, %arg3607 %cmp2 = icmp sle i32 %arg2, %arg3608 %and = and i1 %cmp1, %cmp2609 store volatile i1 %and, ptr addrspace(1) null610 ret void611}612 613define amdgpu_gfx void @test41(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3) {614; GCN-LABEL: test41:615; GCN: ; %bb.0:616; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)617; GCN-NEXT: s_min_u32 s0, s4, s5618; GCN-NEXT: v_mov_b32_e32 v0, 0619; GCN-NEXT: s_cmp_ge_u32 s0, s6620; GCN-NEXT: v_mov_b32_e32 v1, 0621; GCN-NEXT: s_cselect_b32 s0, -1, 0622; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0623; GCN-NEXT: global_store_b8 v[0:1], v2, off dlc624; GCN-NEXT: s_waitcnt_vscnt null, 0x0625; GCN-NEXT: s_setpc_b64 s[30:31]626 %cmp1 = icmp uge i32 %arg1, %arg3627 %cmp2 = icmp uge i32 %arg2, %arg3628 %and = and i1 %cmp1, %cmp2629 store volatile i1 %and, ptr addrspace(1) null630 ret void631}632 633define i1 @test42(i32 %arg1, i32 %arg2, i32 %arg3) {634; GCN-LABEL: test42:635; GCN: ; %bb.0:636; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)637; GCN-NEXT: v_min_u32_e32 v0, v0, v1638; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v2639; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo640; GCN-NEXT: s_setpc_b64 s[30:31]641 %cmp1 = icmp ult i32 %arg3, %arg1642 %cmp2 = icmp ult i32 %arg3, %arg2643 %or = and i1 %cmp1, %cmp2644 ret i1 %or645}646 647define i1 @test43(i32 %arg1, i32 %arg2, i32 %arg3) {648; GCN-LABEL: test43:649; GCN: ; %bb.0:650; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)651; GCN-NEXT: v_max_u32_e32 v0, v0, v1652; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v2653; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo654; GCN-NEXT: s_setpc_b64 s[30:31]655 %cmp1 = icmp ult i32 %arg3, %arg1656 %cmp2 = icmp ult i32 %arg3, %arg2657 %or = or i1 %cmp1, %cmp2658 ret i1 %or659}660 661define i1 @test44(i32 %arg1, i32 %arg2, i32 %arg3) {662; GCN-LABEL: test44:663; GCN: ; %bb.0:664; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)665; GCN-NEXT: v_max_u32_e32 v0, v0, v1666; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2667; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo668; GCN-NEXT: s_setpc_b64 s[30:31]669 %cmp1 = icmp ugt i32 %arg3, %arg1670 %cmp2 = icmp ugt i32 %arg3, %arg2671 %or = and i1 %cmp1, %cmp2672 ret i1 %or673}674 675define i1 @test45(i32 %arg1, i32 %arg2, i32 %arg3) {676; GCN-LABEL: test45:677; GCN: ; %bb.0:678; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)679; GCN-NEXT: v_min_u32_e32 v0, v0, v1680; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2681; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo682; GCN-NEXT: s_setpc_b64 s[30:31]683 %cmp1 = icmp ugt i32 %arg3, %arg1684 %cmp2 = icmp ugt i32 %arg3, %arg2685 %or = or i1 %cmp1, %cmp2686 ret i1 %or687}688 689define i1 @test46(i32 %arg1, i32 %arg2, i32 %arg3) {690; GCN-LABEL: test46:691; GCN: ; %bb.0:692; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)693; GCN-NEXT: v_max_i32_e32 v0, v0, v1694; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2695; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo696; GCN-NEXT: s_setpc_b64 s[30:31]697 %cmp1 = icmp slt i32 %arg3, %arg1698 %cmp2 = icmp sgt i32 %arg2, %arg3699 %or = or i1 %cmp1, %cmp2700 ret i1 %or701}702 703define i1 @test47(i32 %arg1, i32 %arg2, i32 %arg3) {704; GCN-LABEL: test47:705; GCN: ; %bb.0:706; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)707; GCN-NEXT: v_max_i32_e32 v0, v0, v1708; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2709; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo710; GCN-NEXT: s_setpc_b64 s[30:31]711 %cmp1 = icmp sgt i32 %arg1, %arg3712 %cmp2 = icmp slt i32 %arg3, %arg2713 %or = or i1 %cmp1, %cmp2714 ret i1 %or715}716 717define i1 @test48(i32 %arg1, i32 %arg2, i32 %arg3) {718; GCN-LABEL: test48:719; GCN: ; %bb.0:720; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)721; GCN-NEXT: v_min_i32_e32 v0, v0, v1722; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2723; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo724; GCN-NEXT: s_setpc_b64 s[30:31]725 %cmp1 = icmp slt i32 %arg1, %arg3726 %cmp2 = icmp sgt i32 %arg3, %arg2727 %or = or i1 %cmp1, %cmp2728 ret i1 %or729}730 731define i1 @test49(i32 %arg1, i32 %arg2, i32 %arg3) {732; GCN-LABEL: test49:733; GCN: ; %bb.0:734; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)735; GCN-NEXT: v_min_i32_e32 v0, v0, v1736; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2737; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo738; GCN-NEXT: s_setpc_b64 s[30:31]739 %cmp1 = icmp sgt i32 %arg3, %arg1740 %cmp2 = icmp slt i32 %arg2, %arg3741 %or = or i1 %cmp1, %cmp2742 ret i1 %or743}744 745define i1 @test50(i32 %arg1, i32 %arg2, i32 %arg3) {746; GCN-LABEL: test50:747; GCN: ; %bb.0:748; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)749; GCN-NEXT: v_min_i32_e32 v0, v0, v1750; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2751; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo752; GCN-NEXT: s_setpc_b64 s[30:31]753 %cmp1 = icmp slt i32 %arg3, %arg1754 %cmp2 = icmp sgt i32 %arg2, %arg3755 %and = and i1 %cmp1, %cmp2756 ret i1 %and757}758 759define i1 @test51(i32 %arg1, i32 %arg2, i32 %arg3) {760; GCN-LABEL: test51:761; GCN: ; %bb.0:762; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)763; GCN-NEXT: v_min_i32_e32 v0, v0, v1764; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2765; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo766; GCN-NEXT: s_setpc_b64 s[30:31]767 %cmp1 = icmp sgt i32 %arg1, %arg3768 %cmp2 = icmp slt i32 %arg3, %arg2769 %and = and i1 %cmp1, %cmp2770 ret i1 %and771}772 773define i1 @test52(i32 %arg1, i32 %arg2, i32 %arg3) {774; GCN-LABEL: test52:775; GCN: ; %bb.0:776; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)777; GCN-NEXT: v_max_i32_e32 v0, v0, v1778; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2779; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo780; GCN-NEXT: s_setpc_b64 s[30:31]781 %cmp1 = icmp slt i32 %arg1, %arg3782 %cmp2 = icmp sgt i32 %arg3, %arg2783 %and = and i1 %cmp1, %cmp2784 ret i1 %and785}786 787define i1 @test53(i32 %arg1, i32 %arg2, i32 %arg3) {788; GCN-LABEL: test53:789; GCN: ; %bb.0:790; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)791; GCN-NEXT: v_max_i32_e32 v0, v0, v1792; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2793; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo794; GCN-NEXT: s_setpc_b64 s[30:31]795 %cmp1 = icmp sgt i32 %arg3, %arg1796 %cmp2 = icmp slt i32 %arg2, %arg3797 %and = and i1 %cmp1, %cmp2798 ret i1 %and799}800 801define i1 @test54(float %arg1, float %arg2, float %arg3) #0 {802; GCN-LABEL: test54:803; GCN: ; %bb.0:804; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)805; GCN-NEXT: v_min_f32_e32 v0, v0, v1806; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2807; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo808; GCN-NEXT: s_setpc_b64 s[30:31]809 %cmp1 = fcmp olt float %arg1, %arg3810 %cmp2 = fcmp olt float %arg2, %arg3811 %or1 = or i1 %cmp1, %cmp2812 ret i1 %or1813}814 815define i1 @test55(double %arg1, double %arg2, double %arg3) #0 {816; GCN-LABEL: test55:817; GCN: ; %bb.0:818; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)819; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]820; GCN-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]821; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo822; GCN-NEXT: s_setpc_b64 s[30:31]823 %cmp1 = fcmp ole double %arg1, %arg3824 %cmp2 = fcmp ole double %arg2, %arg3825 %or1 = or i1 %cmp1, %cmp2826 ret i1 %or1827}828 829define i1 @test56(double %arg1, double %arg2, double %arg3) #0 {830; GCN-LABEL: test56:831; GCN: ; %bb.0:832; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)833; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]834; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]835; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo836; GCN-NEXT: s_setpc_b64 s[30:31]837 %cmp1 = fcmp ogt double %arg1, %arg3838 %cmp2 = fcmp ogt double %arg2, %arg3839 %or1 = or i1 %cmp1, %cmp2840 ret i1 %or1841}842 843define i1 @test57(float %arg1, float %arg2, float %arg3) #0 {844; GCN-LABEL: test57:845; GCN: ; %bb.0:846; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)847; GCN-NEXT: v_max_f32_e32 v0, v0, v1848; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2849; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo850; GCN-NEXT: s_setpc_b64 s[30:31]851 %cmp1 = fcmp oge float %arg1, %arg3852 %cmp2 = fcmp oge float %arg2, %arg3853 %or1 = or i1 %cmp1, %cmp2854 ret i1 %or1855}856 857define i1 @test58(double %arg1, double %arg2, double %arg3) #0 {858; GFX11-LABEL: test58:859; GFX11: ; %bb.0:860; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)861; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]862; GFX11-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]863; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo864; GFX11-NEXT: s_setpc_b64 s[30:31]865;866; GFX11NONANS-LABEL: test58:867; GFX11NONANS: ; %bb.0:868; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)869; GFX11NONANS-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]870; GFX11NONANS-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]871; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo872; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]873 %cmp1 = fcmp ugt double %arg1, %arg3874 %cmp2 = fcmp ugt double %arg2, %arg3875 %and1 = and i1 %cmp1, %cmp2876 ret i1 %and1877}878 879define i1 @test59(float %arg1, float %arg2, float %arg3) #0 {880; GFX11-LABEL: test59:881; GFX11: ; %bb.0:882; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)883; GFX11-NEXT: v_min_f32_e32 v0, v0, v1884; GFX11-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v2885; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo886; GFX11-NEXT: s_setpc_b64 s[30:31]887;888; GFX11NONANS-LABEL: test59:889; GFX11NONANS: ; %bb.0:890; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)891; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v1892; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2893; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo894; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]895 %cmp1 = fcmp uge float %arg1, %arg3896 %cmp2 = fcmp uge float %arg2, %arg3897 %and1 = and i1 %cmp1, %cmp2898 ret i1 %and1899}900 901define i1 @test60(float %arg1, float %arg2, float %arg3) #0 {902; GFX11-LABEL: test60:903; GFX11: ; %bb.0:904; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)905; GFX11-NEXT: v_max_f32_e32 v0, v0, v1906; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2907; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo908; GFX11-NEXT: s_setpc_b64 s[30:31]909;910; GFX11NONANS-LABEL: test60:911; GFX11NONANS: ; %bb.0:912; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)913; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1914; GFX11NONANS-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2915; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo916; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]917 %cmp1 = fcmp ule float %arg1, %arg3918 %cmp2 = fcmp ule float %arg2, %arg3919 %and1 = and i1 %cmp1, %cmp2920 ret i1 %and1921}922 923define i1 @test61(double %arg1, double %arg2, double %arg3) #0 {924; GFX11-LABEL: test61:925; GFX11: ; %bb.0:926; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)927; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]928; GFX11-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]929; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo930; GFX11-NEXT: s_setpc_b64 s[30:31]931;932; GFX11NONANS-LABEL: test61:933; GFX11NONANS: ; %bb.0:934; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)935; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]936; GFX11NONANS-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]937; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo938; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]939 %cmp1 = fcmp ult double %arg1, %arg3940 %cmp2 = fcmp ult double %arg2, %arg3941 %and1 = and i1 %cmp1, %cmp2942 ret i1 %and1943}944 945define i1 @test62(float %arg1, float %arg2, float %arg3) {946; GCN-LABEL: test62:947; GCN: ; %bb.0:948; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)949; GCN-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1950; GCN-NEXT: v_min_f32_e32 v0, v0, v1951; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2952; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo953; GCN-NEXT: s_setpc_b64 s[30:31]954 %add1 = fadd nnan float %arg1, 1.0955 %add2 = fadd nnan float %arg2, 2.0956 %cmp1 = fcmp nnan olt float %add1, %arg3957 %cmp2 = fcmp nnan olt float %add2, %arg3958 %or1 = or i1 %cmp1, %cmp2959 ret i1 %or1960}961 962define i1 @test63(double %arg1, double %arg2, double %arg3) #0 {963; GCN-LABEL: test63:964; GCN: ; %bb.0:965; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)966; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0967; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 2.0968; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]969; GCN-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]970; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo971; GCN-NEXT: s_setpc_b64 s[30:31]972 %add1 = fadd nnan double %arg1, 1.0973 %add2 = fadd nnan double %arg2, 2.0974 %cmp1 = fcmp nnan ole double %add1, %arg3975 %cmp2 = fcmp nnan ole double %add2, %arg3976 %or1 = or i1 %cmp1, %cmp2977 ret i1 %or1978}979 980define i1 @test64(double %arg1, double %arg2, double %arg3) #0 {981; GCN-LABEL: test64:982; GCN: ; %bb.0:983; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)984; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0985; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 2.0986; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]987; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]988; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo989; GCN-NEXT: s_setpc_b64 s[30:31]990 %add1 = fadd nnan double %arg1, 1.0991 %add2 = fadd nnan double %arg2, 2.0992 %cmp1 = fcmp nnan ogt double %add1, %arg3993 %cmp2 = fcmp nnan ogt double %add2, %arg3994 %or1 = or i1 %cmp1, %cmp2995 ret i1 %or1996}997 998define i1 @test65(float %arg1, float %arg2, float %arg3) {999; GCN-LABEL: test65:1000; GCN: ; %bb.0:1001; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1002; GCN-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v11003; GCN-NEXT: v_max_f32_e32 v0, v0, v11004; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v21005; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1006; GCN-NEXT: s_setpc_b64 s[30:31]1007 %add1 = fadd nnan float %arg1, 1.01008 %add2 = fadd nnan float %arg2, 2.01009 %cmp1 = fcmp nnan oge float %add1, %arg31010 %cmp2 = fcmp nnan oge float %add2, %arg31011 %or1 = or i1 %cmp1, %cmp21012 ret i1 %or11013}1014 1015define i1 @test66(double %arg1, double %arg2, double %arg3) {1016; GCN-LABEL: test66:1017; GCN: ; %bb.0:1018; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1019; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.01020; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 2.01021; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]1022; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]1023; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1024; GCN-NEXT: s_setpc_b64 s[30:31]1025 %add1 = fadd nnan double %arg1, 1.01026 %add2 = fadd nnan double %arg2, 2.01027 %cmp1 = fcmp nnan ugt double %add1, %arg31028 %cmp2 = fcmp nnan ugt double %add2, %arg31029 %and1 = and i1 %cmp1, %cmp21030 ret i1 %and11031}1032 1033define i1 @test67(float %arg1, float %arg2, float %arg3) #0 {1034; GCN-LABEL: test67:1035; GCN: ; %bb.0:1036; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1037; GCN-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v11038; GCN-NEXT: v_min_f32_e32 v0, v0, v11039; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v21040; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1041; GCN-NEXT: s_setpc_b64 s[30:31]1042 %add1 = fadd nnan float %arg1, 1.01043 %add2 = fadd nnan float %arg2, 2.01044 %cmp1 = fcmp nnan uge float %add1, %arg31045 %cmp2 = fcmp nnan uge float %add2, %arg31046 %and1 = and i1 %cmp1, %cmp21047 ret i1 %and11048}1049 1050define i1 @test68(float %arg1, float %arg2, float %arg3) #0 {1051; GCN-LABEL: test68:1052; GCN: ; %bb.0:1053; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1054; GCN-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v11055; GCN-NEXT: v_max_f32_e32 v0, v0, v11056; GCN-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v21057; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1058; GCN-NEXT: s_setpc_b64 s[30:31]1059 %add1 = fadd nnan float %arg1, 1.01060 %add2 = fadd nnan float %arg2, 2.01061 %cmp1 = fcmp nnan ule float %add1, %arg31062 %cmp2 = fcmp nnan ule float %add2, %arg31063 %and1 = and i1 %cmp1, %cmp21064 ret i1 %and11065}1066 1067define i1 @test69(double %arg1, double %arg2, double %arg3) {1068; GCN-LABEL: test69:1069; GCN: ; %bb.0:1070; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1071; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.01072; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 2.01073; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]1074; GCN-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]1075; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1076; GCN-NEXT: s_setpc_b64 s[30:31]1077 %add1 = fadd nnan double %arg1, 1.01078 %add2 = fadd nnan double %arg2, 2.01079 %cmp1 = fcmp nnan ult double %add1, %arg31080 %cmp2 = fcmp nnan ult double %add2, %arg31081 %and1 = and i1 %cmp1, %cmp21082 ret i1 %and11083}1084 1085define i1 @test70(float %arg1, float %arg2, float %arg3) {1086; GFX11-LABEL: test70:1087; GFX11: ; %bb.0:1088; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1089; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v11090; GFX11-NEXT: v_min_f32_e32 v0, v0, v11091; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v21092; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1093; GFX11-NEXT: s_setpc_b64 s[30:31]1094;1095; GFX11NONANS-LABEL: test70:1096; GFX11NONANS: ; %bb.0:1097; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1098; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v11099; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v21100; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1101; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]1102 %var1 = call float @llvm.canonicalize.f32(float %arg1)1103 %var2 = call float @llvm.canonicalize.f32(float %arg2)1104 %cmp1 = fcmp olt float %var1, %arg31105 %cmp2 = fcmp olt float %var2, %arg31106 %or1 = or i1 %cmp1, %cmp21107 ret i1 %or11108}1109 1110define i1 @test71(double %arg1, double %arg2, double %arg3) {1111; GCN-LABEL: test71:1112; GCN: ; %bb.0:1113; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1114; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]1115; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]1116; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]1117; GCN-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]1118; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1119; GCN-NEXT: s_setpc_b64 s[30:31]1120 %var1 = call double @llvm.canonicalize.f64(double %arg1)1121 %var2 = call double @llvm.canonicalize.f64(double %arg2)1122 %cmp1 = fcmp ole double %var1, %arg31123 %cmp2 = fcmp ole double %var2, %arg31124 %or1 = or i1 %cmp1, %cmp21125 ret i1 %or11126}1127 1128define i1 @test72(double %arg1, double %arg2, double %arg3) {1129; GCN-LABEL: test72:1130; GCN: ; %bb.0:1131; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1132; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]1133; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]1134; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]1135; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]1136; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1137; GCN-NEXT: s_setpc_b64 s[30:31]1138 %var1 = call double @llvm.canonicalize.f64(double %arg1)1139 %var2 = call double @llvm.canonicalize.f64(double %arg2)1140 %cmp1 = fcmp ogt double %var1, %arg31141 %cmp2 = fcmp ogt double %var2, %arg31142 %or1 = or i1 %cmp1, %cmp21143 ret i1 %or11144}1145 1146define i1 @test73(float %arg1, float %arg2, float %arg3) {1147; GFX11-LABEL: test73:1148; GFX11: ; %bb.0:1149; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1150; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v11151; GFX11-NEXT: v_max_f32_e32 v0, v0, v11152; GFX11-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v21153; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1154; GFX11-NEXT: s_setpc_b64 s[30:31]1155;1156; GFX11NONANS-LABEL: test73:1157; GFX11NONANS: ; %bb.0:1158; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1159; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v11160; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v21161; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1162; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]1163 %var1 = call float @llvm.canonicalize.f32(float %arg1)1164 %var2 = call float @llvm.canonicalize.f32(float %arg2)1165 %cmp1 = fcmp oge float %var1, %arg31166 %cmp2 = fcmp oge float %var2, %arg31167 %or1 = or i1 %cmp1, %cmp21168 ret i1 %or11169}1170 1171define i1 @test74(double %arg1, double %arg2, double %arg3) {1172; GFX11-LABEL: test74:1173; GFX11: ; %bb.0:1174; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1175; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]1176; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]1177; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]1178; GFX11-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]1179; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1180; GFX11-NEXT: s_setpc_b64 s[30:31]1181;1182; GFX11NONANS-LABEL: test74:1183; GFX11NONANS: ; %bb.0:1184; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1185; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]1186; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]1187; GFX11NONANS-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]1188; GFX11NONANS-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]1189; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1190; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]1191 %var1 = call double @llvm.canonicalize.f64(double %arg1)1192 %var2 = call double @llvm.canonicalize.f64(double %arg2)1193 %cmp1 = fcmp ugt double %var1, %arg31194 %cmp2 = fcmp ugt double %var2, %arg31195 %and1 = and i1 %cmp1, %cmp21196 ret i1 %and11197}1198 1199define i1 @test75(float %arg1, float %arg2, float %arg3) {1200; GFX11-LABEL: test75:1201; GFX11: ; %bb.0:1202; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1203; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v11204; GFX11-NEXT: v_min_f32_e32 v0, v0, v11205; GFX11-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v21206; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1207; GFX11-NEXT: s_setpc_b64 s[30:31]1208;1209; GFX11NONANS-LABEL: test75:1210; GFX11NONANS: ; %bb.0:1211; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1212; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v11213; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v21214; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1215; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]1216 %var1 = call float @llvm.canonicalize.f32(float %arg1)1217 %var2 = call float @llvm.canonicalize.f32(float %arg2)1218 %cmp1 = fcmp uge float %var1, %arg31219 %cmp2 = fcmp uge float %var2, %arg31220 %and1 = and i1 %cmp1, %cmp21221 ret i1 %and11222}1223 1224define i1 @test76(float %arg1, float %arg2, float %arg3) {1225; GFX11-LABEL: test76:1226; GFX11: ; %bb.0:1227; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1228; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v11229; GFX11-NEXT: v_max_f32_e32 v0, v0, v11230; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v21231; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1232; GFX11-NEXT: s_setpc_b64 s[30:31]1233;1234; GFX11NONANS-LABEL: test76:1235; GFX11NONANS: ; %bb.0:1236; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1237; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v11238; GFX11NONANS-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v21239; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1240; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]1241 %var1 = call float @llvm.canonicalize.f32(float %arg1)1242 %var2 = call float @llvm.canonicalize.f32(float %arg2)1243 %cmp1 = fcmp ule float %var1, %arg31244 %cmp2 = fcmp ule float %var2, %arg31245 %and1 = and i1 %cmp1, %cmp21246 ret i1 %and11247}1248 1249define i1 @test77(double %arg1, double %arg2, double %arg3) {1250; GFX11-LABEL: test77:1251; GFX11: ; %bb.0:1252; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1253; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]1254; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]1255; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]1256; GFX11-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]1257; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1258; GFX11-NEXT: s_setpc_b64 s[30:31]1259;1260; GFX11NONANS-LABEL: test77:1261; GFX11NONANS: ; %bb.0:1262; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1263; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]1264; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]1265; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]1266; GFX11NONANS-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]1267; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1268; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]1269 %var1 = call double @llvm.canonicalize.f64(double %arg1)1270 %var2 = call double @llvm.canonicalize.f64(double %arg2)1271 %cmp1 = fcmp ult double %var1, %arg31272 %cmp2 = fcmp ult double %var2, %arg31273 %and1 = and i1 %cmp1, %cmp21274 ret i1 %and11275}1276 1277define i1 @test78(float %arg1, float %arg2, float %arg3) #0 {1278; GCN-LABEL: test78:1279; GCN: ; %bb.0:1280; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1281; GCN-NEXT: v_min_f32_e32 v0, v0, v11282; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v21283; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1284; GCN-NEXT: s_setpc_b64 s[30:31]1285 %cmp1 = fcmp olt float %arg1, %arg31286 %cmp2 = fcmp ogt float %arg3, %arg21287 %or1 = or i1 %cmp1, %cmp21288 ret i1 %or11289}1290 1291define i1 @test79(float %arg1, float %arg2, float %arg3) #0 {1292; GFX11-LABEL: test79:1293; GFX11: ; %bb.0:1294; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1295; GFX11-NEXT: v_max_f32_e32 v0, v0, v11296; GFX11-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v21297; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1298; GFX11-NEXT: s_setpc_b64 s[30:31]1299;1300; GFX11NONANS-LABEL: test79:1301; GFX11NONANS: ; %bb.0:1302; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1303; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v11304; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v21305; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1306; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]1307 %cmp1 = fcmp ult float %arg1, %arg31308 %cmp2 = fcmp ugt float %arg3, %arg21309 %and1 = and i1 %cmp1, %cmp21310 ret i1 %and11311}1312 1313define i1 @test80(float %arg1, float %arg2, float %arg3) {1314; GCN-LABEL: test80:1315; GCN: ; %bb.0:1316; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1317; GCN-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v11318; GCN-NEXT: v_max_f32_e32 v0, v0, v11319; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v21320; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1321; GCN-NEXT: s_setpc_b64 s[30:31]1322 %add1 = fadd nnan float %arg1, 1.01323 %add2 = fadd nnan float %arg2, 2.01324 %cmp1 = fcmp nnan oge float %add1, %arg31325 %cmp2 = fcmp nnan ole float %arg3, %add21326 %or1 = or i1 %cmp1, %cmp21327 ret i1 %or11328}1329 1330define i1 @test81(double %arg1, double %arg2, double %arg3) {1331; GCN-LABEL: test81:1332; GCN: ; %bb.0:1333; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1334; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.01335; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 2.01336; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]1337; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]1338; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1339; GCN-NEXT: s_setpc_b64 s[30:31]1340 %add1 = fadd nnan double %arg1, 1.01341 %add2 = fadd nnan double %arg2, 2.01342 %cmp1 = fcmp nnan ugt double %add1, %arg31343 %cmp2 = fcmp nnan ult double %arg3, %add21344 %and1 = and i1 %cmp1, %cmp21345 ret i1 %and11346}1347 1348define i1 @test82(double %arg1, double %arg2, double %arg3) {1349; GCN-LABEL: test82:1350; GCN: ; %bb.0:1351; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1352; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]1353; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]1354; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]1355; GCN-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]1356; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1357; GCN-NEXT: s_setpc_b64 s[30:31]1358 %var1 = call double @llvm.canonicalize.f64(double %arg1)1359 %var2 = call double @llvm.canonicalize.f64(double %arg2)1360 %cmp1 = fcmp ole double %var1, %arg31361 %cmp2 = fcmp oge double %arg3, %var21362 %or1 = or i1 %cmp1, %cmp21363 ret i1 %or11364}1365 1366define i1 @test83(float %arg1, float %arg2, float %arg3) {1367; GFX11-LABEL: test83:1368; GFX11: ; %bb.0:1369; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1370; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v11371; GFX11-NEXT: v_max_f32_e32 v0, v0, v11372; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v21373; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1374; GFX11-NEXT: s_setpc_b64 s[30:31]1375;1376; GFX11NONANS-LABEL: test83:1377; GFX11NONANS: ; %bb.0:1378; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1379; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v11380; GFX11NONANS-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v21381; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1382; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]1383 %var1 = call float @llvm.canonicalize.f32(float %arg1)1384 %var2 = call float @llvm.canonicalize.f32(float %arg2)1385 %cmp1 = fcmp ule float %var1, %arg31386 %cmp2 = fcmp uge float %arg3, %var21387 %and1 = and i1 %cmp1, %cmp21388 ret i1 %and11389}1390 1391define i1 @test84(half %arg1, half %arg2, half %arg3) {1392; GFX11-TRUE16-LABEL: test84:1393; GFX11-TRUE16: ; %bb.0:1394; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1395; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l1396; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.l1397; GFX11-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h1398; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0.l, v2.l1399; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1400; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1401;1402; GFX11-FAKE16-LABEL: test84:1403; GFX11-FAKE16: ; %bb.0:1404; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1405; GFX11-FAKE16-NEXT: v_max_f16_e32 v0, v0, v01406; GFX11-FAKE16-NEXT: v_max_f16_e32 v1, v1, v11407; GFX11-FAKE16-NEXT: v_min_f16_e32 v0, v0, v11408; GFX11-FAKE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0, v21409; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1410; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1411;1412; GCN-TRUE16-LABEL: test84:1413; GCN-TRUE16: ; %bb.0:1414; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1415; GCN-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v1.l1416; GCN-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0.l, v2.l1417; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1418; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31]1419;1420; GCN-FAKE16-LABEL: test84:1421; GCN-FAKE16: ; %bb.0:1422; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1423; GCN-FAKE16-NEXT: v_min_f16_e32 v0, v0, v11424; GCN-FAKE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0, v21425; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1426; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31]1427 %var1 = call half @llvm.canonicalize.f16(half %arg1)1428 %var2 = call half @llvm.canonicalize.f16(half %arg2)1429 %cmp1 = fcmp olt half %var1, %arg31430 %cmp2 = fcmp olt half %var2, %arg31431 %or1 = or i1 %cmp1, %cmp21432 ret i1 %or11433}1434 1435define <2 x i1> @test85(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {1436; GFX11-TRUE16-LABEL: test85:1437; GFX11-TRUE16: ; %bb.0:1438; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1439; GFX11-TRUE16-NEXT: v_pk_max_f16 v0, v0, v01440; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v1, v11441; GFX11-TRUE16-NEXT: v_pk_min_f16 v1, v0, v11442; GFX11-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v1.l, v2.l1443; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1444; GFX11-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v1.h, v2.h1445; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo1446; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1447;1448; GFX11-FAKE16-LABEL: test85:1449; GFX11-FAKE16: ; %bb.0:1450; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1451; GFX11-FAKE16-NEXT: v_pk_max_f16 v0, v0, v01452; GFX11-FAKE16-NEXT: v_pk_max_f16 v1, v1, v11453; GFX11-FAKE16-NEXT: v_pk_min_f16 v0, v0, v11454; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v21455; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v01456; GFX11-FAKE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0, v21457; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1458; GFX11-FAKE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v3, v11459; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo1460; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1461;1462; GCN-TRUE16-LABEL: test85:1463; GCN-TRUE16: ; %bb.0:1464; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1465; GCN-TRUE16-NEXT: v_pk_min_f16 v1, v0, v11466; GCN-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v1.l, v2.l1467; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1468; GCN-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v1.h, v2.h1469; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo1470; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31]1471;1472; GCN-FAKE16-LABEL: test85:1473; GCN-FAKE16: ; %bb.0:1474; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1475; GCN-FAKE16-NEXT: v_pk_min_f16 v0, v0, v11476; GCN-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v21477; GCN-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v01478; GCN-FAKE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0, v21479; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1480; GCN-FAKE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v3, v11481; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo1482; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31]1483 %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1)1484 %var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2)1485 %cmp1 = fcmp ole <2 x half> %var1, %arg31486 %cmp2 = fcmp ole <2 x half> %var2, %arg31487 %or1 = or <2 x i1> %cmp1, %cmp21488 ret <2 x i1> %or11489}1490 1491define <2 x i1> @test86(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {1492; GFX11-TRUE16-LABEL: test86:1493; GFX11-TRUE16: ; %bb.0:1494; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1495; GFX11-TRUE16-NEXT: v_pk_max_f16 v0, v0, v01496; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v1, v11497; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v0, v11498; GFX11-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1.l, v2.l1499; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1500; GFX11-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1.h, v2.h1501; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo1502; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1503;1504; GFX11-FAKE16-LABEL: test86:1505; GFX11-FAKE16: ; %bb.0:1506; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1507; GFX11-FAKE16-NEXT: v_pk_max_f16 v0, v0, v01508; GFX11-FAKE16-NEXT: v_pk_max_f16 v1, v1, v11509; GFX11-FAKE16-NEXT: v_pk_max_f16 v0, v0, v11510; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v21511; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v01512; GFX11-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0, v21513; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1514; GFX11-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v3, v11515; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo1516; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1517;1518; GCN-TRUE16-LABEL: test86:1519; GCN-TRUE16: ; %bb.0:1520; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1521; GCN-TRUE16-NEXT: v_pk_max_f16 v1, v0, v11522; GCN-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1.l, v2.l1523; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1524; GCN-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1.h, v2.h1525; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo1526; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31]1527;1528; GCN-FAKE16-LABEL: test86:1529; GCN-FAKE16: ; %bb.0:1530; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1531; GCN-FAKE16-NEXT: v_pk_max_f16 v0, v0, v11532; GCN-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v21533; GCN-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v01534; GCN-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0, v21535; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1536; GCN-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v3, v11537; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo1538; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31]1539 %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1)1540 %var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2)1541 %cmp1 = fcmp ogt <2 x half> %var1, %arg31542 %cmp2 = fcmp ogt <2 x half> %var2, %arg31543 %or1 = or <2 x i1> %cmp1, %cmp21544 ret <2 x i1> %or11545}1546 1547define i1 @test87(half %arg1, half %arg2, half %arg3) {1548; GFX11-TRUE16-LABEL: test87:1549; GFX11-TRUE16: ; %bb.0:1550; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1551; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l1552; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.l1553; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h1554; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0.l, v2.l1555; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1556; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1557;1558; GFX11-FAKE16-LABEL: test87:1559; GFX11-FAKE16: ; %bb.0:1560; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1561; GFX11-FAKE16-NEXT: v_max_f16_e32 v0, v0, v01562; GFX11-FAKE16-NEXT: v_max_f16_e32 v1, v1, v11563; GFX11-FAKE16-NEXT: v_max_f16_e32 v0, v0, v11564; GFX11-FAKE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0, v21565; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1566; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1567;1568; GCN-TRUE16-LABEL: test87:1569; GCN-TRUE16: ; %bb.0:1570; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1571; GCN-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v1.l1572; GCN-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0.l, v2.l1573; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1574; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31]1575;1576; GCN-FAKE16-LABEL: test87:1577; GCN-FAKE16: ; %bb.0:1578; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1579; GCN-FAKE16-NEXT: v_max_f16_e32 v0, v0, v11580; GCN-FAKE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0, v21581; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1582; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31]1583 %var1 = call half @llvm.canonicalize.f16(half %arg1)1584 %var2 = call half @llvm.canonicalize.f16(half %arg2)1585 %cmp1 = fcmp oge half %var1, %arg31586 %cmp2 = fcmp oge half %var2, %arg31587 %or1 = or i1 %cmp1, %cmp21588 ret i1 %or11589}1590 1591define <2 x i1> @test88(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {1592; GFX11-TRUE16-LABEL: test88:1593; GFX11-TRUE16: ; %bb.0:1594; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1595; GFX11-TRUE16-NEXT: v_pk_max_f16 v0, v0, v01596; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v1, v11597; GFX11-TRUE16-NEXT: v_pk_min_f16 v1, v0, v11598; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1.l, v2.l1599; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1600; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1.h, v2.h1601; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo1602; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1603;1604; GFX11-FAKE16-LABEL: test88:1605; GFX11-FAKE16: ; %bb.0:1606; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1607; GFX11-FAKE16-NEXT: v_pk_max_f16 v0, v0, v01608; GFX11-FAKE16-NEXT: v_pk_max_f16 v1, v1, v11609; GFX11-FAKE16-NEXT: v_pk_min_f16 v0, v0, v11610; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v21611; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v01612; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v21613; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1614; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v3, v11615; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo1616; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1617;1618; GCN-TRUE16-LABEL: test88:1619; GCN-TRUE16: ; %bb.0:1620; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1621; GCN-TRUE16-NEXT: v_pk_min_f16 v1, v0, v11622; GCN-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1.l, v2.l1623; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1624; GCN-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1.h, v2.h1625; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo1626; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31]1627;1628; GCN-FAKE16-LABEL: test88:1629; GCN-FAKE16: ; %bb.0:1630; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1631; GCN-FAKE16-NEXT: v_pk_min_f16 v0, v0, v11632; GCN-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v21633; GCN-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v01634; GCN-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0, v21635; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1636; GCN-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v3, v11637; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo1638; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31]1639 %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1)1640 %var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2)1641 %cmp1 = fcmp ugt <2 x half> %var1, %arg31642 %cmp2 = fcmp ugt <2 x half> %var2, %arg31643 %and1 = and <2 x i1> %cmp1, %cmp21644 ret <2 x i1> %and11645}1646 1647define i1 @test89(half %arg1, half %arg2, half %arg3) {1648; GFX11-TRUE16-LABEL: test89:1649; GFX11-TRUE16: ; %bb.0:1650; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1651; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l1652; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.l1653; GFX11-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h1654; GFX11-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v2.l1655; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1656; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1657;1658; GFX11-FAKE16-LABEL: test89:1659; GFX11-FAKE16: ; %bb.0:1660; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1661; GFX11-FAKE16-NEXT: v_max_f16_e32 v0, v0, v01662; GFX11-FAKE16-NEXT: v_max_f16_e32 v1, v1, v11663; GFX11-FAKE16-NEXT: v_min_f16_e32 v0, v0, v11664; GFX11-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v21665; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1666; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1667;1668; GCN-TRUE16-LABEL: test89:1669; GCN-TRUE16: ; %bb.0:1670; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1671; GCN-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v1.l1672; GCN-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0.l, v2.l1673; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1674; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31]1675;1676; GCN-FAKE16-LABEL: test89:1677; GCN-FAKE16: ; %bb.0:1678; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1679; GCN-FAKE16-NEXT: v_min_f16_e32 v0, v0, v11680; GCN-FAKE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0, v21681; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1682; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31]1683 %var1 = call half @llvm.canonicalize.f16(half %arg1)1684 %var2 = call half @llvm.canonicalize.f16(half %arg2)1685 %cmp1 = fcmp uge half %var1, %arg31686 %cmp2 = fcmp uge half %var2, %arg31687 %and1 = and i1 %cmp1, %cmp21688 ret i1 %and11689}1690 1691define i1 @test90(half %arg1, half %arg2, half %arg3) {1692; GFX11-TRUE16-LABEL: test90:1693; GFX11-TRUE16: ; %bb.0:1694; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1695; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l1696; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.l1697; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h1698; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v2.l1699; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1700; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1701;1702; GFX11-FAKE16-LABEL: test90:1703; GFX11-FAKE16: ; %bb.0:1704; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1705; GFX11-FAKE16-NEXT: v_max_f16_e32 v0, v0, v01706; GFX11-FAKE16-NEXT: v_max_f16_e32 v1, v1, v11707; GFX11-FAKE16-NEXT: v_max_f16_e32 v0, v0, v11708; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v21709; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1710; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1711;1712; GCN-TRUE16-LABEL: test90:1713; GCN-TRUE16: ; %bb.0:1714; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1715; GCN-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v1.l1716; GCN-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0.l, v2.l1717; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1718; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31]1719;1720; GCN-FAKE16-LABEL: test90:1721; GCN-FAKE16: ; %bb.0:1722; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1723; GCN-FAKE16-NEXT: v_max_f16_e32 v0, v0, v11724; GCN-FAKE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0, v21725; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1726; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31]1727 %var1 = call half @llvm.canonicalize.f16(half %arg1)1728 %var2 = call half @llvm.canonicalize.f16(half %arg2)1729 %cmp1 = fcmp ule half %var1, %arg31730 %cmp2 = fcmp ule half %var2, %arg31731 %and1 = and i1 %cmp1, %cmp21732 ret i1 %and11733}1734 1735define <2 x i1> @test91(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {1736; GFX11-TRUE16-LABEL: test91:1737; GFX11-TRUE16: ; %bb.0:1738; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1739; GFX11-TRUE16-NEXT: v_pk_max_f16 v0, v0, v01740; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v1, v11741; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v0, v11742; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v1.l, v2.l1743; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1744; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v1.h, v2.h1745; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo1746; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1747;1748; GFX11-FAKE16-LABEL: test91:1749; GFX11-FAKE16: ; %bb.0:1750; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1751; GFX11-FAKE16-NEXT: v_pk_max_f16 v0, v0, v01752; GFX11-FAKE16-NEXT: v_pk_max_f16 v1, v1, v11753; GFX11-FAKE16-NEXT: v_pk_max_f16 v0, v0, v11754; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v21755; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v01756; GFX11-FAKE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v0, v21757; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1758; GFX11-FAKE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v3, v11759; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo1760; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1761;1762; GCN-TRUE16-LABEL: test91:1763; GCN-TRUE16: ; %bb.0:1764; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1765; GCN-TRUE16-NEXT: v_pk_max_f16 v1, v0, v11766; GCN-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v1.l, v2.l1767; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1768; GCN-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v1.h, v2.h1769; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo1770; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31]1771;1772; GCN-FAKE16-LABEL: test91:1773; GCN-FAKE16: ; %bb.0:1774; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1775; GCN-FAKE16-NEXT: v_pk_max_f16 v0, v0, v11776; GCN-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v21777; GCN-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v01778; GCN-FAKE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0, v21779; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1780; GCN-FAKE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v3, v11781; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo1782; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31]1783 %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1)1784 %var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2)1785 %cmp1 = fcmp ult <2 x half> %var1, %arg31786 %cmp2 = fcmp ult <2 x half> %var2, %arg31787 %and1 = and <2 x i1> %cmp1, %cmp21788 ret <2 x i1> %and11789}1790 1791define i1 @test92(i32 %arg1, i32 %arg2, i32 %arg3, i32 %C) {1792; GCN-LABEL: test92:1793; GCN: ; %bb.0:1794; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1795; GCN-NEXT: v_min3_u32 v0, v0, v1, v21796; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v31797; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1798; GCN-NEXT: s_setpc_b64 s[30:31]1799 %cmp1 = icmp ult i32 %arg1, %C1800 %cmp2 = icmp ult i32 %arg2, %C1801 %cmp3 = icmp ult i32 %arg3, %C1802 %or1 = or i1 %cmp1, %cmp21803 %or2 = or i1 %or1, %cmp31804 ret i1 %or21805}1806 1807define i1 @test93(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {1808; GCN-LABEL: test93:1809; GCN: ; %bb.0:1810; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1811; GCN-NEXT: v_min_u32_e32 v0, v0, v11812; GCN-NEXT: v_max_u32_e32 v1, v2, v31813; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v41814; GCN-NEXT: v_cmp_gt_u32_e64 s0, v1, v41815; GCN-NEXT: s_or_b32 s0, vcc_lo, s01816; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s01817; GCN-NEXT: s_setpc_b64 s[30:31]1818 %cmp1 = icmp ult i32 %arg1, %C1819 %cmp2 = icmp ult i32 %arg2, %C1820 %cmp3 = icmp ugt i32 %arg3, %C1821 %cmp4 = icmp ugt i32 %arg4, %C1822 %or1 = or i1 %cmp1, %cmp21823 %or2 = or i1 %cmp3, %cmp41824 %or3 = or i1 %or1, %or21825 ret i1 %or31826}1827 1828define i1 @test94(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %C) {1829; GCN-LABEL: test94:1830; GCN: ; %bb.0:1831; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1832; GCN-NEXT: v_min_u32_e32 v2, v2, v31833; GCN-NEXT: v_min3_u32 v0, v0, v1, v21834; GCN-NEXT: v_min_u32_e32 v0, v0, v41835; GCN-NEXT: v_min3_u32 v0, v5, v6, v01836; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v81837; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1838; GCN-NEXT: s_setpc_b64 s[30:31]1839 %cmp1 = icmp ult i32 %arg1, %C1840 %cmp2 = icmp ult i32 %arg2, %C1841 %or1 = or i1 %cmp1, %cmp21842 %cmp3 = icmp ult i32 %arg3, %C1843 %cmp4 = icmp ult i32 %arg4, %C1844 %or2 = or i1 %cmp3, %cmp41845 %cmp5 = icmp ult i32 %arg5, %C1846 %or3 = or i1 %or1, %or21847 %or4 = or i1 %or3, %cmp51848 %cmp6 = icmp ult i32 %arg6, %C1849 %cmp7 = icmp ult i32 %arg7, %C1850 %or5 = or i1 %cmp6, %cmp71851 %cmp8 = icmp ult i32 %arg8, %C1852 %or6 = or i1 %or5, %or41853 %or7 = or i1 %or6, %cmp81854 ret i1 %or61855}1856 1857define i1 @test95(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {1858; GCN-LABEL: test95:1859; GCN: ; %bb.0:1860; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1861; GCN-NEXT: v_maxmin_u32 v0, v0, v1, v21862; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v41863; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1864; GCN-NEXT: s_setpc_b64 s[30:31]1865 %cmp1 = icmp ult i32 %arg1, %C1866 %cmp2 = icmp ult i32 %arg2, %C1867 %cmp3 = icmp ult i32 %arg3, %C1868 %and1 = and i1 %cmp1, %cmp21869 %or1 = or i1 %and1, %cmp31870 ret i1 %or11871}1872 1873define i1 @test96(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {1874; GCN-LABEL: test96:1875; GCN: ; %bb.0:1876; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1877; GCN-NEXT: v_minmax_u32 v0, v0, v1, v21878; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v41879; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1880; GCN-NEXT: s_setpc_b64 s[30:31]1881 %cmp1 = icmp ult i32 %arg1, %C1882 %cmp2 = icmp ult i32 %arg2, %C1883 %cmp3 = icmp ult i32 %arg3, %C1884 %and1 = or i1 %cmp1, %cmp21885 %or1 = and i1 %and1, %cmp31886 ret i1 %or11887}1888 1889define i1 @test97(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {1890; GCN-LABEL: test97:1891; GCN: ; %bb.0:1892; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1893; GCN-NEXT: v_min_u32_e32 v0, v0, v11894; GCN-NEXT: v_max3_u32 v0, v0, v2, v31895; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v41896; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1897; GCN-NEXT: s_setpc_b64 s[30:31]1898 %cmp1 = icmp ult i32 %arg1, %C1899 %cmp2 = icmp ult i32 %arg2, %C1900 %cmp3 = icmp ult i32 %arg3, %C1901 %cmp4 = icmp ult i32 %arg4, %C1902 %or1 = or i1 %cmp1, %cmp21903 %and1 = and i1 %cmp3, %cmp41904 %and2 = and i1 %or1, %and11905 ret i1 %and21906}1907 1908define i1 @test98(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {1909; GCN-LABEL: test98:1910; GCN: ; %bb.0:1911; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1912; GCN-NEXT: v_min_u32_e32 v2, v2, v31913; GCN-NEXT: v_minmax_u32 v0, v0, v1, v21914; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v41915; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1916; GCN-NEXT: s_setpc_b64 s[30:31]1917 %cmp1 = icmp ult i32 %arg1, %C1918 %cmp2 = icmp ult i32 %arg2, %C1919 %cmp3 = icmp ult i32 %arg3, %C1920 %cmp4 = icmp ult i32 %arg4, %C1921 %or1 = or i1 %cmp1, %cmp21922 %or2 = or i1 %cmp3, %cmp41923 %and1 = and i1 %or1, %or21924 ret i1 %and11925}1926 1927define i1 @test99(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {1928; GCN-LABEL: test99:1929; GCN: ; %bb.0:1930; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1931; GCN-NEXT: v_max_u32_e32 v2, v2, v31932; GCN-NEXT: v_min3_u32 v0, v0, v1, v21933; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v41934; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1935; GCN-NEXT: s_setpc_b64 s[30:31]1936 %cmp1 = icmp ult i32 %arg1, %C1937 %cmp2 = icmp ult i32 %arg2, %C1938 %cmp3 = icmp ult i32 %arg3, %C1939 %cmp4 = icmp ult i32 %arg4, %C1940 %or1 = or i1 %cmp1, %cmp21941 %and1 = and i1 %cmp3, %cmp41942 %or2 = or i1 %or1, %and11943 ret i1 %or21944}1945 1946define i1 @test100(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {1947; GCN-LABEL: test100:1948; GCN: ; %bb.0:1949; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1950; GCN-NEXT: v_max_u32_e32 v2, v2, v31951; GCN-NEXT: v_maxmin_u32 v0, v0, v1, v21952; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v41953; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1954; GCN-NEXT: s_setpc_b64 s[30:31]1955 %cmp1 = icmp ult i32 %arg1, %C1956 %cmp2 = icmp ult i32 %arg2, %C1957 %cmp3 = icmp ult i32 %arg3, %C1958 %cmp4 = icmp ult i32 %arg4, %C1959 %and1 = and i1 %cmp1, %cmp21960 %and2 = and i1 %cmp3, %cmp41961 %or1 = or i1 %and1, %and21962 ret i1 %or11963}1964 1965define i1 @test101(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %C) {1966; GCN-LABEL: test101:1967; GCN: ; %bb.0:1968; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1969; GCN-NEXT: v_max_u32_e32 v0, v0, v11970; GCN-NEXT: v_minmax_u32 v1, v3, v4, v51971; GCN-NEXT: v_min3_u32 v0, v0, v2, v11972; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v61973; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1974; GCN-NEXT: s_setpc_b64 s[30:31]1975 %cmp1 = icmp ult i32 %arg1, %C1976 %cmp2 = icmp ult i32 %arg2, %C1977 %cmp3 = icmp ult i32 %arg3, %C1978 %and1 = and i1 %cmp1, %cmp21979 %or1 = or i1 %and1, %cmp31980 %cmp4 = icmp ult i32 %arg4, %C1981 %cmp5 = icmp ult i32 %arg5, %C1982 %cmp6 = icmp ult i32 %arg6, %C1983 %or2 = or i1 %cmp4, %cmp51984 %and2 = and i1 %or2, %cmp61985 %or3 = or i1 %or1, %and21986 ret i1 %or31987}1988 1989define i1 @test102(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %C) {1990; GCN-LABEL: test102:1991; GCN: ; %bb.0:1992; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1993; GCN-NEXT: v_max_u32_e32 v0, v0, v11994; GCN-NEXT: v_min_u32_e32 v1, v2, v31995; GCN-NEXT: v_min3_u32 v0, v0, v5, v11996; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v61997; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1998; GCN-NEXT: s_setpc_b64 s[30:31]1999 %cmp1 = icmp ult i32 %arg1, %C2000 %cmp2 = icmp ult i32 %arg2, %C2001 %cmp3 = icmp ult i32 %arg3, %C2002 %cmp4 = icmp ult i32 %arg4, %C2003 %cmp5 = icmp ult i32 %arg5, %C2004 %cmp6 = icmp ult i32 %arg6, %C2005 %and1 = and i1 %cmp1, %cmp22006 %or1 = or i1 %cmp3, %cmp42007 %and2 = and i1 %cmp4, %cmp52008 %or2 = or i1 %and1, %cmp62009 %or3 = or i1 %or1, %and22010 %or4 = or i1 %or2, %or32011 ret i1 %or42012}2013 2014define i1 @test103(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %C) {2015; GCN-LABEL: test103:2016; GCN: ; %bb.0:2017; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2018; GCN-NEXT: v_max_u32_e32 v4, v4, v52019; GCN-NEXT: v_max_u32_e32 v2, v2, v32020; GCN-NEXT: v_maxmin_u32 v0, v0, v1, v42021; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, v2, v62022; GCN-NEXT: v_cmp_lt_u32_e64 s0, v0, v62023; GCN-NEXT: s_or_b32 s0, s0, vcc_lo2024; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02025; GCN-NEXT: s_setpc_b64 s[30:31]2026 %cmp1 = icmp ult i32 %arg1, %C2027 %cmp2 = icmp ult i32 %arg2, %C2028 %cmp3 = icmp ugt i32 %arg3, %C2029 %cmp4 = icmp ugt i32 %arg4, %C2030 %cmp5 = icmp ult i32 %arg5, %C2031 %cmp6 = icmp ult i32 %arg6, %C2032 %and1 = and i1 %cmp1, %cmp22033 %or1 = or i1 %cmp3, %cmp42034 %and2 = and i1 %cmp5, %cmp62035 %or2 = or i1 %and1, %or12036 %or3 = or i1 %or2, %and22037 ret i1 %or32038}2039 2040 2041define i1 @test104(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %C) {2042; GCN-LABEL: test104:2043; GCN: ; %bb.0:2044; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2045; GCN-NEXT: v_min_u32_e32 v8, v8, v92046; GCN-NEXT: v_max_u32_e32 v2, v2, v32047; GCN-NEXT: v_min_u32_e32 v3, v4, v52048; GCN-NEXT: v_max_u32_e32 v4, v6, v72049; GCN-NEXT: v_min3_u32 v0, v0, v1, v82050; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, v2, v102051; GCN-NEXT: v_cmp_lt_u32_e64 s0, v3, v102052; GCN-NEXT: v_cmp_gt_u32_e64 s1, v4, v102053; GCN-NEXT: v_cmp_lt_u32_e64 s2, v0, v102054; GCN-NEXT: s_or_b32 s0, s0, s12055; GCN-NEXT: s_or_b32 s1, s2, vcc_lo2056; GCN-NEXT: s_or_b32 s0, s0, s12057; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02058; GCN-NEXT: s_setpc_b64 s[30:31]2059 %cmp1 = icmp ult i32 %arg1, %C2060 %cmp2 = icmp ult i32 %arg2, %C2061 %cmp3 = icmp ugt i32 %arg3, %C2062 %cmp4 = icmp ugt i32 %arg4, %C2063 %cmp5 = icmp ult i32 %arg5, %C2064 %cmp6 = icmp ult i32 %arg6, %C2065 %cmp7 = icmp ugt i32 %arg7, %C2066 %cmp8 = icmp ugt i32 %arg8, %C2067 %cmp9 = icmp ult i32 %arg9, %C2068 %cmp10 = icmp ult i32 %arg10, %C2069 %or1 = or i1 %cmp1, %cmp22070 %or2 = or i1 %cmp3, %cmp42071 %or3 = or i1 %cmp5, %cmp62072 %or4 = or i1 %cmp7, %cmp82073 %or5 = or i1 %cmp9, %cmp102074 %or6 = or i1 %or1, %or22075 %or7 = or i1 %or3, %or42076 %or8 = or i1 %or5, %or62077 %or9 = or i1 %or7, %or82078 ret i1 %or92079}2080 2081define i1 @test105(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %C) {2082; GCN-LABEL: test105:2083; GCN: ; %bb.0:2084; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2085; GCN-NEXT: v_max_u32_e32 v0, v0, v12086; GCN-NEXT: v_max_u32_e32 v1, v2, v32087; GCN-NEXT: v_max_u32_e32 v2, v4, v52088; GCN-NEXT: v_max_u32_e32 v3, v6, v72089; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v102090; GCN-NEXT: v_cmp_gt_u32_e64 s0, v1, v102091; GCN-NEXT: v_cmp_lt_u32_e64 s1, v2, v102092; GCN-NEXT: v_cmp_gt_u32_e64 s2, v3, v102093; GCN-NEXT: s_and_b32 s0, vcc_lo, s02094; GCN-NEXT: s_or_b32 s1, s2, s12095; GCN-NEXT: s_and_b32 s0, s0, s12096; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02097; GCN-NEXT: s_setpc_b64 s[30:31]2098 %cmp1 = icmp ult i32 %arg1, %C2099 %cmp2 = icmp ult i32 %arg2, %C2100 %cmp3 = icmp ugt i32 %arg3, %C2101 %cmp4 = icmp ugt i32 %arg4, %C2102 %cmp5 = icmp ult i32 %arg5, %C2103 %cmp6 = icmp ult i32 %arg6, %C2104 %cmp7 = icmp ugt i32 %arg7, %C2105 %cmp8 = icmp ugt i32 %arg8, %C2106 %and1 = and i1 %cmp1, %cmp22107 %or1 = or i1 %cmp3, %cmp42108 %and2 = and i1 %cmp5, %cmp62109 %or2 = or i1 %cmp7, %cmp82110 %and3 = and i1 %and1, %or12111 %or3 = or i1 %or2, %and22112 %or4 = and i1 %and3, %or32113 ret i1 %or42114}2115 2116define i1 @test106(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %C1, i32 %C2) {2117; GCN-LABEL: test106:2118; GCN: ; %bb.0:2119; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2120; GCN-NEXT: v_min_u32_e32 v6, v6, v72121; GCN-NEXT: v_min_u32_e32 v0, v0, v12122; GCN-NEXT: v_min_u32_e32 v1, v10, v112123; GCN-NEXT: v_min_u32_e32 v2, v2, v32124; GCN-NEXT: v_min3_u32 v3, v4, v5, v62125; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v122126; GCN-NEXT: v_min3_u32 v0, v8, v9, v12127; GCN-NEXT: v_cmp_lt_u32_e64 s0, v2, v132128; GCN-NEXT: v_cmp_lt_u32_e64 s1, v3, v132129; GCN-NEXT: v_cmp_lt_u32_e64 s2, v0, v122130; GCN-NEXT: s_or_b32 s0, vcc_lo, s02131; GCN-NEXT: s_or_b32 s0, s0, s12132; GCN-NEXT: s_or_b32 s0, s2, s02133; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02134; GCN-NEXT: s_setpc_b64 s[30:31]2135 %cmp1 = icmp ult i32 %arg1, %C12136 %cmp2 = icmp ult i32 %arg2, %C12137 %cmp3 = icmp ult i32 %arg3, %C22138 %cmp4 = icmp ult i32 %arg4, %C22139 %cmp5 = icmp ult i32 %arg5, %C22140 %cmp6 = icmp ult i32 %arg6, %C22141 %cmp7 = icmp ult i32 %arg7, %C22142 %cmp8 = icmp ult i32 %arg8, %C22143 %cmp9 = icmp ult i32 %arg9, %C12144 %cmp10 = icmp ult i32 %arg10, %C12145 %cmp11 = icmp ult i32 %arg11, %C12146 %cmp12 = icmp ult i32 %arg12, %C12147 %or1 = or i1 %cmp1, %cmp22148 %or2 = or i1 %cmp3, %cmp42149 %or3 = or i1 %cmp5, %cmp62150 %or4 = or i1 %cmp7, %cmp82151 %or5 = or i1 %cmp9, %cmp102152 %or6 = or i1 %cmp11, %cmp122153 %or7 = or i1 %or1, %or22154 %or8 = or i1 %or3, %or42155 %or9 = or i1 %or5, %or62156 %or10 = or i1 %or7, %or82157 %or11 = or i1 %or9, %or102158 ret i1 %or112159}2160 2161define i1 @test107(float %arg1, float %arg2, float %arg3, float %C) {2162; GCN-LABEL: test107:2163; GCN: ; %bb.0:2164; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2165; GCN-NEXT: v_min3_f32 v0, v0, v1, v22166; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v32167; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo2168; GCN-NEXT: s_setpc_b64 s[30:31]2169 %cmp1 = fcmp olt float %arg1, %C2170 %cmp2 = fcmp olt float %arg2, %C2171 %cmp3 = fcmp olt float %arg3, %C2172 %or1 = or i1 %cmp1, %cmp22173 %or2 = or i1 %or1, %cmp32174 ret i1 %or22175}2176 2177define i1 @test108(float %arg1, float %arg2, float %arg3, float %C) {2178; GFX11-LABEL: test108:2179; GFX11: ; %bb.0:2180; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2181; GFX11-NEXT: v_max3_f32 v0, v0, v1, v22182; GFX11-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v32183; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo2184; GFX11-NEXT: s_setpc_b64 s[30:31]2185;2186; GFX11NONANS-LABEL: test108:2187; GFX11NONANS: ; %bb.0:2188; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2189; GFX11NONANS-NEXT: v_max3_f32 v0, v0, v1, v22190; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v32191; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo2192; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]2193 %cmp1 = fcmp ult float %arg1, %C2194 %cmp2 = fcmp ult float %arg2, %C2195 %cmp3 = fcmp ult float %arg3, %C2196 %and1 = and i1 %cmp1, %cmp22197 %and2 = and i1 %and1, %cmp32198 ret i1 %and22199}2200 2201define i1 @test109(float %arg1, float %arg2, float %arg3, float %arg4, float %C) {2202; GFX11-LABEL: test109:2203; GFX11: ; %bb.0:2204; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2205; GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v02206; GFX11-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v22207; GFX11-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v32208; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v42209; GFX11-NEXT: v_cmp_gt_f32_e64 s0, v1, v42210; GFX11-NEXT: s_or_b32 s0, vcc_lo, s02211; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02212; GFX11-NEXT: s_setpc_b64 s[30:31]2213;2214; GFX11NONANS-LABEL: test109:2215; GFX11NONANS: ; %bb.0:2216; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2217; GFX11NONANS-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v32218; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v42219; GFX11NONANS-NEXT: v_cmp_gt_f32_e64 s0, v1, v42220; GFX11NONANS-NEXT: s_or_b32 s0, vcc_lo, s02221; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02222; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]2223 %cmp1 = fcmp olt float %arg1, %C2224 %cmp2 = fcmp olt float %arg2, %C2225 %cmp3 = fcmp ogt float %arg3, %C2226 %cmp4 = fcmp ogt float %arg4, %C2227 %or1 = or i1 %cmp1, %cmp22228 %or2 = or i1 %cmp3, %cmp42229 %or3 = or i1 %or1, %or22230 ret i1 %or32231}2232 2233define i1 @test110(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 {2234; GCN-LABEL: test110:2235; GCN: ; %bb.0:2236; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2237; GCN-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v52238; GCN-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v72239; GCN-NEXT: v_dual_max_f32 v0, v0, v1 :: v_dual_min_f32 v1, v2, v32240; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v82241; GCN-NEXT: v_cmp_gt_f32_e64 s0, v1, v82242; GCN-NEXT: s_and_b32 s0, vcc_lo, s02243; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02244; GCN-NEXT: s_setpc_b64 s[30:31]2245 %add1 = fadd nnan float %arg1, %C12246 %add2 = fadd nnan float %arg2, %C22247 %add3 = fadd nnan float %arg3, %C32248 %add4 = fadd nnan float %arg4, %C42249 %cmp1 = fcmp nnan ult float %add1, %C2250 %cmp2 = fcmp nnan ult float %add2, %C2251 %cmp3 = fcmp nnan ugt float %add3, %C2252 %cmp4 = fcmp nnan ugt float %add4, %C2253 %or1 = and i1 %cmp1, %cmp22254 %or2 = and i1 %cmp3, %cmp42255 %or3 = and i1 %or1, %or22256 ret i1 %or32257}2258 2259define i1 @test111(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %C) {2260; GFX11-LABEL: test111:2261; GFX11: ; %bb.0:2262; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2263; GFX11-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v22264; GFX11-NEXT: v_dual_min_f32 v2, v2, v3 :: v_dual_max_f32 v3, v4, v42265; GFX11-NEXT: v_min3_f32 v0, v0, v1, v22266; GFX11-NEXT: v_min_f32_e32 v0, v0, v32267; GFX11-NEXT: v_min3_f32 v0, v5, v6, v02268; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v82269; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo2270; GFX11-NEXT: s_setpc_b64 s[30:31]2271;2272; GFX11NONANS-LABEL: test111:2273; GFX11NONANS: ; %bb.0:2274; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2275; GFX11NONANS-NEXT: v_min_f32_e32 v2, v2, v32276; GFX11NONANS-NEXT: v_min3_f32 v0, v0, v1, v22277; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v42278; GFX11NONANS-NEXT: v_min3_f32 v0, v5, v6, v02279; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v82280; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo2281; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]2282 %cmp1 = fcmp olt float %arg1, %C2283 %cmp2 = fcmp olt float %arg2, %C2284 %or1 = or i1 %cmp1, %cmp22285 %cmp3 = fcmp olt float %arg3, %C2286 %cmp4 = fcmp olt float %arg4, %C2287 %or2 = or i1 %cmp3, %cmp42288 %cmp5 = fcmp olt float %arg5, %C2289 %or3 = or i1 %or1, %or22290 %or4 = or i1 %or3, %cmp52291 %cmp6 = fcmp olt float %arg6, %C2292 %cmp7 = fcmp olt float %arg7, %C2293 %or5 = or i1 %cmp6, %cmp72294 %cmp8 = fcmp olt float %arg8, %C2295 %or6 = or i1 %or5, %or42296 %or7 = or i1 %or6, %cmp82297 ret i1 %or62298}2299 2300define i1 @test112(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %C) {2301; GFX11-LABEL: test112:2302; GFX11: ; %bb.0:2303; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2304; GFX11-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v22305; GFX11-NEXT: v_cmp_nge_f32_e32 vcc_lo, v4, v82306; GFX11-NEXT: v_dual_max_f32 v5, v5, v5 :: v_dual_min_f32 v2, v2, v32307; GFX11-NEXT: v_max_f32_e32 v3, v6, v62308; GFX11-NEXT: v_min3_f32 v0, v0, v1, v22309; GFX11-NEXT: v_min3_f32 v0, v0, v5, v32310; GFX11-NEXT: v_cmp_lt_f32_e64 s0, v0, v82311; GFX11-NEXT: s_or_b32 s0, s0, vcc_lo2312; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02313; GFX11-NEXT: s_setpc_b64 s[30:31]2314;2315; GFX11NONANS-LABEL: test112:2316; GFX11NONANS: ; %bb.0:2317; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2318; GFX11NONANS-NEXT: v_min_f32_e32 v2, v2, v32319; GFX11NONANS-NEXT: v_min3_f32 v0, v0, v1, v22320; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v42321; GFX11NONANS-NEXT: v_min3_f32 v0, v5, v6, v02322; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v82323; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo2324; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]2325 %cmp1 = fcmp olt float %arg1, %C2326 %cmp2 = fcmp olt float %arg2, %C2327 %or1 = or i1 %cmp1, %cmp22328 %cmp3 = fcmp olt float %arg3, %C2329 %cmp4 = fcmp olt float %arg4, %C2330 %or2 = or i1 %cmp3, %cmp42331 %cmp5 = fcmp ult float %arg5, %C2332 %or3 = or i1 %or1, %or22333 %or4 = or i1 %or3, %cmp52334 %cmp6 = fcmp olt float %arg6, %C2335 %cmp7 = fcmp olt float %arg7, %C2336 %or5 = or i1 %cmp6, %cmp72337 %cmp8 = fcmp ult float %arg8, %C2338 %or6 = or i1 %or5, %or42339 %or7 = or i1 %or6, %cmp82340 ret i1 %or62341}2342 2343define i1 @test113(float %arg1, float %arg2, float %arg3, float %C) {2344; GFX11-LABEL: test113:2345; GFX11: ; %bb.0:2346; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2347; GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v02348; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v32349; GFX11-NEXT: v_max_f32_e32 v0, v0, v12350; GFX11-NEXT: v_cmp_nge_f32_e64 s0, v0, v32351; GFX11-NEXT: s_or_b32 s0, s0, vcc_lo2352; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02353; GFX11-NEXT: s_setpc_b64 s[30:31]2354;2355; GFX11NONANS-LABEL: test113:2356; GFX11NONANS: ; %bb.0:2357; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2358; GFX11NONANS-NEXT: v_maxmin_f32 v0, v0, v1, v22359; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v32360; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo2361; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]2362 %cmp1 = fcmp ult float %arg1, %C2363 %cmp2 = fcmp ult float %arg2, %C2364 %cmp3 = fcmp olt float %arg3, %C2365 %and1 = and i1 %cmp1, %cmp22366 %or1 = or i1 %and1, %cmp32367 ret i1 %or12368}2369 2370define i1 @test114(float %arg1, float %arg2, float %arg3, float %C) {2371; GFX11-LABEL: test114:2372; GFX11: ; %bb.0:2373; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2374; GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v02375; GFX11-NEXT: v_cmp_nge_f32_e32 vcc_lo, v2, v32376; GFX11-NEXT: v_max_f32_e32 v0, v0, v12377; GFX11-NEXT: v_cmp_gt_f32_e64 s0, v0, v32378; GFX11-NEXT: s_and_b32 s0, s0, vcc_lo2379; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02380; GFX11-NEXT: s_setpc_b64 s[30:31]2381;2382; GFX11NONANS-LABEL: test114:2383; GFX11NONANS: ; %bb.0:2384; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2385; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v12386; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v32387; GFX11NONANS-NEXT: v_cmp_gt_f32_e64 s0, v0, v32388; GFX11NONANS-NEXT: s_and_b32 s0, s0, vcc_lo2389; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02390; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]2391 %cmp1 = fcmp ogt float %arg1, %C2392 %cmp2 = fcmp ogt float %arg2, %C2393 %cmp3 = fcmp ult float %arg3, %C2394 %and1 = or i1 %cmp1, %cmp22395 %or1 = and i1 %and1, %cmp32396 ret i1 %or12397}2398 2399define i1 @test115(float %arg1, float %arg2, float %arg3, float %arg4, float %C) {2400; GFX11-LABEL: test115:2401; GFX11: ; %bb.0:2402; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2403; GFX11-NEXT: v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v1, v1, v12404; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v3, v3, v32405; GFX11-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v32406; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v42407; GFX11-NEXT: v_cmp_nge_f32_e64 s0, v1, v42408; GFX11-NEXT: s_or_b32 s0, vcc_lo, s02409; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02410; GFX11-NEXT: s_setpc_b64 s[30:31]2411;2412; GFX11NONANS-LABEL: test115:2413; GFX11NONANS: ; %bb.0:2414; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2415; GFX11NONANS-NEXT: v_max_f32_e32 v2, v2, v32416; GFX11NONANS-NEXT: v_min3_f32 v0, v0, v1, v22417; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v42418; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo2419; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]2420 %cmp1 = fcmp olt float %arg1, %C2421 %cmp2 = fcmp olt float %arg2, %C2422 %var3 = call float @llvm.canonicalize.f32(float %arg3)2423 %var4 = call float @llvm.canonicalize.f32(float %arg4)2424 %cmp3 = fcmp ult float %var3, %C2425 %cmp4 = fcmp ult float %var4, %C2426 %or1 = or i1 %cmp1, %cmp22427 %and1 = and i1 %cmp3, %cmp42428 %or2 = or i1 %or1, %and12429 ret i1 %or22430}2431 2432define i1 @test116(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %arg9, float %arg10, float %C) {2433; GFX11-LABEL: test116:2434; GFX11: ; %bb.0:2435; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2436; GFX11-NEXT: v_dual_max_f32 v9, v9, v9 :: v_dual_max_f32 v8, v8, v82437; GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v02438; GFX11-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v22439; GFX11-NEXT: v_dual_max_f32 v5, v5, v5 :: v_dual_max_f32 v4, v4, v42440; GFX11-NEXT: v_dual_max_f32 v7, v7, v7 :: v_dual_max_f32 v6, v6, v62441; GFX11-NEXT: v_min_f32_e32 v8, v8, v92442; GFX11-NEXT: v_dual_max_f32 v2, v2, v3 :: v_dual_min_f32 v3, v4, v52443; GFX11-NEXT: v_max_f32_e32 v4, v6, v72444; GFX11-NEXT: v_min3_f32 v0, v0, v1, v82445; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v102446; GFX11-NEXT: v_cmp_lt_f32_e64 s0, v3, v102447; GFX11-NEXT: v_cmp_gt_f32_e64 s1, v4, v102448; GFX11-NEXT: v_cmp_lt_f32_e64 s2, v0, v102449; GFX11-NEXT: s_or_b32 s0, s0, s12450; GFX11-NEXT: s_or_b32 s1, s2, vcc_lo2451; GFX11-NEXT: s_or_b32 s0, s0, s12452; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02453; GFX11-NEXT: s_setpc_b64 s[30:31]2454;2455; GFX11NONANS-LABEL: test116:2456; GFX11NONANS: ; %bb.0:2457; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2458; GFX11NONANS-NEXT: v_min_f32_e32 v8, v8, v92459; GFX11NONANS-NEXT: v_dual_max_f32 v2, v2, v3 :: v_dual_min_f32 v3, v4, v52460; GFX11NONANS-NEXT: v_max_f32_e32 v4, v6, v72461; GFX11NONANS-NEXT: v_min3_f32 v0, v0, v1, v82462; GFX11NONANS-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v102463; GFX11NONANS-NEXT: v_cmp_lt_f32_e64 s0, v3, v102464; GFX11NONANS-NEXT: v_cmp_gt_f32_e64 s1, v4, v102465; GFX11NONANS-NEXT: v_cmp_lt_f32_e64 s2, v0, v102466; GFX11NONANS-NEXT: s_or_b32 s0, s0, s12467; GFX11NONANS-NEXT: s_or_b32 s1, s2, vcc_lo2468; GFX11NONANS-NEXT: s_or_b32 s0, s0, s12469; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02470; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]2471 %cmp1 = fcmp olt float %arg1, %C2472 %cmp2 = fcmp olt float %arg2, %C2473 %cmp3 = fcmp ogt float %arg3, %C2474 %cmp4 = fcmp ogt float %arg4, %C2475 %cmp5 = fcmp olt float %arg5, %C2476 %cmp6 = fcmp olt float %arg6, %C2477 %cmp7 = fcmp ogt float %arg7, %C2478 %cmp8 = fcmp ogt float %arg8, %C2479 %cmp9 = fcmp olt float %arg9, %C2480 %cmp10 = fcmp olt float %arg10, %C2481 %or1 = or i1 %cmp1, %cmp22482 %or2 = or i1 %cmp3, %cmp42483 %or3 = or i1 %cmp5, %cmp62484 %or4 = or i1 %cmp7, %cmp82485 %or5 = or i1 %cmp9, %cmp102486 %or6 = or i1 %or1, %or22487 %or7 = or i1 %or3, %or42488 %or8 = or i1 %or5, %or62489 %or9 = or i1 %or7, %or82490 ret i1 %or92491}2492 2493define i1 @test117(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %arg9, float %arg10, float %arg11, float %arg12, float %C1, float %C2) {2494; GFX11-LABEL: test117:2495; GFX11: ; %bb.0:2496; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2497; GFX11-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v6, v6, v62498; GFX11-NEXT: v_dual_max_f32 v7, v7, v7 :: v_dual_max_f32 v10, v10, v102499; GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v02500; GFX11-NEXT: v_dual_max_f32 v11, v11, v11 :: v_dual_max_f32 v2, v2, v22501; GFX11-NEXT: v_min_f32_e32 v6, v6, v72502; GFX11-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_min_f32 v1, v10, v112503; GFX11-NEXT: v_min_f32_e32 v2, v2, v32504; GFX11-NEXT: v_min3_f32 v3, v4, v5, v62505; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v122506; GFX11-NEXT: v_min3_f32 v0, v8, v9, v12507; GFX11-NEXT: v_cmp_lt_f32_e64 s0, v2, v132508; GFX11-NEXT: v_cmp_lt_f32_e64 s1, v3, v132509; GFX11-NEXT: v_cmp_lt_f32_e64 s2, v0, v122510; GFX11-NEXT: s_or_b32 s0, vcc_lo, s02511; GFX11-NEXT: s_or_b32 s0, s0, s12512; GFX11-NEXT: s_or_b32 s0, s2, s02513; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02514; GFX11-NEXT: s_setpc_b64 s[30:31]2515;2516; GFX11NONANS-LABEL: test117:2517; GFX11NONANS: ; %bb.0:2518; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2519; GFX11NONANS-NEXT: v_min_f32_e32 v6, v6, v72520; GFX11NONANS-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_min_f32 v1, v10, v112521; GFX11NONANS-NEXT: v_min_f32_e32 v2, v2, v32522; GFX11NONANS-NEXT: v_min3_f32 v3, v4, v5, v62523; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v122524; GFX11NONANS-NEXT: v_min3_f32 v0, v8, v9, v12525; GFX11NONANS-NEXT: v_cmp_lt_f32_e64 s0, v2, v132526; GFX11NONANS-NEXT: v_cmp_lt_f32_e64 s1, v3, v132527; GFX11NONANS-NEXT: v_cmp_lt_f32_e64 s2, v0, v122528; GFX11NONANS-NEXT: s_or_b32 s0, vcc_lo, s02529; GFX11NONANS-NEXT: s_or_b32 s0, s0, s12530; GFX11NONANS-NEXT: s_or_b32 s0, s2, s02531; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02532; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]2533 %cmp1 = fcmp olt float %arg1, %C12534 %cmp2 = fcmp olt float %arg2, %C12535 %cmp3 = fcmp olt float %arg3, %C22536 %cmp4 = fcmp olt float %arg4, %C22537 %cmp5 = fcmp olt float %arg5, %C22538 %cmp6 = fcmp olt float %arg6, %C22539 %cmp7 = fcmp olt float %arg7, %C22540 %cmp8 = fcmp olt float %arg8, %C22541 %cmp9 = fcmp olt float %arg9, %C12542 %cmp10 = fcmp olt float %arg10, %C12543 %cmp11 = fcmp olt float %arg11, %C12544 %cmp12 = fcmp olt float %arg12, %C12545 %or1 = or i1 %cmp1, %cmp22546 %or2 = or i1 %cmp3, %cmp42547 %or3 = or i1 %cmp5, %cmp62548 %or4 = or i1 %cmp7, %cmp82549 %or5 = or i1 %cmp9, %cmp102550 %or6 = or i1 %cmp11, %cmp122551 %or7 = or i1 %or1, %or22552 %or8 = or i1 %or3, %or42553 %or9 = or i1 %or5, %or62554 %or10 = or i1 %or7, %or82555 %or11 = or i1 %or9, %or102556 ret i1 %or112557}2558 2559 2560define i1 @test118(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 {2561; GCN-LABEL: test118:2562; GCN: ; %bb.0:2563; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2564; GCN-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v52565; GCN-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v72566; GCN-NEXT: v_min_f32_e32 v0, v0, v12567; GCN-NEXT: v_max3_f32 v0, v0, v2, v32568; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v82569; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo2570; GCN-NEXT: s_setpc_b64 s[30:31]2571 %add1 = fadd nnan float %arg1, %C12572 %add2 = fadd nnan float %arg2, %C22573 %add3 = fadd nnan float %arg3, %C32574 %add4 = fadd nnan float %arg4, %C42575 %cmp1 = fcmp nnan ult float %add1, %C2576 %cmp2 = fcmp nnan ult float %add2, %C2577 %cmp3 = fcmp nnan ult float %add3, %C2578 %cmp4 = fcmp nnan ult float %add4, %C2579 %or1 = or i1 %cmp1, %cmp22580 %and1 = and i1 %cmp3, %cmp42581 %and2 = and i1 %or1, %and12582 ret i1 %and22583}2584 2585define i1 @test119(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 {2586; GCN-LABEL: test119:2587; GCN: ; %bb.0:2588; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2589; GCN-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v72590; GCN-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v52591; GCN-NEXT: v_min_f32_e32 v2, v2, v32592; GCN-NEXT: v_minmax_f32 v0, v0, v1, v22593; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v82594; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo2595; GCN-NEXT: s_setpc_b64 s[30:31]2596 %add1 = fadd nnan float %arg1, %C12597 %add2 = fadd nnan float %arg2, %C22598 %add3 = fadd nnan float %arg3, %C32599 %add4 = fadd nnan float %arg4, %C42600 %cmp1 = fcmp nnan ult float %add1, %C2601 %cmp2 = fcmp nnan ult float %add2, %C2602 %cmp3 = fcmp nnan ult float %add3, %C2603 %cmp4 = fcmp nnan ult float %add4, %C2604 %or1 = or i1 %cmp1, %cmp22605 %and1 = or i1 %cmp3, %cmp42606 %and2 = and i1 %or1, %and12607 ret i1 %and22608}2609 2610define i1 @test120(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 {2611; GCN-LABEL: test120:2612; GCN: ; %bb.0:2613; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2614; GCN-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v72615; GCN-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v52616; GCN-NEXT: v_max_f32_e32 v2, v2, v32617; GCN-NEXT: v_min3_f32 v0, v0, v1, v22618; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v82619; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo2620; GCN-NEXT: s_setpc_b64 s[30:31]2621 %add1 = fadd nnan float %arg1, %C12622 %add2 = fadd nnan float %arg2, %C22623 %add3 = fadd nnan float %arg3, %C32624 %add4 = fadd nnan float %arg4, %C42625 %cmp1 = fcmp nnan ult float %add1, %C2626 %cmp2 = fcmp nnan ult float %add2, %C2627 %cmp3 = fcmp nnan ult float %add3, %C2628 %cmp4 = fcmp nnan ult float %add4, %C2629 %or1 = or i1 %cmp1, %cmp22630 %and1 = and i1 %cmp3, %cmp42631 %and2 = or i1 %or1, %and12632 ret i1 %and22633}2634 2635define i1 @test121(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 {2636; GCN-LABEL: test121:2637; GCN: ; %bb.0:2638; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2639; GCN-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v72640; GCN-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v52641; GCN-NEXT: v_max_f32_e32 v2, v2, v32642; GCN-NEXT: v_maxmin_f32 v0, v0, v1, v22643; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v82644; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo2645; GCN-NEXT: s_setpc_b64 s[30:31]2646 %add1 = fadd nnan float %arg1, %C12647 %add2 = fadd nnan float %arg2, %C22648 %add3 = fadd nnan float %arg3, %C32649 %add4 = fadd nnan float %arg4, %C42650 %cmp1 = fcmp nnan ult float %add1, %C2651 %cmp2 = fcmp nnan ult float %add2, %C2652 %cmp3 = fcmp nnan ult float %add3, %C2653 %cmp4 = fcmp nnan ult float %add4, %C2654 %or1 = and i1 %cmp1, %cmp22655 %and1 = and i1 %cmp3, %cmp42656 %and2 = or i1 %or1, %and12657 ret i1 %and22658}2659 2660define i1 @test122(double %arg1, double %arg2, double %arg3) #1 {2661; GCN-LABEL: test122:2662; GCN: ; %bb.0:2663; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2664; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]2665; GCN-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]2666; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo2667; GCN-NEXT: s_setpc_b64 s[30:31]2668 %cmp1 = fcmp ult double %arg1, %arg32669 %cmp2 = fcmp ult double %arg2, %arg32670 %or1 = or i1 %cmp1, %cmp22671 ret i1 %or12672}2673 2674define i1 @test123(double %arg1, double %arg2, double %arg3) #1 {2675; GCN-LABEL: test123:2676; GCN: ; %bb.0:2677; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2678; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]2679; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]2680; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]2681; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]2682; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo2683; GCN-NEXT: s_setpc_b64 s[30:31]2684 %var1 = call double @llvm.canonicalize.f64(double %arg1)2685 %var2 = call double @llvm.canonicalize.f64(double %arg2)2686 %cmp1 = fcmp ogt double %var1, %arg32687 %cmp2 = fcmp ogt double %var2, %arg32688 %or1 = and i1 %cmp1, %cmp22689 ret i1 %or12690}2691 2692; The optimization does not apply to the following tests.2693 2694define i1 @test124(i32 %arg1, i64 %arg2) {2695; GCN-LABEL: test124:2696; GCN: ; %bb.0:2697; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2698; GCN-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0x3e8, v[1:2]2699; GCN-NEXT: v_cmp_gt_i32_e64 s0, 0x3e8, v02700; GCN-NEXT: s_or_b32 s0, s0, vcc_lo2701; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02702; GCN-NEXT: s_setpc_b64 s[30:31]2703 %cmp1 = icmp slt i32 %arg1, 10002704 %cmp2 = icmp slt i64 %arg2, 10002705 %or = or i1 %cmp1, %cmp22706 ret i1 %or2707}2708 2709define i1 @test125(i32 %arg1, i32 %arg2) {2710; GCN-LABEL: test125:2711; GCN: ; %bb.0:2712; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2713; GCN-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x3e8, v02714; GCN-NEXT: v_cmp_eq_u32_e64 s0, 0x3e8, v12715; GCN-NEXT: s_or_b32 s0, vcc_lo, s02716; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02717; GCN-NEXT: s_setpc_b64 s[30:31]2718 %cmp1 = icmp eq i32 %arg1, 10002719 %cmp2 = icmp eq i32 %arg2, 10002720 %or = or i1 %cmp1, %cmp22721 ret i1 %or2722}2723 2724define i1 @test126(i32 %arg1, i32 %arg2) {2725; GCN-LABEL: test126:2726; GCN: ; %bb.0:2727; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2728; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0x3e8, v02729; GCN-NEXT: v_cmp_ne_u32_e64 s0, 0x3e8, v12730; GCN-NEXT: s_or_b32 s0, vcc_lo, s02731; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02732; GCN-NEXT: s_setpc_b64 s[30:31]2733 %cmp1 = icmp ne i32 %arg1, 10002734 %cmp2 = icmp ne i32 %arg2, 10002735 %or = or i1 %cmp1, %cmp22736 ret i1 %or2737}2738 2739define i1 @test127(i64 %arg1, i64 %arg2, i64 %arg3) {2740; GCN-LABEL: test127:2741; GCN: ; %bb.0:2742; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2743; GCN-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]2744; GCN-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[4:5]2745; GCN-NEXT: s_or_b32 s0, vcc_lo, s02746; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02747; GCN-NEXT: s_setpc_b64 s[30:31]2748 %cmp1 = icmp ult i64 %arg1, %arg32749 %cmp2 = icmp ult i64 %arg2, %arg32750 %or = or i1 %cmp1, %cmp22751 ret i1 %or2752}2753 2754define i1 @test128(i32 %arg1, i32 %arg2, i32 %arg3) {2755; GCN-LABEL: test128:2756; GCN: ; %bb.0:2757; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2758; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v22759; GCN-NEXT: v_cmp_lt_u32_e64 s0, v2, v12760; GCN-NEXT: s_or_b32 s0, vcc_lo, s02761; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02762; GCN-NEXT: s_setpc_b64 s[30:31]2763 %cmp1 = icmp ult i32 %arg1, %arg32764 %cmp2 = icmp ult i32 %arg3, %arg22765 %or = or i1 %cmp1, %cmp22766 ret i1 %or2767}2768 2769define i1 @test129(i32 %arg1, i32 %arg2, i32 %arg3) {2770; GCN-LABEL: test129:2771; GCN: ; %bb.0:2772; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2773; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v22774; GCN-NEXT: v_cmp_le_u32_e64 s0, v1, v22775; GCN-NEXT: s_or_b32 s0, vcc_lo, s02776; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02777; GCN-NEXT: s_setpc_b64 s[30:31]2778 %cmp1 = icmp ult i32 %arg1, %arg32779 %cmp2 = icmp ule i32 %arg2, %arg32780 %or = or i1 %cmp1, %cmp22781 ret i1 %or2782}2783 2784define i1 @test130(i32 %arg1, i32 %arg2, i32 %arg3) {2785; GCN-LABEL: test130:2786; GCN: ; %bb.0:2787; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2788; GCN-NEXT: v_cmp_le_u32_e32 vcc_lo, v2, v02789; GCN-NEXT: v_cmp_gt_u32_e64 s0, v1, v22790; GCN-NEXT: s_or_b32 s0, vcc_lo, s02791; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02792; GCN-NEXT: s_setpc_b64 s[30:31]2793 %cmp1 = icmp ule i32 %arg3, %arg12794 %cmp2 = icmp ugt i32 %arg2, %arg32795 %or = or i1 %cmp1, %cmp22796 ret i1 %or2797}2798 2799define i1 @test131(i16 %arg1, i32 %arg2) {2800; GFX11-TRUE16-LABEL: test131:2801; GFX11-TRUE16: ; %bb.0:2802; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2803; GFX11-TRUE16-NEXT: v_cmp_gt_u32_e32 vcc_lo, 10, v12804; GFX11-TRUE16-NEXT: v_cmp_gt_u16_e64 s0, 10, v0.l2805; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, vcc_lo2806; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02807; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]2808;2809; GFX11-FAKE16-LABEL: test131:2810; GFX11-FAKE16: ; %bb.0:2811; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2812; GFX11-FAKE16-NEXT: v_cmp_gt_u16_e32 vcc_lo, 10, v02813; GFX11-FAKE16-NEXT: v_cmp_gt_u32_e64 s0, 10, v12814; GFX11-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s02815; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02816; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]2817;2818; GCN-TRUE16-LABEL: test131:2819; GCN-TRUE16: ; %bb.0:2820; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2821; GCN-TRUE16-NEXT: v_cmp_gt_u32_e32 vcc_lo, 10, v12822; GCN-TRUE16-NEXT: v_cmp_gt_u16_e64 s0, 10, v0.l2823; GCN-TRUE16-NEXT: s_or_b32 s0, s0, vcc_lo2824; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02825; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31]2826;2827; GCN-FAKE16-LABEL: test131:2828; GCN-FAKE16: ; %bb.0:2829; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2830; GCN-FAKE16-NEXT: v_cmp_gt_u16_e32 vcc_lo, 10, v02831; GCN-FAKE16-NEXT: v_cmp_gt_u32_e64 s0, 10, v12832; GCN-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s02833; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02834; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31]2835 %cmp1 = icmp ult i16 %arg1, 102836 %cmp2 = icmp ult i32 %arg2, 102837 %or = or i1 %cmp1, %cmp22838 ret i1 %or2839}2840 2841define i1 @test132(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {2842; GCN-LABEL: test132:2843; GCN: ; %bb.0:2844; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2845; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v22846; GCN-NEXT: v_cmp_lt_u32_e64 s0, v1, v22847; GCN-NEXT: v_cmp_lt_u32_e64 s1, v0, v32848; GCN-NEXT: s_or_b32 s0, vcc_lo, s02849; GCN-NEXT: s_or_b32 s1, s1, vcc_lo2850; GCN-NEXT: s_or_b32 s0, s0, s12851; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02852; GCN-NEXT: s_setpc_b64 s[30:31]2853 %cmp1 = icmp ult i32 %arg1, %arg32854 %cmp2 = icmp ult i32 %arg2, %arg32855 %or1 = or i1 %cmp1, %cmp22856 %cmp3 = icmp ult i32 %arg1, %arg42857 %or2 = or i1 %cmp3, %cmp12858 %or3 = or i1 %or1, %or22859 ret i1 %or32860}2861 2862define i1 @test133(i32 %arg1, i32 %arg2) {2863; GCN-LABEL: test133:2864; GCN: ; %bb.0:2865; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2866; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x64, v02867; GCN-NEXT: v_cmp_gt_u32_e64 s0, 0x3e8, v12868; GCN-NEXT: s_or_b32 s0, vcc_lo, s02869; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02870; GCN-NEXT: s_setpc_b64 s[30:31]2871 %cmp1 = icmp ult i32 %arg1, 1002872 %cmp2 = icmp ult i32 %arg2, 10002873 %or = or i1 %cmp1, %cmp22874 ret i1 %or2875}2876 2877define i1 @test134(float %arg1, float %arg2, float %arg3) #0 {2878; GFX11-LABEL: test134:2879; GFX11: ; %bb.0:2880; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2881; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v22882; GFX11-NEXT: v_cmp_gt_f32_e64 s0, v2, v12883; GFX11-NEXT: s_and_b32 s0, vcc_lo, s02884; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02885; GFX11-NEXT: s_setpc_b64 s[30:31]2886;2887; GFX11NONANS-LABEL: test134:2888; GFX11NONANS: ; %bb.0:2889; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2890; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v12891; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v22892; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo2893; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]2894 %cmp1 = fcmp olt float %arg1, %arg32895 %cmp2 = fcmp ogt float %arg3, %arg22896 %and1 = and i1 %cmp1, %cmp22897 ret i1 %and12898}2899 2900define i1 @test135(float %arg1, float %arg2, float %arg3) #0 {2901; GFX11-LABEL: test135:2902; GFX11: ; %bb.0:2903; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2904; GFX11-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v22905; GFX11-NEXT: v_cmp_nle_f32_e64 s0, v2, v12906; GFX11-NEXT: s_or_b32 s0, vcc_lo, s02907; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02908; GFX11-NEXT: s_setpc_b64 s[30:31]2909;2910; GFX11NONANS-LABEL: test135:2911; GFX11NONANS: ; %bb.0:2912; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2913; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v12914; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v22915; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo2916; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]2917 %cmp1 = fcmp ult float %arg1, %arg32918 %cmp2 = fcmp ugt float %arg3, %arg22919 %or1 = or i1 %cmp1, %cmp22920 ret i1 %or12921}2922 2923define i1 @test136(double %arg1, double %arg2, double %arg3) {2924; GFX11-LABEL: test136:2925; GFX11: ; %bb.0:2926; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2927; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]2928; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]2929; GFX11-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]2930; GFX11-NEXT: v_cmp_ge_f64_e64 s0, v[4:5], v[2:3]2931; GFX11-NEXT: s_and_b32 s0, vcc_lo, s02932; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02933; GFX11-NEXT: s_setpc_b64 s[30:31]2934;2935; GFX11NONANS-LABEL: test136:2936; GFX11NONANS: ; %bb.0:2937; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2938; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]2939; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]2940; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]2941; GFX11NONANS-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]2942; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo2943; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]2944 %var1 = call double @llvm.canonicalize.f64(double %arg1)2945 %var2 = call double @llvm.canonicalize.f64(double %arg2)2946 %cmp1 = fcmp ole double %var1, %arg32947 %cmp2 = fcmp oge double %arg3, %var22948 %and1 = and i1 %cmp1, %cmp22949 ret i1 %and12950}2951 2952define i1 @test137(float %arg1, float %arg2, float %arg3) {2953; GFX11-LABEL: test137:2954; GFX11: ; %bb.0:2955; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2956; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v12957; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v22958; GFX11-NEXT: v_cmp_nlt_f32_e64 s0, v2, v12959; GFX11-NEXT: s_or_b32 s0, vcc_lo, s02960; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02961; GFX11-NEXT: s_setpc_b64 s[30:31]2962;2963; GFX11NONANS-LABEL: test137:2964; GFX11NONANS: ; %bb.0:2965; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2966; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v12967; GFX11NONANS-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v22968; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo2969; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]2970 %var1 = call float @llvm.canonicalize.f32(float %arg1)2971 %var2 = call float @llvm.canonicalize.f32(float %arg2)2972 %cmp1 = fcmp ule float %var1, %arg32973 %cmp2 = fcmp uge float %arg3, %var22974 %or1 = or i1 %cmp1, %cmp22975 ret i1 %or12976}2977 2978define i1 @test138(float %arg1, float %arg2, float %arg3) #0 {2979; GFX11-LABEL: test138:2980; GFX11: ; %bb.0:2981; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2982; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v22983; GFX11-NEXT: v_cmp_lt_f32_e64 s0, v1, v22984; GFX11-NEXT: s_and_b32 s0, vcc_lo, s02985; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s02986; GFX11-NEXT: s_setpc_b64 s[30:31]2987;2988; GFX11NONANS-LABEL: test138:2989; GFX11NONANS: ; %bb.0:2990; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2991; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v12992; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v22993; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo2994; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]2995 %cmp1 = fcmp olt float %arg1, %arg32996 %cmp2 = fcmp olt float %arg2, %arg32997 %and1 = and i1 %cmp1, %cmp22998 ret i1 %and12999}3000 3001define i1 @test139(double %arg1, double %arg2, double %arg3) #0 {3002; GFX11-LABEL: test139:3003; GFX11: ; %bb.0:3004; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3005; GFX11-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]3006; GFX11-NEXT: v_cmp_le_f64_e64 s0, v[2:3], v[4:5]3007; GFX11-NEXT: s_and_b32 s0, vcc_lo, s03008; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s03009; GFX11-NEXT: s_setpc_b64 s[30:31]3010;3011; GFX11NONANS-LABEL: test139:3012; GFX11NONANS: ; %bb.0:3013; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3014; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]3015; GFX11NONANS-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]3016; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo3017; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]3018 %cmp1 = fcmp ole double %arg1, %arg33019 %cmp2 = fcmp ole double %arg2, %arg33020 %and1 = and i1 %cmp1, %cmp23021 ret i1 %and13022}3023 3024define i1 @test140(double %arg1, double %arg2, double %arg3) #0 {3025; GFX11-LABEL: test140:3026; GFX11: ; %bb.0:3027; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3028; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]3029; GFX11-NEXT: v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]3030; GFX11-NEXT: s_and_b32 s0, vcc_lo, s03031; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s03032; GFX11-NEXT: s_setpc_b64 s[30:31]3033;3034; GFX11NONANS-LABEL: test140:3035; GFX11NONANS: ; %bb.0:3036; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3037; GFX11NONANS-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]3038; GFX11NONANS-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]3039; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo3040; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]3041 %cmp1 = fcmp ogt double %arg1, %arg33042 %cmp2 = fcmp ogt double %arg2, %arg33043 %and1 = and i1 %cmp1, %cmp23044 ret i1 %and13045}3046 3047define i1 @test141(float %arg1, float %arg2, float %arg3) #0 {3048; GFX11-LABEL: test141:3049; GFX11: ; %bb.0:3050; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3051; GFX11-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v23052; GFX11-NEXT: v_cmp_ge_f32_e64 s0, v1, v23053; GFX11-NEXT: s_and_b32 s0, vcc_lo, s03054; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s03055; GFX11-NEXT: s_setpc_b64 s[30:31]3056;3057; GFX11NONANS-LABEL: test141:3058; GFX11NONANS: ; %bb.0:3059; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3060; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v13061; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v23062; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo3063; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]3064 %cmp1 = fcmp oge float %arg1, %arg33065 %cmp2 = fcmp oge float %arg2, %arg33066 %and1 = and i1 %cmp1, %cmp23067 ret i1 %and13068}3069 3070define i1 @test142(double %arg1, double %arg2, double %arg3) #0 {3071; GFX11-LABEL: test142:3072; GFX11: ; %bb.0:3073; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3074; GFX11-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]3075; GFX11-NEXT: v_cmp_nle_f64_e64 s0, v[2:3], v[4:5]3076; GFX11-NEXT: s_or_b32 s0, vcc_lo, s03077; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s03078; GFX11-NEXT: s_setpc_b64 s[30:31]3079;3080; GFX11NONANS-LABEL: test142:3081; GFX11NONANS: ; %bb.0:3082; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3083; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]3084; GFX11NONANS-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]3085; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo3086; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]3087 %cmp1 = fcmp ugt double %arg1, %arg33088 %cmp2 = fcmp ugt double %arg2, %arg33089 %or1 = or i1 %cmp1, %cmp23090 ret i1 %or13091}3092 3093define i1 @test143(float %arg1, float %arg2, float %arg3) #0 {3094; GFX11-LABEL: test143:3095; GFX11: ; %bb.0:3096; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3097; GFX11-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v23098; GFX11-NEXT: v_cmp_nlt_f32_e64 s0, v1, v23099; GFX11-NEXT: s_or_b32 s0, vcc_lo, s03100; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s03101; GFX11-NEXT: s_setpc_b64 s[30:31]3102;3103; GFX11NONANS-LABEL: test143:3104; GFX11NONANS: ; %bb.0:3105; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3106; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v13107; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v23108; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo3109; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]3110 %cmp1 = fcmp uge float %arg1, %arg33111 %cmp2 = fcmp uge float %arg2, %arg33112 %or1 = or i1 %cmp1, %cmp23113 ret i1 %or13114}3115 3116define i1 @test144(float %arg1, float %arg2, float %arg3) #0 {3117; GFX11-LABEL: test144:3118; GFX11: ; %bb.0:3119; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3120; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v23121; GFX11-NEXT: v_cmp_ngt_f32_e64 s0, v1, v23122; GFX11-NEXT: s_or_b32 s0, vcc_lo, s03123; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s03124; GFX11-NEXT: s_setpc_b64 s[30:31]3125;3126; GFX11NONANS-LABEL: test144:3127; GFX11NONANS: ; %bb.0:3128; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3129; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v13130; GFX11NONANS-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v23131; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo3132; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]3133 %cmp1 = fcmp ule float %arg1, %arg33134 %cmp2 = fcmp ule float %arg2, %arg33135 %or1 = or i1 %cmp1, %cmp23136 ret i1 %or13137}3138 3139define i1 @test145(double %arg1, double %arg2, double %arg3) #0 {3140; GFX11-LABEL: test145:3141; GFX11: ; %bb.0:3142; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3143; GFX11-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]3144; GFX11-NEXT: v_cmp_nge_f64_e64 s0, v[2:3], v[4:5]3145; GFX11-NEXT: s_or_b32 s0, vcc_lo, s03146; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s03147; GFX11-NEXT: s_setpc_b64 s[30:31]3148;3149; GFX11NONANS-LABEL: test145:3150; GFX11NONANS: ; %bb.0:3151; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3152; GFX11NONANS-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]3153; GFX11NONANS-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]3154; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo3155; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]3156 %cmp1 = fcmp ult double %arg1, %arg33157 %cmp2 = fcmp ult double %arg2, %arg33158 %or1 = or i1 %cmp1, %cmp23159 ret i1 %or13160}3161 3162define i1 @test146(float %arg1, float %arg2, float %arg3) {3163; GFX11-LABEL: test146:3164; GFX11: ; %bb.0:3165; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3166; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v13167; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v23168; GFX11-NEXT: v_cmp_lt_f32_e64 s0, v1, v23169; GFX11-NEXT: s_and_b32 s0, vcc_lo, s03170; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s03171; GFX11-NEXT: s_setpc_b64 s[30:31]3172;3173; GFX11NONANS-LABEL: test146:3174; GFX11NONANS: ; %bb.0:3175; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3176; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v13177; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v23178; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo3179; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]3180 %var1 = call float @llvm.canonicalize.f32(float %arg1)3181 %var2 = call float @llvm.canonicalize.f32(float %arg2)3182 %cmp1 = fcmp olt float %var1, %arg33183 %cmp2 = fcmp olt float %var2, %arg33184 %and1 = and i1 %cmp1, %cmp23185 ret i1 %and13186}3187 3188define i1 @test147(double %arg1, double %arg2, double %arg3) {3189; GFX11-LABEL: test147:3190; GFX11: ; %bb.0:3191; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3192; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]3193; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]3194; GFX11-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]3195; GFX11-NEXT: v_cmp_le_f64_e64 s0, v[2:3], v[4:5]3196; GFX11-NEXT: s_and_b32 s0, vcc_lo, s03197; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s03198; GFX11-NEXT: s_setpc_b64 s[30:31]3199;3200; GFX11NONANS-LABEL: test147:3201; GFX11NONANS: ; %bb.0:3202; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3203; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]3204; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]3205; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]3206; GFX11NONANS-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]3207; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo3208; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]3209 %var1 = call double @llvm.canonicalize.f64(double %arg1)3210 %var2 = call double @llvm.canonicalize.f64(double %arg2)3211 %cmp1 = fcmp ole double %var1, %arg33212 %cmp2 = fcmp ole double %var2, %arg33213 %and1 = and i1 %cmp1, %cmp23214 ret i1 %and13215}3216 3217define i1 @test148(double %arg1, double %arg2, double %arg3) {3218; GFX11-LABEL: test148:3219; GFX11: ; %bb.0:3220; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3221; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]3222; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]3223; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]3224; GFX11-NEXT: v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]3225; GFX11-NEXT: s_and_b32 s0, vcc_lo, s03226; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s03227; GFX11-NEXT: s_setpc_b64 s[30:31]3228;3229; GFX11NONANS-LABEL: test148:3230; GFX11NONANS: ; %bb.0:3231; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3232; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]3233; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]3234; GFX11NONANS-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]3235; GFX11NONANS-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]3236; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo3237; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]3238 %var1 = call double @llvm.canonicalize.f64(double %arg1)3239 %var2 = call double @llvm.canonicalize.f64(double %arg2)3240 %cmp1 = fcmp ogt double %var1, %arg33241 %cmp2 = fcmp ogt double %var2, %arg33242 %and1 = and i1 %cmp1, %cmp23243 ret i1 %and13244}3245 3246define i1 @test149(float %arg1, float %arg2, float %arg3) {3247; GFX11-LABEL: test149:3248; GFX11: ; %bb.0:3249; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3250; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v13251; GFX11-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v23252; GFX11-NEXT: v_cmp_ge_f32_e64 s0, v1, v23253; GFX11-NEXT: s_and_b32 s0, vcc_lo, s03254; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s03255; GFX11-NEXT: s_setpc_b64 s[30:31]3256;3257; GFX11NONANS-LABEL: test149:3258; GFX11NONANS: ; %bb.0:3259; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3260; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v13261; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v23262; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo3263; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]3264 %var1 = call float @llvm.canonicalize.f32(float %arg1)3265 %var2 = call float @llvm.canonicalize.f32(float %arg2)3266 %cmp1 = fcmp oge float %var1, %arg33267 %cmp2 = fcmp oge float %var2, %arg33268 %and1 = and i1 %cmp1, %cmp23269 ret i1 %and13270}3271 3272define i1 @test150(double %arg1, double %arg2, double %arg3) {3273; GFX11-LABEL: test150:3274; GFX11: ; %bb.0:3275; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3276; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]3277; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]3278; GFX11-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]3279; GFX11-NEXT: v_cmp_nle_f64_e64 s0, v[2:3], v[4:5]3280; GFX11-NEXT: s_or_b32 s0, vcc_lo, s03281; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s03282; GFX11-NEXT: s_setpc_b64 s[30:31]3283;3284; GFX11NONANS-LABEL: test150:3285; GFX11NONANS: ; %bb.0:3286; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3287; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]3288; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]3289; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]3290; GFX11NONANS-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]3291; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo3292; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]3293 %var1 = call double @llvm.canonicalize.f64(double %arg1)3294 %var2 = call double @llvm.canonicalize.f64(double %arg2)3295 %cmp1 = fcmp ugt double %var1, %arg33296 %cmp2 = fcmp ugt double %var2, %arg33297 %or1 = or i1 %cmp1, %cmp23298 ret i1 %or13299}3300 3301define i1 @test151(float %arg1, float %arg2, float %arg3) {3302; GFX11-LABEL: test151:3303; GFX11: ; %bb.0:3304; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3305; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v13306; GFX11-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v23307; GFX11-NEXT: v_cmp_nlt_f32_e64 s0, v1, v23308; GFX11-NEXT: s_or_b32 s0, vcc_lo, s03309; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s03310; GFX11-NEXT: s_setpc_b64 s[30:31]3311;3312; GFX11NONANS-LABEL: test151:3313; GFX11NONANS: ; %bb.0:3314; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3315; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v13316; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v23317; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo3318; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]3319 %var1 = call float @llvm.canonicalize.f32(float %arg1)3320 %var2 = call float @llvm.canonicalize.f32(float %arg2)3321 %cmp1 = fcmp uge float %var1, %arg33322 %cmp2 = fcmp uge float %var2, %arg33323 %or1 = or i1 %cmp1, %cmp23324 ret i1 %or13325}3326 3327define i1 @test152(float %arg1, float %arg2, float %arg3) {3328; GFX11-LABEL: test152:3329; GFX11: ; %bb.0:3330; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3331; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v13332; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v23333; GFX11-NEXT: v_cmp_ngt_f32_e64 s0, v1, v23334; GFX11-NEXT: s_or_b32 s0, vcc_lo, s03335; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s03336; GFX11-NEXT: s_setpc_b64 s[30:31]3337;3338; GFX11NONANS-LABEL: test152:3339; GFX11NONANS: ; %bb.0:3340; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3341; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v13342; GFX11NONANS-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v23343; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo3344; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]3345 %var1 = call float @llvm.canonicalize.f32(float %arg1)3346 %var2 = call float @llvm.canonicalize.f32(float %arg2)3347 %cmp1 = fcmp ule float %var1, %arg33348 %cmp2 = fcmp ule float %var2, %arg33349 %or1 = or i1 %cmp1, %cmp23350 ret i1 %or13351}3352 3353define i1 @test153(double %arg1, double %arg2, double %arg3) {3354; GFX11-LABEL: test153:3355; GFX11: ; %bb.0:3356; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3357; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]3358; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]3359; GFX11-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]3360; GFX11-NEXT: v_cmp_nge_f64_e64 s0, v[2:3], v[4:5]3361; GFX11-NEXT: s_or_b32 s0, vcc_lo, s03362; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s03363; GFX11-NEXT: s_setpc_b64 s[30:31]3364;3365; GFX11NONANS-LABEL: test153:3366; GFX11NONANS: ; %bb.0:3367; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3368; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]3369; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]3370; GFX11NONANS-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]3371; GFX11NONANS-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]3372; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo3373; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]3374 %var1 = call double @llvm.canonicalize.f64(double %arg1)3375 %var2 = call double @llvm.canonicalize.f64(double %arg2)3376 %cmp1 = fcmp ult double %var1, %arg33377 %cmp2 = fcmp ult double %var2, %arg33378 %or1 = or i1 %cmp1, %cmp23379 ret i1 %or13380}3381 3382declare double @llvm.canonicalize.f64(double)3383declare float @llvm.canonicalize.f32(float)3384declare half @llvm.canonicalize.f16(half)3385declare <2 x half> @llvm.canonicalize.v2f16(<2 x half>)3386 3387attributes #0 = { nounwind "amdgpu-ieee"="false" }3388attributes #1 = { nounwind "no-nans-fp-math"="true" }3389;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:3390; GFX11NONANS-FAKE16: {{.*}}3391; GFX11NONANS-TRUE16: {{.*}}3392