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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -amdgpu-sdwa-peephole=0 < %s | FileCheck -check-prefix=SDAG %s3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1150 -amdgpu-sdwa-peephole=0 < %s | FileCheck -check-prefix=GISEL %s4 5define amdgpu_vs void @fcmp_f32_olt_to_ogt(ptr addrspace(1) inreg %out, float inreg %a) {6; SDAG-LABEL: fcmp_f32_olt_to_ogt:7; SDAG: ; %bb.0: ; %entry8; SDAG-NEXT: s_cmp_gt_f32 s2, 2.09; SDAG-NEXT: v_mov_b32_e32 v0, 010; SDAG-NEXT: s_cselect_b32 s2, -1, 011; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)12; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s213; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]14; SDAG-NEXT: s_endpgm15;16; GISEL-LABEL: fcmp_f32_olt_to_ogt:17; GISEL: ; %bb.0: ; %entry18; GISEL-NEXT: s_cmp_gt_f32 s2, 2.019; GISEL-NEXT: v_mov_b32_e32 v1, 020; GISEL-NEXT: s_cselect_b32 s2, 1, 021; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)22; GISEL-NEXT: s_bfe_i32 s2, s2, 0x1000023; GISEL-NEXT: v_mov_b32_e32 v0, s224; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]25; GISEL-NEXT: s_endpgm26entry:27 %0 = fcmp olt float 2.0, %a28 %1 = sext i1 %0 to i3229 store i32 %1, ptr addrspace(1) %out30 ret void31}32 33define amdgpu_vs void @fcmp_f32_ogt_to_olt(ptr addrspace(1) inreg %out, float inreg %a) {34; SDAG-LABEL: fcmp_f32_ogt_to_olt:35; SDAG: ; %bb.0: ; %entry36; SDAG-NEXT: s_cmp_lt_f32 s2, 2.037; SDAG-NEXT: v_mov_b32_e32 v0, 038; SDAG-NEXT: s_cselect_b32 s2, -1, 039; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)40; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s241; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]42; SDAG-NEXT: s_endpgm43;44; GISEL-LABEL: fcmp_f32_ogt_to_olt:45; GISEL: ; %bb.0: ; %entry46; GISEL-NEXT: s_cmp_lt_f32 s2, 2.047; GISEL-NEXT: v_mov_b32_e32 v1, 048; GISEL-NEXT: s_cselect_b32 s2, 1, 049; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)50; GISEL-NEXT: s_bfe_i32 s2, s2, 0x1000051; GISEL-NEXT: v_mov_b32_e32 v0, s252; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]53; GISEL-NEXT: s_endpgm54entry:55 %0 = fcmp ogt float 2.0, %a56 %1 = sext i1 %0 to i3257 store i32 %1, ptr addrspace(1) %out58 ret void59}60 61define amdgpu_vs void @fcmp_f32_ole_to_oge(ptr addrspace(1) inreg %out, float inreg %a) {62; SDAG-LABEL: fcmp_f32_ole_to_oge:63; SDAG: ; %bb.0: ; %entry64; SDAG-NEXT: s_cmp_ge_f32 s2, 2.065; SDAG-NEXT: v_mov_b32_e32 v0, 066; SDAG-NEXT: s_cselect_b32 s2, -1, 067; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)68; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s269; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]70; SDAG-NEXT: s_endpgm71;72; GISEL-LABEL: fcmp_f32_ole_to_oge:73; GISEL: ; %bb.0: ; %entry74; GISEL-NEXT: s_cmp_ge_f32 s2, 2.075; GISEL-NEXT: v_mov_b32_e32 v1, 076; GISEL-NEXT: s_cselect_b32 s2, 1, 077; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)78; GISEL-NEXT: s_bfe_i32 s2, s2, 0x1000079; GISEL-NEXT: v_mov_b32_e32 v0, s280; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]81; GISEL-NEXT: s_endpgm82entry:83 %0 = fcmp ole float 2.0, %a84 %1 = sext i1 %0 to i3285 store i32 %1, ptr addrspace(1) %out86 ret void87}88 89define amdgpu_vs void @fcmp_f32_oge_to_ole(ptr addrspace(1) inreg %out, float inreg %a) {90; SDAG-LABEL: fcmp_f32_oge_to_ole:91; SDAG: ; %bb.0: ; %entry92; SDAG-NEXT: s_cmp_le_f32 s2, 2.093; SDAG-NEXT: v_mov_b32_e32 v0, 094; SDAG-NEXT: s_cselect_b32 s2, -1, 095; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)96; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s297; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]98; SDAG-NEXT: s_endpgm99;100; GISEL-LABEL: fcmp_f32_oge_to_ole:101; GISEL: ; %bb.0: ; %entry102; GISEL-NEXT: s_cmp_le_f32 s2, 2.0103; GISEL-NEXT: v_mov_b32_e32 v1, 0104; GISEL-NEXT: s_cselect_b32 s2, 1, 0105; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)106; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000107; GISEL-NEXT: v_mov_b32_e32 v0, s2108; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]109; GISEL-NEXT: s_endpgm110entry:111 %0 = fcmp oge float 2.0, %a112 %1 = sext i1 %0 to i32113 store i32 %1, ptr addrspace(1) %out114 ret void115}116 117define amdgpu_vs void @fcmp_f32_ult_to_ugt(ptr addrspace(1) inreg %out, float inreg %a) {118; SDAG-LABEL: fcmp_f32_ult_to_ugt:119; SDAG: ; %bb.0: ; %entry120; SDAG-NEXT: s_cmp_nle_f32 s2, 2.0121; SDAG-NEXT: v_mov_b32_e32 v0, 0122; SDAG-NEXT: s_cselect_b32 s2, -1, 0123; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)124; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2125; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]126; SDAG-NEXT: s_endpgm127;128; GISEL-LABEL: fcmp_f32_ult_to_ugt:129; GISEL: ; %bb.0: ; %entry130; GISEL-NEXT: s_cmp_nle_f32 s2, 2.0131; GISEL-NEXT: v_mov_b32_e32 v1, 0132; GISEL-NEXT: s_cselect_b32 s2, 1, 0133; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)134; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000135; GISEL-NEXT: v_mov_b32_e32 v0, s2136; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]137; GISEL-NEXT: s_endpgm138entry:139 %0 = fcmp ult float 2.0, %a140 %1 = sext i1 %0 to i32141 store i32 %1, ptr addrspace(1) %out142 ret void143}144 145define amdgpu_vs void @fcmp_f32_ugt_to_ult(ptr addrspace(1) inreg %out, float inreg %a) {146; SDAG-LABEL: fcmp_f32_ugt_to_ult:147; SDAG: ; %bb.0: ; %entry148; SDAG-NEXT: s_cmp_nge_f32 s2, 2.0149; SDAG-NEXT: v_mov_b32_e32 v0, 0150; SDAG-NEXT: s_cselect_b32 s2, -1, 0151; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)152; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2153; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]154; SDAG-NEXT: s_endpgm155;156; GISEL-LABEL: fcmp_f32_ugt_to_ult:157; GISEL: ; %bb.0: ; %entry158; GISEL-NEXT: s_cmp_nge_f32 s2, 2.0159; GISEL-NEXT: v_mov_b32_e32 v1, 0160; GISEL-NEXT: s_cselect_b32 s2, 1, 0161; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)162; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000163; GISEL-NEXT: v_mov_b32_e32 v0, s2164; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]165; GISEL-NEXT: s_endpgm166entry:167 %0 = fcmp ugt float 2.0, %a168 %1 = sext i1 %0 to i32169 store i32 %1, ptr addrspace(1) %out170 ret void171}172 173define amdgpu_vs void @fcmp_f32_ule_to_uge(ptr addrspace(1) inreg %out, float inreg %a) {174; SDAG-LABEL: fcmp_f32_ule_to_uge:175; SDAG: ; %bb.0: ; %entry176; SDAG-NEXT: s_cmp_nlt_f32 s2, 2.0177; SDAG-NEXT: v_mov_b32_e32 v0, 0178; SDAG-NEXT: s_cselect_b32 s2, -1, 0179; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)180; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2181; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]182; SDAG-NEXT: s_endpgm183;184; GISEL-LABEL: fcmp_f32_ule_to_uge:185; GISEL: ; %bb.0: ; %entry186; GISEL-NEXT: s_cmp_nlt_f32 s2, 2.0187; GISEL-NEXT: v_mov_b32_e32 v1, 0188; GISEL-NEXT: s_cselect_b32 s2, 1, 0189; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)190; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000191; GISEL-NEXT: v_mov_b32_e32 v0, s2192; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]193; GISEL-NEXT: s_endpgm194entry:195 %0 = fcmp ule float 2.0, %a196 %1 = sext i1 %0 to i32197 store i32 %1, ptr addrspace(1) %out198 ret void199}200 201define amdgpu_vs void @fcmp_f32_uge_to_ule(ptr addrspace(1) inreg %out, float inreg %a) {202; SDAG-LABEL: fcmp_f32_uge_to_ule:203; SDAG: ; %bb.0: ; %entry204; SDAG-NEXT: s_cmp_ngt_f32 s2, 2.0205; SDAG-NEXT: v_mov_b32_e32 v0, 0206; SDAG-NEXT: s_cselect_b32 s2, -1, 0207; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)208; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2209; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]210; SDAG-NEXT: s_endpgm211;212; GISEL-LABEL: fcmp_f32_uge_to_ule:213; GISEL: ; %bb.0: ; %entry214; GISEL-NEXT: s_cmp_ngt_f32 s2, 2.0215; GISEL-NEXT: v_mov_b32_e32 v1, 0216; GISEL-NEXT: s_cselect_b32 s2, 1, 0217; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)218; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000219; GISEL-NEXT: v_mov_b32_e32 v0, s2220; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]221; GISEL-NEXT: s_endpgm222entry:223 %0 = fcmp uge float 2.0, %a224 %1 = sext i1 %0 to i32225 store i32 %1, ptr addrspace(1) %out226 ret void227}228 229define amdgpu_vs void @fcmp_f16_olt_to_ogt(ptr addrspace(1) inreg %out, half inreg %a) {230; SDAG-LABEL: fcmp_f16_olt_to_ogt:231; SDAG: ; %bb.0: ; %entry232; SDAG-NEXT: s_cmp_gt_f16 s2, 0x4000233; SDAG-NEXT: v_mov_b32_e32 v0, 0234; SDAG-NEXT: s_cselect_b32 s2, -1, 0235; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)236; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2237; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]238; SDAG-NEXT: s_endpgm239;240; GISEL-LABEL: fcmp_f16_olt_to_ogt:241; GISEL: ; %bb.0: ; %entry242; GISEL-NEXT: s_cmp_gt_f16 s2, 0x4000243; GISEL-NEXT: v_mov_b32_e32 v1, 0244; GISEL-NEXT: s_cselect_b32 s2, 1, 0245; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)246; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000247; GISEL-NEXT: v_mov_b32_e32 v0, s2248; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]249; GISEL-NEXT: s_endpgm250entry:251 %0 = fcmp olt half 2.0, %a252 %1 = sext i1 %0 to i32253 store i32 %1, ptr addrspace(1) %out254 ret void255}256 257define amdgpu_vs void @fcmp_f16_ogt_to_olt(ptr addrspace(1) inreg %out, half inreg %a) {258; SDAG-LABEL: fcmp_f16_ogt_to_olt:259; SDAG: ; %bb.0: ; %entry260; SDAG-NEXT: s_cmp_lt_f16 s2, 0x4000261; SDAG-NEXT: v_mov_b32_e32 v0, 0262; SDAG-NEXT: s_cselect_b32 s2, -1, 0263; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)264; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2265; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]266; SDAG-NEXT: s_endpgm267;268; GISEL-LABEL: fcmp_f16_ogt_to_olt:269; GISEL: ; %bb.0: ; %entry270; GISEL-NEXT: s_cmp_lt_f16 s2, 0x4000271; GISEL-NEXT: v_mov_b32_e32 v1, 0272; GISEL-NEXT: s_cselect_b32 s2, 1, 0273; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)274; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000275; GISEL-NEXT: v_mov_b32_e32 v0, s2276; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]277; GISEL-NEXT: s_endpgm278entry:279 %0 = fcmp ogt half 2.0, %a280 %1 = sext i1 %0 to i32281 store i32 %1, ptr addrspace(1) %out282 ret void283}284 285define amdgpu_vs void @fcmp_f16_ole_to_oge(ptr addrspace(1) inreg %out, half inreg %a) {286; SDAG-LABEL: fcmp_f16_ole_to_oge:287; SDAG: ; %bb.0: ; %entry288; SDAG-NEXT: s_cmp_ge_f16 s2, 0x4000289; SDAG-NEXT: v_mov_b32_e32 v0, 0290; SDAG-NEXT: s_cselect_b32 s2, -1, 0291; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)292; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2293; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]294; SDAG-NEXT: s_endpgm295;296; GISEL-LABEL: fcmp_f16_ole_to_oge:297; GISEL: ; %bb.0: ; %entry298; GISEL-NEXT: s_cmp_ge_f16 s2, 0x4000299; GISEL-NEXT: v_mov_b32_e32 v1, 0300; GISEL-NEXT: s_cselect_b32 s2, 1, 0301; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)302; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000303; GISEL-NEXT: v_mov_b32_e32 v0, s2304; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]305; GISEL-NEXT: s_endpgm306entry:307 %0 = fcmp ole half 2.0, %a308 %1 = sext i1 %0 to i32309 store i32 %1, ptr addrspace(1) %out310 ret void311}312 313define amdgpu_vs void @fcmp_f16_oge_to_ole(ptr addrspace(1) inreg %out, half inreg %a) {314; SDAG-LABEL: fcmp_f16_oge_to_ole:315; SDAG: ; %bb.0: ; %entry316; SDAG-NEXT: s_cmp_le_f16 s2, 0x4000317; SDAG-NEXT: v_mov_b32_e32 v0, 0318; SDAG-NEXT: s_cselect_b32 s2, -1, 0319; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)320; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2321; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]322; SDAG-NEXT: s_endpgm323;324; GISEL-LABEL: fcmp_f16_oge_to_ole:325; GISEL: ; %bb.0: ; %entry326; GISEL-NEXT: s_cmp_le_f16 s2, 0x4000327; GISEL-NEXT: v_mov_b32_e32 v1, 0328; GISEL-NEXT: s_cselect_b32 s2, 1, 0329; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)330; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000331; GISEL-NEXT: v_mov_b32_e32 v0, s2332; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]333; GISEL-NEXT: s_endpgm334entry:335 %0 = fcmp oge half 2.0, %a336 %1 = sext i1 %0 to i32337 store i32 %1, ptr addrspace(1) %out338 ret void339}340 341define amdgpu_vs void @fcmp_f16_ult_to_ugt(ptr addrspace(1) inreg %out, half inreg %a) {342; SDAG-LABEL: fcmp_f16_ult_to_ugt:343; SDAG: ; %bb.0: ; %entry344; SDAG-NEXT: s_cmp_nle_f16 s2, 0x4000345; SDAG-NEXT: v_mov_b32_e32 v0, 0346; SDAG-NEXT: s_cselect_b32 s2, -1, 0347; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)348; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2349; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]350; SDAG-NEXT: s_endpgm351;352; GISEL-LABEL: fcmp_f16_ult_to_ugt:353; GISEL: ; %bb.0: ; %entry354; GISEL-NEXT: s_cmp_nle_f16 s2, 0x4000355; GISEL-NEXT: v_mov_b32_e32 v1, 0356; GISEL-NEXT: s_cselect_b32 s2, 1, 0357; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)358; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000359; GISEL-NEXT: v_mov_b32_e32 v0, s2360; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]361; GISEL-NEXT: s_endpgm362entry:363 %0 = fcmp ult half 2.0, %a364 %1 = sext i1 %0 to i32365 store i32 %1, ptr addrspace(1) %out366 ret void367}368 369define amdgpu_vs void @fcmp_f16_ugt_to_ult(ptr addrspace(1) inreg %out, half inreg %a) {370; SDAG-LABEL: fcmp_f16_ugt_to_ult:371; SDAG: ; %bb.0: ; %entry372; SDAG-NEXT: s_cmp_nge_f16 s2, 0x4000373; SDAG-NEXT: v_mov_b32_e32 v0, 0374; SDAG-NEXT: s_cselect_b32 s2, -1, 0375; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)376; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2377; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]378; SDAG-NEXT: s_endpgm379;380; GISEL-LABEL: fcmp_f16_ugt_to_ult:381; GISEL: ; %bb.0: ; %entry382; GISEL-NEXT: s_cmp_nge_f16 s2, 0x4000383; GISEL-NEXT: v_mov_b32_e32 v1, 0384; GISEL-NEXT: s_cselect_b32 s2, 1, 0385; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)386; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000387; GISEL-NEXT: v_mov_b32_e32 v0, s2388; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]389; GISEL-NEXT: s_endpgm390entry:391 %0 = fcmp ugt half 2.0, %a392 %1 = sext i1 %0 to i32393 store i32 %1, ptr addrspace(1) %out394 ret void395}396 397define amdgpu_vs void @fcmp_ule_to_uge(ptr addrspace(1) inreg %out, half inreg %a) {398; SDAG-LABEL: fcmp_ule_to_uge:399; SDAG: ; %bb.0: ; %entry400; SDAG-NEXT: s_cmp_nlt_f16 s2, 0x4000401; SDAG-NEXT: v_mov_b32_e32 v0, 0402; SDAG-NEXT: s_cselect_b32 s2, -1, 0403; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)404; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2405; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]406; SDAG-NEXT: s_endpgm407;408; GISEL-LABEL: fcmp_ule_to_uge:409; GISEL: ; %bb.0: ; %entry410; GISEL-NEXT: s_cmp_nlt_f16 s2, 0x4000411; GISEL-NEXT: v_mov_b32_e32 v1, 0412; GISEL-NEXT: s_cselect_b32 s2, 1, 0413; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)414; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000415; GISEL-NEXT: v_mov_b32_e32 v0, s2416; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]417; GISEL-NEXT: s_endpgm418entry:419 %0 = fcmp ule half 2.0, %a420 %1 = sext i1 %0 to i32421 store i32 %1, ptr addrspace(1) %out422 ret void423}424 425define amdgpu_vs void @fcmp_uge_to_ule(ptr addrspace(1) inreg %out, half inreg %a) {426; SDAG-LABEL: fcmp_uge_to_ule:427; SDAG: ; %bb.0: ; %entry428; SDAG-NEXT: s_cmp_ngt_f16 s2, 0x4000429; SDAG-NEXT: v_mov_b32_e32 v0, 0430; SDAG-NEXT: s_cselect_b32 s2, -1, 0431; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)432; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2433; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]434; SDAG-NEXT: s_endpgm435;436; GISEL-LABEL: fcmp_uge_to_ule:437; GISEL: ; %bb.0: ; %entry438; GISEL-NEXT: s_cmp_ngt_f16 s2, 0x4000439; GISEL-NEXT: v_mov_b32_e32 v1, 0440; GISEL-NEXT: s_cselect_b32 s2, 1, 0441; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)442; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000443; GISEL-NEXT: v_mov_b32_e32 v0, s2444; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]445; GISEL-NEXT: s_endpgm446entry:447 %0 = fcmp uge half 2.0, %a448 %1 = sext i1 %0 to i32449 store i32 %1, ptr addrspace(1) %out450 ret void451}452