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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=verde < %s | FileCheck -check-prefix=SI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI %s4 5define amdgpu_ps float @main(float %arg0, float %arg1) #0 {6; SI-LABEL: main:7; SI: ; %bb.0: ; %bb8; SI-NEXT: image_load v2, v0, s[0:7] dmask:0x1 unorm9; SI-NEXT: v_cvt_i32_f32_e32 v0, v010; SI-NEXT: v_and_b32_e32 v0, 7, v011; SI-NEXT: s_waitcnt vmcnt(0)12; SI-NEXT: v_lshrrev_b32_e32 v0, v0, v213; SI-NEXT: v_and_b32_e32 v0, 1, v014; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v015; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc16; SI-NEXT: v_cvt_pkrtz_f16_f32_e32 v0, s0, v017; SI-NEXT: ; return to shader part epilog18;19; VI-LABEL: main:20; VI: ; %bb.0: ; %bb21; VI-NEXT: image_load v2, v0, s[0:7] dmask:0x1 unorm22; VI-NEXT: v_cvt_i32_f32_e32 v0, v023; VI-NEXT: v_and_b32_e32 v0, 7, v024; VI-NEXT: s_waitcnt vmcnt(0)25; VI-NEXT: v_lshrrev_b32_e32 v0, v0, v226; VI-NEXT: v_and_b32_e32 v0, 1, v027; VI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v028; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc29; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, s0, v030; VI-NEXT: ; return to shader part epilog31bb:32 %tmp = fptosi float %arg0 to i3233 %tmp1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 poison, <8 x i32> poison, i32 0, i32 0)34 %tmp2.f = extractelement <4 x float> %tmp1, i32 035 %tmp2 = bitcast float %tmp2.f to i3236 %tmp3 = and i32 %tmp, 737 %tmp4 = shl i32 1, %tmp338 %tmp5 = and i32 %tmp2, %tmp439 %tmp6 = icmp eq i32 %tmp5, 040 %tmp7 = select i1 %tmp6, float 0.000000e+00, float %arg141 %tmp8 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float poison, float %tmp7)42 %tmp9 = bitcast <2 x half> %tmp8 to float43 ret float %tmp944}45 46declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #147declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32, i32, <8 x i32>, i32, i32) #248 49attributes #0 = { nounwind }50attributes #1 = { nounwind readnone }51attributes #2 = { nounwind readonly }52