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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - -amdgpu-codegenprepare-mul24=0 < %s | FileCheck -check-prefix=GFX9 %s3 4define i16 @num_sign_bits_mul_i48_0(i8 %X, i8 %Y, i8 %Z, i8 %W) {5; GFX9-LABEL: num_sign_bits_mul_i48_0:6; GFX9: ; %bb.0:7; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8; GFX9-NEXT: v_mul_i32_i24_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_09; GFX9-NEXT: v_mul_i32_i24_sdwa v1, sext(v2), sext(v3) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_010; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v111; GFX9-NEXT: s_setpc_b64 s[30:31]12 %A = sext i8 %X to i4813 %B = sext i8 %Y to i4814 %C = sext i8 %Z to i4815 %D = sext i8 %W to i4816 %mul0 = mul i48 %A, %B17 %mul1 = mul i48 %C, %D18 %mul2 = mul i48 %mul0, %mul119 %trunc = trunc i48 %mul2 to i1620 ret i16 %trunc21}22 23define i16 @num_sign_bits_mul_i48_1(i8 %X, i8 %Y, i8 %Z, i8 %W) {24; GFX9-LABEL: num_sign_bits_mul_i48_1:25; GFX9: ; %bb.0:26; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)27; GFX9-NEXT: v_mul_i32_i24_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_028; GFX9-NEXT: v_mul_i32_i24_sdwa v2, sext(v2), sext(v3) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_029; GFX9-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v230; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v231; GFX9-NEXT: v_lshrrev_b64 v[0:1], 24, v[0:1]32; GFX9-NEXT: s_setpc_b64 s[30:31]33 %A = sext i8 %X to i4834 %B = sext i8 %Y to i4835 %C = sext i8 %Z to i4836 %D = sext i8 %W to i4837 %mul0 = mul i48 %A, %B38 %mul1 = mul i48 %C, %D39 %mul2 = mul i48 %mul0, %mul140 %ashr = ashr i48 %mul2, 2441 %trunc = trunc i48 %ashr to i1642 ret i16 %trunc43}44 45define i32 @num_sign_bits_mul_i32_7(i32 %x, i32 %y, i32 %z, i32 %w) {46; GFX9-LABEL: num_sign_bits_mul_i32_7:47; GFX9: ; %bb.0:48; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)49; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 2550; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 2551; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 2552; GFX9-NEXT: v_bfe_i32 v3, v3, 0, 2553; GFX9-NEXT: v_mul_lo_u32 v0, v0, v154; GFX9-NEXT: v_mul_lo_u32 v1, v2, v355; GFX9-NEXT: v_mul_lo_u32 v0, v0, v156; GFX9-NEXT: s_setpc_b64 s[30:31]57 %x.shl = shl i32 %x, 758 %x.bits = ashr i32 %x.shl, 759 60 %y.shl = shl i32 %y, 761 %y.bits = ashr i32 %y.shl, 762 63 %z.shl = shl i32 %z, 764 %z.bits = ashr i32 %z.shl, 765 66 %w.shl = shl i32 %w, 767 %w.bits = ashr i32 %w.shl, 768 69 %mul0 = mul i32 %x.bits, %y.bits70 %mul1 = mul i32 %z.bits, %w.bits71 %mul2 = mul i32 %mul0, %mul172 ret i32 %mul273}74 75define i32 @num_sign_bits_mul_i32_8(i32 %x, i32 %y, i32 %z, i32 %w) {76; GFX9-LABEL: num_sign_bits_mul_i32_8:77; GFX9: ; %bb.0:78; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)79; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v180; GFX9-NEXT: v_mul_i32_i24_e32 v1, v2, v381; GFX9-NEXT: v_mul_lo_u32 v0, v0, v182; GFX9-NEXT: s_setpc_b64 s[30:31]83 %x.shl = shl i32 %x, 884 %x.bits = ashr i32 %x.shl, 885 86 %y.shl = shl i32 %y, 887 %y.bits = ashr i32 %y.shl, 888 89 %z.shl = shl i32 %z, 890 %z.bits = ashr i32 %z.shl, 891 92 %w.shl = shl i32 %w, 893 %w.bits = ashr i32 %w.shl, 894 95 %mul0 = mul i32 %x.bits, %y.bits96 %mul1 = mul i32 %z.bits, %w.bits97 %mul2 = mul i32 %mul0, %mul198 ret i32 %mul299}100 101define i32 @num_sign_bits_mul_i32_9(i32 %x, i32 %y, i32 %z, i32 %w) {102; GFX9-LABEL: num_sign_bits_mul_i32_9:103; GFX9: ; %bb.0:104; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)105; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 23106; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 23107; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 23108; GFX9-NEXT: v_bfe_i32 v3, v3, 0, 23109; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v1110; GFX9-NEXT: v_mul_i32_i24_e32 v1, v2, v3111; GFX9-NEXT: v_mul_lo_u32 v0, v0, v1112; GFX9-NEXT: s_setpc_b64 s[30:31]113 %x.shl = shl i32 %x, 9114 %x.bits = ashr i32 %x.shl, 9115 116 %y.shl = shl i32 %y, 9117 %y.bits = ashr i32 %y.shl, 9118 119 %z.shl = shl i32 %z, 9120 %z.bits = ashr i32 %z.shl, 9121 122 %w.shl = shl i32 %w, 9123 %w.bits = ashr i32 %w.shl, 9124 125 %mul0 = mul i32 %x.bits, %y.bits126 %mul1 = mul i32 %z.bits, %w.bits127 %mul2 = mul i32 %mul0, %mul1128 ret i32 %mul2129}130 131define i32 @num_sign_bits_mul_i32_10(i32 %x, i32 %y, i32 %z, i32 %w) {132; GFX9-LABEL: num_sign_bits_mul_i32_10:133; GFX9: ; %bb.0:134; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)135; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 22136; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 22137; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 22138; GFX9-NEXT: v_bfe_i32 v3, v3, 0, 22139; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v1140; GFX9-NEXT: v_mul_i32_i24_e32 v1, v2, v3141; GFX9-NEXT: v_mul_lo_u32 v0, v0, v1142; GFX9-NEXT: s_setpc_b64 s[30:31]143 %x.shl = shl i32 %x, 10144 %x.bits = ashr i32 %x.shl, 10145 146 %y.shl = shl i32 %y, 10147 %y.bits = ashr i32 %y.shl, 10148 149 %z.shl = shl i32 %z, 10150 %z.bits = ashr i32 %z.shl, 10151 152 %w.shl = shl i32 %w, 10153 %w.bits = ashr i32 %w.shl, 10154 155 %mul0 = mul i32 %x.bits, %y.bits156 %mul1 = mul i32 %z.bits, %w.bits157 %mul2 = mul i32 %mul0, %mul1158 ret i32 %mul2159}160 161define i32 @known_bits_mul24() {162; GFX9-LABEL: known_bits_mul24:163; GFX9: ; %bb.0:164; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)165; GFX9-NEXT: v_mov_b32_e32 v0, 0166; GFX9-NEXT: s_setpc_b64 s[30:31]167 %r0 = call i32 @llvm.amdgcn.mul.i24(i32 0, i32 -7)168 %r1 = shl i32 %r0, 2169 ret i32 %r1170}171 172declare i32 @llvm.amdgcn.mul.i24(i32, i32)173