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1; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope --check-prefix=GCN %s2; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GCN,VI %s3 4; GCN-LABEL: {{^}}test_concat_v1i32:5; 0x80f000 is the high 32 bits of the resource descriptor used by MUBUF6; instructions that access scratch memory. Bit 23, which is the add_tid_enable7; bit, is only set for scratch access, so we can check for the absence of this8; value if we want to ensure scratch memory is not being used.9; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f00010; GCN-NOT: movrel11define amdgpu_kernel void @test_concat_v1i32(ptr addrspace(1) %out, <1 x i32> %a, <1 x i32> %b) nounwind {12 %concat = shufflevector <1 x i32> %a, <1 x i32> %b, <2 x i32> <i32 0, i32 1>13 store <2 x i32> %concat, ptr addrspace(1) %out, align 814 ret void15}16 17; GCN-LABEL: {{^}}test_concat_v2i32:18; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f00019; GCN-NOT: movrel20define amdgpu_kernel void @test_concat_v2i32(ptr addrspace(1) %out, <2 x i32> %a, <2 x i32> %b) nounwind {21 %concat = shufflevector <2 x i32> %a, <2 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>22 store <4 x i32> %concat, ptr addrspace(1) %out, align 1623 ret void24}25 26; GCN-LABEL: {{^}}test_concat_v4i32:27; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f00028; GCN-NOT: movrel29define amdgpu_kernel void @test_concat_v4i32(ptr addrspace(1) %out, <4 x i32> %a, <4 x i32> %b) nounwind {30 %concat = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>31 store <8 x i32> %concat, ptr addrspace(1) %out, align 3232 ret void33}34 35; GCN-LABEL: {{^}}test_concat_v8i32:36; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f00037; GCN-NOT: movrel38define amdgpu_kernel void @test_concat_v8i32(ptr addrspace(1) %out, <8 x i32> %a, <8 x i32> %b) nounwind {39 %concat = shufflevector <8 x i32> %a, <8 x i32> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>40 store <16 x i32> %concat, ptr addrspace(1) %out, align 6441 ret void42}43 44; GCN-LABEL: {{^}}test_concat_v16i32:45; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f00046; GCN-NOT: movrel47define amdgpu_kernel void @test_concat_v16i32(ptr addrspace(1) %out, <16 x i32> %a, <16 x i32> %b) nounwind {48 %concat = shufflevector <16 x i32> %a, <16 x i32> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>49 store <32 x i32> %concat, ptr addrspace(1) %out, align 12850 ret void51}52 53; GCN-LABEL: {{^}}test_concat_v1f32:54; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f00055; GCN-NOT: movrel56define amdgpu_kernel void @test_concat_v1f32(ptr addrspace(1) %out, <1 x float> %a, <1 x float> %b) nounwind {57 %concat = shufflevector <1 x float> %a, <1 x float> %b, <2 x i32> <i32 0, i32 1>58 store <2 x float> %concat, ptr addrspace(1) %out, align 859 ret void60}61 62; GCN-LABEL: {{^}}test_concat_v2f32:63; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f00064; GCN-NOT: movrel65define amdgpu_kernel void @test_concat_v2f32(ptr addrspace(1) %out, <2 x float> %a, <2 x float> %b) nounwind {66 %concat = shufflevector <2 x float> %a, <2 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>67 store <4 x float> %concat, ptr addrspace(1) %out, align 1668 ret void69}70 71; GCN-LABEL: {{^}}test_concat_v4f32:72; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f00073; GCN-NOT: movrel74define amdgpu_kernel void @test_concat_v4f32(ptr addrspace(1) %out, <4 x float> %a, <4 x float> %b) nounwind {75 %concat = shufflevector <4 x float> %a, <4 x float> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>76 store <8 x float> %concat, ptr addrspace(1) %out, align 3277 ret void78}79 80; GCN-LABEL: {{^}}test_concat_v8f32:81; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f00082; GCN-NOT: movrel83define amdgpu_kernel void @test_concat_v8f32(ptr addrspace(1) %out, <8 x float> %a, <8 x float> %b) nounwind {84 %concat = shufflevector <8 x float> %a, <8 x float> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>85 store <16 x float> %concat, ptr addrspace(1) %out, align 6486 ret void87}88 89; GCN-LABEL: {{^}}test_concat_v16f32:90; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f00091; GCN-NOT: movrel92define amdgpu_kernel void @test_concat_v16f32(ptr addrspace(1) %out, <16 x float> %a, <16 x float> %b) nounwind {93 %concat = shufflevector <16 x float> %a, <16 x float> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>94 store <32 x float> %concat, ptr addrspace(1) %out, align 12895 ret void96}97 98; GCN-LABEL: {{^}}test_concat_v1i64:99; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000100; GCN-NOT: movrel101define amdgpu_kernel void @test_concat_v1i64(ptr addrspace(1) %out, <1 x double> %a, <1 x double> %b) nounwind {102 %concat = shufflevector <1 x double> %a, <1 x double> %b, <2 x i32> <i32 0, i32 1>103 store <2 x double> %concat, ptr addrspace(1) %out, align 16104 ret void105}106 107; GCN-LABEL: {{^}}test_concat_v2i64:108; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000109; GCN-NOT: movrel110define amdgpu_kernel void @test_concat_v2i64(ptr addrspace(1) %out, <2 x double> %a, <2 x double> %b) nounwind {111 %concat = shufflevector <2 x double> %a, <2 x double> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>112 store <4 x double> %concat, ptr addrspace(1) %out, align 32113 ret void114}115 116; GCN-LABEL: {{^}}test_concat_v4i64:117; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000118; GCN-NOT: movrel119define amdgpu_kernel void @test_concat_v4i64(ptr addrspace(1) %out, <4 x double> %a, <4 x double> %b) nounwind {120 %concat = shufflevector <4 x double> %a, <4 x double> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>121 store <8 x double> %concat, ptr addrspace(1) %out, align 64122 ret void123}124 125; GCN-LABEL: {{^}}test_concat_v8i64:126; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000127; GCN-NOT: movrel128define amdgpu_kernel void @test_concat_v8i64(ptr addrspace(1) %out, <8 x double> %a, <8 x double> %b) nounwind {129 %concat = shufflevector <8 x double> %a, <8 x double> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>130 store <16 x double> %concat, ptr addrspace(1) %out, align 128131 ret void132}133 134; GCN-LABEL: {{^}}test_concat_v16i64:135; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000136; GCN-NOT: movrel137define amdgpu_kernel void @test_concat_v16i64(ptr addrspace(1) %out, <16 x double> %a, <16 x double> %b) nounwind {138 %concat = shufflevector <16 x double> %a, <16 x double> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>139 store <32 x double> %concat, ptr addrspace(1) %out, align 256140 ret void141}142 143; GCN-LABEL: {{^}}test_concat_v1f64:144; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000145; GCN-NOT: movrel146define amdgpu_kernel void @test_concat_v1f64(ptr addrspace(1) %out, <1 x double> %a, <1 x double> %b) nounwind {147 %concat = shufflevector <1 x double> %a, <1 x double> %b, <2 x i32> <i32 0, i32 1>148 store <2 x double> %concat, ptr addrspace(1) %out, align 16149 ret void150}151 152; GCN-LABEL: {{^}}test_concat_v2f64:153; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000154; GCN-NOT: movrel155define amdgpu_kernel void @test_concat_v2f64(ptr addrspace(1) %out, <2 x double> %a, <2 x double> %b) nounwind {156 %concat = shufflevector <2 x double> %a, <2 x double> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>157 store <4 x double> %concat, ptr addrspace(1) %out, align 32158 ret void159}160 161; GCN-LABEL: {{^}}test_concat_v4f64:162; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000163; GCN-NOT: movrel164define amdgpu_kernel void @test_concat_v4f64(ptr addrspace(1) %out, <4 x double> %a, <4 x double> %b) nounwind {165 %concat = shufflevector <4 x double> %a, <4 x double> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>166 store <8 x double> %concat, ptr addrspace(1) %out, align 64167 ret void168}169 170; GCN-LABEL: {{^}}test_concat_v8f64:171; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000172; GCN-NOT: movrel173define amdgpu_kernel void @test_concat_v8f64(ptr addrspace(1) %out, <8 x double> %a, <8 x double> %b) nounwind {174 %concat = shufflevector <8 x double> %a, <8 x double> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>175 store <16 x double> %concat, ptr addrspace(1) %out, align 128176 ret void177}178 179; GCN-LABEL: {{^}}test_concat_v16f64:180; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000181; GCN-NOT: movrel182define amdgpu_kernel void @test_concat_v16f64(ptr addrspace(1) %out, <16 x double> %a, <16 x double> %b) nounwind {183 %concat = shufflevector <16 x double> %a, <16 x double> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>184 store <32 x double> %concat, ptr addrspace(1) %out, align 256185 ret void186}187 188; GCN-LABEL: {{^}}test_concat_v1i1:189; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000190; GCN-NOT: movrel191define amdgpu_kernel void @test_concat_v1i1(ptr addrspace(1) %out, <1 x i1> %a, <1 x i1> %b) nounwind {192 %concat = shufflevector <1 x i1> %a, <1 x i1> %b, <2 x i32> <i32 0, i32 1>193 store <2 x i1> %concat, ptr addrspace(1) %out194 ret void195}196 197; GCN-LABEL: {{^}}test_concat_v2i1:198; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000199; GCN-NOT: movrel200define amdgpu_kernel void @test_concat_v2i1(ptr addrspace(1) %out, <2 x i1> %a, <2 x i1> %b) nounwind {201 %concat = shufflevector <2 x i1> %a, <2 x i1> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>202 store <4 x i1> %concat, ptr addrspace(1) %out203 ret void204}205 206; GCN-LABEL: {{^}}test_concat_v4i1:207; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000208; GCN-NOT: movrel209define amdgpu_kernel void @test_concat_v4i1(ptr addrspace(1) %out, <4 x i1> %a, <4 x i1> %b) nounwind {210 %concat = shufflevector <4 x i1> %a, <4 x i1> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>211 store <8 x i1> %concat, ptr addrspace(1) %out212 ret void213}214 215; GCN-LABEL: {{^}}test_concat_v8i1:216; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000217; GCN-NOT: movrel218define amdgpu_kernel void @test_concat_v8i1(ptr addrspace(1) %out, <8 x i1> %a, <8 x i1> %b) nounwind {219 %concat = shufflevector <8 x i1> %a, <8 x i1> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>220 store <16 x i1> %concat, ptr addrspace(1) %out221 ret void222}223 224; GCN-LABEL: {{^}}test_concat_v16i1:225; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000226; GCN-NOT: movrel227define amdgpu_kernel void @test_concat_v16i1(ptr addrspace(1) %out, <16 x i1> %a, <16 x i1> %b) nounwind {228 %concat = shufflevector <16 x i1> %a, <16 x i1> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>229 store <32 x i1> %concat, ptr addrspace(1) %out230 ret void231}232 233; GCN-LABEL: {{^}}test_concat_v32i1:234; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000235; GCN-NOT: movrel236define amdgpu_kernel void @test_concat_v32i1(ptr addrspace(1) %out, <32 x i1> %a, <32 x i1> %b) nounwind {237 %concat = shufflevector <32 x i1> %a, <32 x i1> %b, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>238 store <64 x i1> %concat, ptr addrspace(1) %out239 ret void240}241 242; GCN-LABEL: {{^}}test_concat_v1i16:243; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000244; GCN-NOT: movrel245define amdgpu_kernel void @test_concat_v1i16(ptr addrspace(1) %out, <1 x i16> %a, <1 x i16> %b) nounwind {246 %concat = shufflevector <1 x i16> %a, <1 x i16> %b, <2 x i32> <i32 0, i32 1>247 store <2 x i16> %concat, ptr addrspace(1) %out, align 4248 ret void249}250 251; GCN-LABEL: {{^}}test_concat_v2i16:252; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000253; GCN-NOT: movrel254define amdgpu_kernel void @test_concat_v2i16(ptr addrspace(1) %out, <2 x i16> %a, <2 x i16> %b) nounwind {255 %concat = shufflevector <2 x i16> %a, <2 x i16> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>256 store <4 x i16> %concat, ptr addrspace(1) %out, align 8257 ret void258}259 260; GCN-LABEL: {{^}}test_concat_v4i16:261; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000262; GCN-NOT: movrel263define amdgpu_kernel void @test_concat_v4i16(ptr addrspace(1) %out, <4 x i16> %a, <4 x i16> %b) nounwind {264 %concat = shufflevector <4 x i16> %a, <4 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>265 store <8 x i16> %concat, ptr addrspace(1) %out, align 16266 ret void267}268 269; GCN-LABEL: {{^}}test_concat_v8i16:270; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000271; GCN-NOT: movrel272define amdgpu_kernel void @test_concat_v8i16(ptr addrspace(1) %out, <8 x i16> %a, <8 x i16> %b) nounwind {273 %concat = shufflevector <8 x i16> %a, <8 x i16> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>274 store <16 x i16> %concat, ptr addrspace(1) %out, align 32275 ret void276}277 278; GCN-LABEL: {{^}}test_concat_v16i16:279; GCN-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000280; GCN-NOT: movrel281define amdgpu_kernel void @test_concat_v16i16(ptr addrspace(1) %out, <16 x i16> %a, <16 x i16> %b) nounwind {282 %concat = shufflevector <16 x i16> %a, <16 x i16> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>283 store <32 x i16> %concat, ptr addrspace(1) %out, align 64284 ret void285}286 287; GCN-LABEL: {{^}}concat_vector_crash:288; GCN: s_endpgm289define amdgpu_kernel void @concat_vector_crash(ptr addrspace(1) %out, ptr addrspace(1) %in) {290bb:291 %tmp = load <2 x float>, ptr addrspace(1) %in, align 4292 %tmp1 = shufflevector <2 x float> %tmp, <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>293 %tmp2 = shufflevector <8 x float> poison, <8 x float> %tmp1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>294 store <8 x float> %tmp2, ptr addrspace(1) %out, align 32295 ret void296}297 298; GCN-LABEL: {{^}}concat_vector_crash2:299; GCN: s_endpgm300define amdgpu_kernel void @concat_vector_crash2(ptr addrspace(1) %out, ptr addrspace(1) %in) {301 %tmp = load i32, ptr addrspace(1) %in, align 1302 %tmp1 = trunc i32 %tmp to i24303 %tmp2 = bitcast i24 %tmp1 to <3 x i8>304 %tmp3 = shufflevector <3 x i8> %tmp2, <3 x i8> poison, <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 1, i32 poison, i32 poison>305 %tmp4 = shufflevector <8 x i8> %tmp3, <8 x i8> <i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 7, i8 8>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 14, i32 15>306 store <8 x i8> %tmp4, ptr addrspace(1) %out, align 8307 ret void308}309 310; GCN-LABEL: {{^}}build_vector_splat_concat_v8i16:311; VI: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}}312; VI: ds_write_b128313; VI: ds_write_b128314define amdgpu_kernel void @build_vector_splat_concat_v8i16() {315entry:316 store <8 x i16> zeroinitializer, ptr addrspace(3) poison, align 16317 store <8 x i16> zeroinitializer, ptr addrspace(3) null, align 16318 ret void319}320