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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel < %s | FileCheck -check-prefix=GISEL %s4 5define i16 @csh_16(i16 %a, i16 %b) {6; CHECK-LABEL: csh_16:7; CHECK: ; %bb.0:8; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9; CHECK-NEXT: v_lshlrev_b16_e32 v2, v1, v010; CHECK-NEXT: v_lshrrev_b16_e32 v3, v1, v011; CHECK-NEXT: v_ashrrev_i16_e32 v0, v1, v012; CHECK-NEXT: v_add_u16_e32 v1, v2, v313; CHECK-NEXT: v_add_u16_e32 v0, v1, v014; CHECK-NEXT: s_setpc_b64 s[30:31]15;16; GISEL-LABEL: csh_16:17; GISEL: ; %bb.0:18; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)19; GISEL-NEXT: v_and_b32_e32 v1, 15, v120; GISEL-NEXT: v_lshlrev_b16_e32 v2, v1, v021; GISEL-NEXT: v_lshrrev_b16_e32 v3, v1, v022; GISEL-NEXT: v_ashrrev_i16_e32 v0, v1, v023; GISEL-NEXT: v_add_u16_e32 v1, v2, v324; GISEL-NEXT: v_add_u16_e32 v0, v1, v025; GISEL-NEXT: s_setpc_b64 s[30:31]26 %and = and i16 %b, 1527 %shl = shl i16 %a, %and28 %lshr = lshr i16 %a, %and29 %ashr = ashr i16 %a, %and30 %ret.0 = add i16 %shl, %lshr31 %ret = add i16 %ret.0, %ashr32 ret i16 %ret33}34 35define i32 @csh_32(i32 %a, i32 %b) {36; CHECK-LABEL: csh_32:37; CHECK: ; %bb.0:38; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)39; CHECK-NEXT: v_lshlrev_b32_e32 v2, v1, v040; CHECK-NEXT: v_lshrrev_b32_e32 v3, v1, v041; CHECK-NEXT: v_ashrrev_i32_e32 v0, v1, v042; CHECK-NEXT: v_add3_u32 v0, v2, v3, v043; CHECK-NEXT: s_setpc_b64 s[30:31]44;45; GISEL-LABEL: csh_32:46; GISEL: ; %bb.0:47; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)48; GISEL-NEXT: v_and_b32_e32 v1, 31, v149; GISEL-NEXT: v_lshlrev_b32_e32 v2, v1, v050; GISEL-NEXT: v_lshrrev_b32_e32 v3, v1, v051; GISEL-NEXT: v_ashrrev_i32_e32 v0, v1, v052; GISEL-NEXT: v_add3_u32 v0, v2, v3, v053; GISEL-NEXT: s_setpc_b64 s[30:31]54 %and = and i32 %b, 3155 %shl = shl i32 %a, %and56 %lshr = lshr i32 %a, %and57 %ashr = ashr i32 %a, %and58 %ret.0 = add i32 %shl, %lshr59 %ret = add i32 %ret.0, %ashr60 ret i32 %ret61}62 63define amdgpu_ps i32 @s_csh_32_0(i32 inreg %a, i32 inreg %b) {64; CHECK-LABEL: s_csh_32_0:65; CHECK: ; %bb.0:66; CHECK-NEXT: s_lshl_b32 s2, s0, s167; CHECK-NEXT: s_lshr_b32 s3, s0, s168; CHECK-NEXT: s_ashr_i32 s0, s0, s169; CHECK-NEXT: s_add_i32 s1, s2, s370; CHECK-NEXT: s_add_i32 s0, s1, s071; CHECK-NEXT: ; return to shader part epilog72;73; GISEL-LABEL: s_csh_32_0:74; GISEL: ; %bb.0:75; GISEL-NEXT: s_lshl_b32 s2, s0, s176; GISEL-NEXT: s_lshr_b32 s3, s0, s177; GISEL-NEXT: s_ashr_i32 s0, s0, s178; GISEL-NEXT: s_add_i32 s1, s2, s379; GISEL-NEXT: s_add_i32 s0, s1, s080; GISEL-NEXT: ; return to shader part epilog81 %and = and i32 %b, 3182 %shl = shl i32 %a, %and83 %lshr = lshr i32 %a, %and84 %ashr = ashr i32 %a, %and85 %ret.0 = add i32 %shl, %lshr86 %ret = add i32 %ret.0, %ashr87 ret i32 %ret88}89 90define amdgpu_ps i32 @s_csh_32_1(i32 inreg %a, i32 inreg %b) {91; CHECK-LABEL: s_csh_32_1:92; CHECK: ; %bb.0:93; CHECK-NEXT: s_lshl_b32 s2, s0, s194; CHECK-NEXT: s_lshr_b32 s3, s0, s195; CHECK-NEXT: s_ashr_i32 s0, s0, s196; CHECK-NEXT: s_add_i32 s1, s2, s397; CHECK-NEXT: s_add_i32 s0, s1, s098; CHECK-NEXT: ; return to shader part epilog99;100; GISEL-LABEL: s_csh_32_1:101; GISEL: ; %bb.0:102; GISEL-NEXT: s_lshl_b32 s2, s0, s1103; GISEL-NEXT: s_lshr_b32 s3, s0, s1104; GISEL-NEXT: s_ashr_i32 s0, s0, s1105; GISEL-NEXT: s_add_i32 s1, s2, s3106; GISEL-NEXT: s_add_i32 s0, s1, s0107; GISEL-NEXT: ; return to shader part epilog108 %and = and i32 %b, 127109 %shl = shl i32 %a, %and110 %lshr = lshr i32 %a, %and111 %ashr = ashr i32 %a, %and112 %ret.0 = add i32 %shl, %lshr113 %ret = add i32 %ret.0, %ashr114 ret i32 %ret115}116 117define <4 x i32> @csh_v4i32(<4 x i32> %a, <4 x i32> %b) {118; CHECK-LABEL: csh_v4i32:119; CHECK: ; %bb.0:120; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)121; CHECK-NEXT: v_lshlrev_b32_e32 v8, v7, v3122; CHECK-NEXT: v_lshlrev_b32_e32 v9, v6, v2123; CHECK-NEXT: v_lshlrev_b32_e32 v10, v5, v1124; CHECK-NEXT: v_lshlrev_b32_e32 v11, v4, v0125; CHECK-NEXT: v_lshrrev_b32_e32 v12, v7, v3126; CHECK-NEXT: v_lshrrev_b32_e32 v13, v6, v2127; CHECK-NEXT: v_lshrrev_b32_e32 v14, v5, v1128; CHECK-NEXT: v_lshrrev_b32_e32 v15, v4, v0129; CHECK-NEXT: v_ashrrev_i32_e32 v3, v7, v3130; CHECK-NEXT: v_ashrrev_i32_e32 v2, v6, v2131; CHECK-NEXT: v_ashrrev_i32_e32 v1, v5, v1132; CHECK-NEXT: v_ashrrev_i32_e32 v0, v4, v0133; CHECK-NEXT: v_add3_u32 v0, v11, v15, v0134; CHECK-NEXT: v_add3_u32 v1, v10, v14, v1135; CHECK-NEXT: v_add3_u32 v2, v9, v13, v2136; CHECK-NEXT: v_add3_u32 v3, v8, v12, v3137; CHECK-NEXT: s_setpc_b64 s[30:31]138;139; GISEL-LABEL: csh_v4i32:140; GISEL: ; %bb.0:141; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)142; GISEL-NEXT: v_lshlrev_b32_e32 v8, v4, v0143; GISEL-NEXT: v_lshlrev_b32_e32 v9, v5, v1144; GISEL-NEXT: v_lshlrev_b32_e32 v10, v6, v2145; GISEL-NEXT: v_lshlrev_b32_e32 v11, v7, v3146; GISEL-NEXT: v_lshrrev_b32_e32 v12, v4, v0147; GISEL-NEXT: v_lshrrev_b32_e32 v13, v5, v1148; GISEL-NEXT: v_lshrrev_b32_e32 v14, v6, v2149; GISEL-NEXT: v_lshrrev_b32_e32 v15, v7, v3150; GISEL-NEXT: v_ashrrev_i32_e32 v0, v4, v0151; GISEL-NEXT: v_ashrrev_i32_e32 v1, v5, v1152; GISEL-NEXT: v_ashrrev_i32_e32 v2, v6, v2153; GISEL-NEXT: v_ashrrev_i32_e32 v3, v7, v3154; GISEL-NEXT: v_add3_u32 v0, v8, v12, v0155; GISEL-NEXT: v_add3_u32 v1, v9, v13, v1156; GISEL-NEXT: v_add3_u32 v2, v10, v14, v2157; GISEL-NEXT: v_add3_u32 v3, v11, v15, v3158; GISEL-NEXT: s_setpc_b64 s[30:31]159 %and = and <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>160 %shl = shl <4 x i32> %a, %and161 %lshr = lshr <4 x i32> %a, %and162 %ashr = ashr <4 x i32> %a, %and163 %ret.0 = add <4 x i32> %shl, %lshr164 %ret = add <4 x i32> %ret.0, %ashr165 ret <4 x i32> %ret166}167 168define amdgpu_ps <4 x i32> @s_csh_v4i32(<4 x i32> inreg %a, <4 x i32> inreg %b) {169; CHECK-LABEL: s_csh_v4i32:170; CHECK: ; %bb.0:171; CHECK-NEXT: s_lshl_b32 s8, s3, s7172; CHECK-NEXT: s_lshl_b32 s9, s2, s6173; CHECK-NEXT: s_lshl_b32 s10, s1, s5174; CHECK-NEXT: s_lshl_b32 s11, s0, s4175; CHECK-NEXT: s_lshr_b32 s12, s3, s7176; CHECK-NEXT: s_lshr_b32 s13, s2, s6177; CHECK-NEXT: s_lshr_b32 s14, s1, s5178; CHECK-NEXT: s_lshr_b32 s15, s0, s4179; CHECK-NEXT: s_ashr_i32 s0, s0, s4180; CHECK-NEXT: s_ashr_i32 s1, s1, s5181; CHECK-NEXT: s_ashr_i32 s2, s2, s6182; CHECK-NEXT: s_ashr_i32 s3, s3, s7183; CHECK-NEXT: s_add_i32 s4, s11, s15184; CHECK-NEXT: s_add_i32 s5, s10, s14185; CHECK-NEXT: s_add_i32 s6, s9, s13186; CHECK-NEXT: s_add_i32 s7, s8, s12187; CHECK-NEXT: s_add_i32 s3, s7, s3188; CHECK-NEXT: s_add_i32 s2, s6, s2189; CHECK-NEXT: s_add_i32 s1, s5, s1190; CHECK-NEXT: s_add_i32 s0, s4, s0191; CHECK-NEXT: ; return to shader part epilog192;193; GISEL-LABEL: s_csh_v4i32:194; GISEL: ; %bb.0:195; GISEL-NEXT: s_mov_b32 s8, 31196; GISEL-NEXT: s_mov_b32 s9, s8197; GISEL-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]198; GISEL-NEXT: s_and_b64 s[6:7], s[6:7], s[8:9]199; GISEL-NEXT: s_lshl_b32 s8, s0, s4200; GISEL-NEXT: s_lshl_b32 s9, s1, s5201; GISEL-NEXT: s_lshl_b32 s10, s2, s6202; GISEL-NEXT: s_lshl_b32 s11, s3, s7203; GISEL-NEXT: s_lshr_b32 s12, s0, s4204; GISEL-NEXT: s_lshr_b32 s13, s1, s5205; GISEL-NEXT: s_lshr_b32 s14, s2, s6206; GISEL-NEXT: s_lshr_b32 s15, s3, s7207; GISEL-NEXT: s_ashr_i32 s0, s0, s4208; GISEL-NEXT: s_ashr_i32 s1, s1, s5209; GISEL-NEXT: s_ashr_i32 s2, s2, s6210; GISEL-NEXT: s_ashr_i32 s3, s3, s7211; GISEL-NEXT: s_add_i32 s4, s8, s12212; GISEL-NEXT: s_add_i32 s5, s9, s13213; GISEL-NEXT: s_add_i32 s6, s10, s14214; GISEL-NEXT: s_add_i32 s7, s11, s15215; GISEL-NEXT: s_add_i32 s0, s4, s0216; GISEL-NEXT: s_add_i32 s1, s5, s1217; GISEL-NEXT: s_add_i32 s2, s6, s2218; GISEL-NEXT: s_add_i32 s3, s7, s3219; GISEL-NEXT: ; return to shader part epilog220 %and = and <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>221 %shl = shl <4 x i32> %a, %and222 %lshr = lshr <4 x i32> %a, %and223 %ashr = ashr <4 x i32> %a, %and224 %ret.0 = add <4 x i32> %shl, %lshr225 %ret = add <4 x i32> %ret.0, %ashr226 ret <4 x i32> %ret227}228 229define i64 @csh_64(i64 %a, i64 %b) {230; CHECK-LABEL: csh_64:231; CHECK: ; %bb.0:232; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)233; CHECK-NEXT: v_lshlrev_b64 v[3:4], v2, v[0:1]234; CHECK-NEXT: v_lshrrev_b64 v[5:6], v2, v[0:1]235; CHECK-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1]236; CHECK-NEXT: v_add_co_u32_e32 v2, vcc, v3, v5237; CHECK-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v6, vcc238; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0239; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v1, vcc240; CHECK-NEXT: s_setpc_b64 s[30:31]241;242; GISEL-LABEL: csh_64:243; GISEL: ; %bb.0:244; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)245; GISEL-NEXT: v_and_b32_e32 v6, 63, v2246; GISEL-NEXT: v_lshlrev_b64 v[2:3], v6, v[0:1]247; GISEL-NEXT: v_lshrrev_b64 v[4:5], v6, v[0:1]248; GISEL-NEXT: v_ashrrev_i64 v[0:1], v6, v[0:1]249; GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4250; GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v5, vcc251; GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0252; GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v1, vcc253; GISEL-NEXT: s_setpc_b64 s[30:31]254 %and = and i64 %b, 63255 %shl = shl i64 %a, %and256 %lshr = lshr i64 %a, %and257 %ashr = ashr i64 %a, %and258 %ret.0 = add i64 %shl, %lshr259 %ret = add i64 %ret.0, %ashr260 ret i64 %ret261}262 263define amdgpu_ps i64 @s_csh_64_0(i64 inreg %a, i64 inreg %b) {264; CHECK-LABEL: s_csh_64_0:265; CHECK: ; %bb.0:266; CHECK-NEXT: s_lshl_b64 s[4:5], s[0:1], s2267; CHECK-NEXT: s_lshr_b64 s[6:7], s[0:1], s2268; CHECK-NEXT: s_ashr_i64 s[0:1], s[0:1], s2269; CHECK-NEXT: s_add_u32 s2, s4, s6270; CHECK-NEXT: s_addc_u32 s3, s5, s7271; CHECK-NEXT: s_add_u32 s0, s2, s0272; CHECK-NEXT: s_addc_u32 s1, s3, s1273; CHECK-NEXT: ; return to shader part epilog274;275; GISEL-LABEL: s_csh_64_0:276; GISEL: ; %bb.0:277; GISEL-NEXT: s_lshl_b64 s[4:5], s[0:1], s2278; GISEL-NEXT: s_lshr_b64 s[6:7], s[0:1], s2279; GISEL-NEXT: s_ashr_i64 s[0:1], s[0:1], s2280; GISEL-NEXT: s_add_u32 s2, s4, s6281; GISEL-NEXT: s_addc_u32 s3, s5, s7282; GISEL-NEXT: s_add_u32 s0, s2, s0283; GISEL-NEXT: s_addc_u32 s1, s3, s1284; GISEL-NEXT: ; return to shader part epilog285 %and = and i64 %b, 63286 %shl = shl i64 %a, %and287 %lshr = lshr i64 %a, %and288 %ashr = ashr i64 %a, %and289 %ret.0 = add i64 %shl, %lshr290 %ret = add i64 %ret.0, %ashr291 ret i64 %ret292}293 294define amdgpu_ps i64 @s_csh_64_1(i64 inreg %a, i64 inreg %b) {295; CHECK-LABEL: s_csh_64_1:296; CHECK: ; %bb.0:297; CHECK-NEXT: s_lshl_b64 s[4:5], s[0:1], s2298; CHECK-NEXT: s_lshr_b64 s[6:7], s[0:1], s2299; CHECK-NEXT: s_ashr_i64 s[0:1], s[0:1], s2300; CHECK-NEXT: s_add_u32 s2, s4, s6301; CHECK-NEXT: s_addc_u32 s3, s5, s7302; CHECK-NEXT: s_add_u32 s0, s2, s0303; CHECK-NEXT: s_addc_u32 s1, s3, s1304; CHECK-NEXT: ; return to shader part epilog305;306; GISEL-LABEL: s_csh_64_1:307; GISEL: ; %bb.0:308; GISEL-NEXT: s_lshl_b64 s[4:5], s[0:1], s2309; GISEL-NEXT: s_lshr_b64 s[6:7], s[0:1], s2310; GISEL-NEXT: s_ashr_i64 s[0:1], s[0:1], s2311; GISEL-NEXT: s_add_u32 s2, s4, s6312; GISEL-NEXT: s_addc_u32 s3, s5, s7313; GISEL-NEXT: s_add_u32 s0, s2, s0314; GISEL-NEXT: s_addc_u32 s1, s3, s1315; GISEL-NEXT: ; return to shader part epilog316 %and = and i64 %b, 255317 %shl = shl i64 %a, %and318 %lshr = lshr i64 %a, %and319 %ashr = ashr i64 %a, %and320 %ret.0 = add i64 %shl, %lshr321 %ret = add i64 %ret.0, %ashr322 ret i64 %ret323}324 325define i32 @cshl_or(i32 %a, i32 %b) {326; CHECK-LABEL: cshl_or:327; CHECK: ; %bb.0:328; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)329; CHECK-NEXT: v_lshl_or_b32 v0, v0, v1, v0330; CHECK-NEXT: s_setpc_b64 s[30:31]331;332; GISEL-LABEL: cshl_or:333; GISEL: ; %bb.0:334; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)335; GISEL-NEXT: v_and_b32_e32 v1, 31, v1336; GISEL-NEXT: v_lshl_or_b32 v0, v0, v1, v0337; GISEL-NEXT: s_setpc_b64 s[30:31]338 %and = and i32 %b, 31339 %shl = shl i32 %a, %and340 %or = or i32 %shl, %a341 ret i32 %or342}343 344define i32 @cshl_add(i32 %a, i32 %b, i32 %c) {345; CHECK-LABEL: cshl_add:346; CHECK: ; %bb.0:347; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)348; CHECK-NEXT: v_lshl_add_u32 v0, v0, v1, v2349; CHECK-NEXT: s_setpc_b64 s[30:31]350;351; GISEL-LABEL: cshl_add:352; GISEL: ; %bb.0:353; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)354; GISEL-NEXT: v_and_b32_e32 v1, 31, v1355; GISEL-NEXT: v_lshl_add_u32 v0, v0, v1, v2356; GISEL-NEXT: s_setpc_b64 s[30:31]357 %and = and i32 %b, 31358 %shl = shl i32 %a, %and359 %add = add i32 %shl, %c360 ret i32 %add361}362 363define i32 @add_cshl(i32 %a, i32 %b) {364; CHECK-LABEL: add_cshl:365; CHECK: ; %bb.0:366; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)367; CHECK-NEXT: v_add_lshl_u32 v0, v0, v1, v1368; CHECK-NEXT: s_setpc_b64 s[30:31]369;370; GISEL-LABEL: add_cshl:371; GISEL: ; %bb.0:372; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)373; GISEL-NEXT: v_and_b32_e32 v2, 31, v1374; GISEL-NEXT: v_add_lshl_u32 v0, v0, v1, v2375; GISEL-NEXT: s_setpc_b64 s[30:31]376 %add = add i32 %a, %b377 %and = and i32 %b, 31378 %shl = shl i32 %add, %and379 ret i32 %shl380}381