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1; RUN: llc -O0 -mtriple=amdgcn--amdhsa -amdgpu-spill-sgpr-to-vgpr=0 < %s | FileCheck -enable-var-scope -check-prefix=VMEM -check-prefix=GCN %s2; RUN: llc -O0 -mtriple=amdgcn--amdhsa -amdgpu-spill-sgpr-to-vgpr=1 < %s | FileCheck -enable-var-scope -check-prefix=VGPR -check-prefix=GCN %s3 4; Verify registers used for tracking exec mask changes when all5; registers are spilled at the end of the block. The SGPR spill6; placement relative to the exec modifications are important.7 8; FIXME: This checks with SGPR to VGPR spilling disabled, but this may9; not work correctly in cases where no workitems take a branch.10 11 12; GCN-LABEL: {{^}}divergent_if_endif:13 14; GCN: {{^}}; %bb.0:15; GCN: s_mov_b32 m0, -116; GCN: ds_read_b32 [[LOAD0:v[0-9]+]]17 18; Spill load19; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], 0 offset:[[LOAD0_OFFSET:[0-9]+]] ; 4-byte Folded Spill20; GCN: v_cmp_eq_u32_e64 [[CMP0:s\[[0-9]+:[0-9]\]]], v{{[0-9]+}}, v{{[0-9]+}}21 22; Spill saved exec23; GCN: s_mov_b64 s[[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]], exec24; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]]25; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]]26 27; VMEM: v_writelane_b32 v[[V_SAVEEXEC:[0-9]+]], s[[SAVEEXEC_LO]], 028; VMEM: v_writelane_b32 v[[V_SAVEEXEC]], s[[SAVEEXEC_HI]], 129; VMEM: buffer_store_dword v[[V_SAVEEXEC]], off, s[0:3], 0 ; 4-byte Folded Spill30 31; GCN: s_and_b64 s[[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]], s[[[SAVEEXEC_LO]]:[[SAVEEXEC_HI]]], [[CMP0]]32; GCN: s_mov_b64 exec, s[[[ANDEXEC_LO]]:[[ANDEXEC_HI]]]33 34; GCN: s_cbranch_execz [[ENDIF:.LBB[0-9]+_[0-9]+]]35 36; GCN: ; %bb.{{[0-9]+}}: ; %if37; GCN: buffer_load_dword [[RELOAD_LOAD0:v[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload38; GCN: s_mov_b32 m0, -139; GCN: ds_read_b32 [[LOAD1:v[0-9]+]]40; GCN: s_waitcnt vmcnt(0) lgkmcnt(0)41 42 43; Spill val register44; GCN: v_add_i32_e32 [[VAL:v[0-9]+]], vcc, [[RELOAD_LOAD0]], [[LOAD1]]45; GCN: buffer_store_dword [[VAL]], off, s[0:3], 0 offset:[[VAL_OFFSET:[0-9]+]] ; 4-byte Folded Spill46 47; VMEM: [[ENDIF]]:48 49; Reload and restore exec mask50; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]51; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]52 53; VMEM: buffer_load_dword v[[V_RELOAD_SAVEEXEC:[0-9]+]], off, s[0:3], 0 ; 4-byte Folded Reload54; VMEM: s_waitcnt vmcnt(0)55; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 056; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 157 58; GCN: s_or_b64 exec, exec, s[[[S_RELOAD_SAVEEXEC_LO]]:[[S_RELOAD_SAVEEXEC_HI]]]59 60; Restore val61; GCN: buffer_load_dword [[RELOAD_VAL:v[0-9]+]], off, s[0:3], 0 offset:[[VAL_OFFSET]] ; 4-byte Folded Reload62 63; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RELOAD_VAL]]64 65; VGPR: .amdhsa_private_segment_fixed_size 1666define amdgpu_kernel void @divergent_if_endif(ptr addrspace(1) %out) #0 {67entry:68 %tid = call i32 @llvm.amdgcn.workitem.id.x()69 %load0 = load volatile i32, ptr addrspace(3) poison70 %cmp0 = icmp eq i32 %tid, 071 br i1 %cmp0, label %if, label %endif72 73if:74 %load1 = load volatile i32, ptr addrspace(3) poison75 %val = add i32 %load0, %load176 br label %endif77 78endif:79 %tmp4 = phi i32 [ %val, %if ], [ 0, %entry ]80 store i32 %tmp4, ptr addrspace(1) %out81 ret void82}83 84; GCN-LABEL: {{^}}divergent_loop:85 86; GCN: {{^}}; %bb.0:87; GCN-DAG: s_mov_b32 m0, -188; GCN-DAG: v_mov_b32_e32 [[PTR0:v[0-9]+]], 0{{$}}89; GCN: ds_read_b32 [[LOAD0:v[0-9]+]], [[PTR0]]90; GCN: v_cmp_eq_u32_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, s{{[0-9]+}}91 92; Spill load93; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], 0 offset:[[LOAD0_OFFSET:[0-9]+]] ; 4-byte Folded Spill94; GCN: s_mov_b64 s[[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]], exec95 96; Spill saved exec97; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]]98; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]]99 100; VMEM: v_writelane_b32 v[[V_SAVEEXEC:[0-9]+]], s[[SAVEEXEC_LO]], 0101; VMEM: v_writelane_b32 v[[V_SAVEEXEC]], s[[SAVEEXEC_HI]], 1102; VMEM: buffer_store_dword v[[V_SAVEEXEC]], off, s[0:3], 0 ; 4-byte Folded Spill103 104 105; GCN: s_and_b64 s[[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]], s[[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]], [[CMP0]]106; GCN: s_mov_b64 exec, s[[[ANDEXEC_LO]]:[[ANDEXEC_HI]]]107; GCN-NEXT: s_cbranch_execz [[END:.LBB[0-9]+_[0-9]+]]108 109 110; GCN: [[LOOP:.LBB[0-9]+_[0-9]+]]:111; GCN: buffer_load_dword v[[VAL_LOOP_RELOAD:[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload112; GCN: v_sub_i32_e32 v[[VAL_LOOP_RELOAD]], vcc, v[[VAL_LOOP_RELOAD]], v{{[0-9]+}}113; GCN: s_cmp_lg_u32114; VMEM: buffer_store_dword115; VMEM: buffer_store_dword116; VMEM: buffer_store_dword117; GCN: buffer_store_dword v[[VAL_LOOP_RELOAD]], off, s[0:3], 0 offset:{{[0-9]+}} ; 4-byte Folded Spill118; GCN-NEXT: s_cbranch_scc1 [[LOOP]]119 120; GCN: buffer_store_dword v[[VAL_LOOP_RELOAD]], off, s[0:3], 0 offset:[[VAL_SUB_OFFSET:[0-9]+]] ; 4-byte Folded Spill121 122; GCN: [[END]]:123; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]124; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]125 126; VMEM: buffer_load_dword v[[V_RELOAD_SAVEEXEC:[0-9]+]], off, s[0:3], 0 ; 4-byte Folded Reload127; VMEM: s_waitcnt vmcnt(0)128; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 0129; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 1130 131; GCN: s_or_b64 exec, exec, s[[[S_RELOAD_SAVEEXEC_LO]]:[[S_RELOAD_SAVEEXEC_HI]]]132 133; GCN: buffer_load_dword v[[VAL_END:[0-9]+]], off, s[0:3], 0 offset:[[VAL_SUB_OFFSET]] ; 4-byte Folded Reload134 135; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[VAL_END]]136 137; VGPR: .amdhsa_private_segment_fixed_size 20138define amdgpu_kernel void @divergent_loop(ptr addrspace(1) %out) #0 {139entry:140 %tid = call i32 @llvm.amdgcn.workitem.id.x()141 %load0 = load volatile i32, ptr addrspace(3) null142 %cmp0 = icmp eq i32 %tid, 0143 br i1 %cmp0, label %loop, label %end144 145loop:146 %i = phi i32 [ %i.inc, %loop ], [ 0, %entry ]147 %val = phi i32 [ %val.sub, %loop ], [ %load0, %entry ]148 %load1 = load volatile i32, ptr addrspace(3) poison149 %i.inc = add i32 %i, 1150 %val.sub = sub i32 %val, %load1151 %cmp1 = icmp ne i32 %i, 256152 br i1 %cmp1, label %loop, label %end153 154end:155 %tmp4 = phi i32 [ %val.sub, %loop ], [ 0, %entry ]156 store i32 %tmp4, ptr addrspace(1) %out157 ret void158}159 160; GCN-LABEL: {{^}}divergent_if_else_endif:161; GCN: {{^}}; %bb.0:162 163; GCN-DAG: s_mov_b32 m0, -1164; GCN-DAG: v_mov_b32_e32 [[PTR0:v[0-9]+]], 0{{$}}165; GCN: ds_read_b32 [[LOAD0:v[0-9]+]], [[PTR0]]166 167; Spill load168; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], 0 offset:[[LOAD0_OFFSET:[0-9]+]] ; 4-byte Folded Spill169 170; GCN: s_mov_b32 [[ZERO:s[0-9]+]], 0171; GCN: v_cmp_ne_u32_e64 [[CMP0:s\[[0-9]+:[0-9]\]]], v{{[0-9]+}}, [[ZERO]]172 173; GCN: s_mov_b64 s[[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]], exec174; GCN: s_and_b64 s[[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]], s[[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]], [[CMP0]]175; GCN: s_xor_b64 s[[[SAVEEXEC_LO]]:[[SAVEEXEC_HI]]], s[[[ANDEXEC_LO]]:[[ANDEXEC_HI]]], s[[[SAVEEXEC_LO]]:[[SAVEEXEC_HI]]]176 177; Spill saved exec178; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]]179; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]]180; VGPR: buffer_store_dword [[SPILL_VGPR]], off, s[0:3], 0 ; 4-byte Folded Spill181 182; VMEM: v_writelane_b32 v[[V_SAVEEXEC:[0-9]+]], s[[SAVEEXEC_LO]], 0183; VMEM: v_writelane_b32 v[[V_SAVEEXEC]], s[[SAVEEXEC_HI]], 1184; VMEM: buffer_store_dword v[[V_SAVEEXEC]], off, s[0:3], 0 ; 4-byte Folded Spill185 186; GCN: s_mov_b64 exec, [[CMP0]]187 188; FIXME: It makes no sense to put this skip here189; GCN: s_cbranch_execz [[FLOW:.LBB[0-9]+_[0-9]+]]190; GCN-NEXT: s_branch [[ELSE:.LBB[0-9]+_[0-9]+]]191 192; GCN: [[FLOW]]: ; %Flow193; VGPR: buffer_load_dword [[SPILL_VGPR:v[0-9]+]], off, s[0:3], 0 ; 4-byte Folded Reload194; VGPR: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]195; VGPR: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]196 197; VMEM: buffer_load_dword v[[FLOW_V_RELOAD_SAVEEXEC:[0-9]+]], off, s[0:3], 0198; VMEM: s_waitcnt vmcnt(0)199; VMEM: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[FLOW_V_RELOAD_SAVEEXEC]], 0200; VMEM: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_HI:[0-9]+]], v[[FLOW_V_RELOAD_SAVEEXEC]], 1201 202; GCN: s_or_saveexec_b64 s[[[FLOW_S_RELOAD_SAVEEXEC_LO_SAVEEXEC:[0-9]+]]:[[FLOW_S_RELOAD_SAVEEXEC_HI_SAVEEXEC:[0-9]+]]], s[[[FLOW_S_RELOAD_SAVEEXEC_LO]]:[[FLOW_S_RELOAD_SAVEEXEC_HI]]]203 204; GCN: buffer_load_dword [[FLOW_VAL:v[0-9]+]], off, s[0:3], 0 offset:[[FLOW_VAL_OFFSET:[0-9]+]] ; 4-byte Folded Reload205 206; Regular spill value restored after exec modification207; Followed by spill208; GCN: buffer_store_dword [[FLOW_VAL]], off, s[0:3], 0 offset:[[RESULT_OFFSET:[0-9]+]] ; 4-byte Folded Spill209 210; GCN: s_and_b64 s[[[FLOW_AND_EXEC_LO:[0-9]+]]:[[FLOW_AND_EXEC_HI:[0-9]+]]], exec, s[[[FLOW_S_RELOAD_SAVEEXEC_LO_SAVEEXEC]]:[[FLOW_S_RELOAD_SAVEEXEC_HI_SAVEEXEC]]]211 212; Spill saved exec213; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[FLOW_AND_EXEC_LO]], [[FLOW_SAVEEXEC_LO_LANE:[0-9]+]]214; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[FLOW_AND_EXEC_HI]], [[FLOW_SAVEEXEC_HI_LANE:[0-9]+]]215 216; VMEM: v_writelane_b32 v[[FLOW_V_SAVEEXEC:[0-9]+]], s[[FLOW_AND_EXEC_LO]], 0217; VMEM: v_writelane_b32 v[[FLOW_V_SAVEEXEC]], s[[FLOW_AND_EXEC_HI]], 1218; VMEM: buffer_store_dword v[[FLOW_V_SAVEEXEC]], off, s[0:3], 0 offset:[[FLOW_SAVEEXEC_OFFSET:[0-9]+]] ; 4-byte Folded Spill219 220; GCN: s_xor_b64 exec, exec, s[[[FLOW_AND_EXEC_LO]]:[[FLOW_AND_EXEC_HI]]]221; GCN-NEXT: s_cbranch_execz [[ENDIF:.LBB[0-9]+_[0-9]+]]222 223 224; GCN: ; %bb.{{[0-9]+}}: ; %if225; GCN: buffer_load_dword v[[LOAD0_RELOAD:[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload226; GCN: ds_read_b32227; GCN: v_add_i32_e32 v[[LOAD0_RELOAD]], vcc, v[[LOAD0_RELOAD]], [[ADD:v[0-9]+]]228; GCN: buffer_store_dword v[[LOAD0_RELOAD]], off, s[0:3], 0 offset:[[RESULT_OFFSET]] ; 4-byte Folded Spill229; GCN-NEXT: s_branch [[ENDIF:.LBB[0-9]+_[0-9]+]]230 231; GCN: [[ELSE]]: ; %else232; GCN: buffer_load_dword v[[LOAD0_RELOAD:[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload233; GCN: v_sub_i32_e32 v[[LOAD0_RELOAD]], vcc, v[[LOAD0_RELOAD]], v{{[0-9]+}}234; GCN: buffer_store_dword v[[LOAD0_RELOAD]], off, s[0:3], 0 offset:[[FLOW_RESULT_OFFSET:[0-9]+]] ; 4-byte Folded Spill235; GCN-NEXT: s_branch [[FLOW]]236 237; GCN: [[ENDIF]]:238; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[FLOW_SAVEEXEC_LO_LANE]]239; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[FLOW_SAVEEXEC_HI_LANE]]240 241 242; VMEM: buffer_load_dword v[[V_RELOAD_SAVEEXEC:[0-9]+]], off, s[0:3], 0 offset:[[FLOW_SAVEEXEC_OFFSET]] ; 4-byte Folded Reload243; VMEM: s_waitcnt vmcnt(0)244; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 0245; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 1246 247; GCN: s_or_b64 exec, exec, s[[[S_RELOAD_SAVEEXEC_LO]]:[[S_RELOAD_SAVEEXEC_HI]]]248 249; GCN: buffer_load_dword v[[RESULT:[0-9]+]], off, s[0:3], 0 offset:[[RESULT_OFFSET]] ; 4-byte Folded Reload250 251; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RESULT]]252define amdgpu_kernel void @divergent_if_else_endif(ptr addrspace(1) %out) #0 {253entry:254 %tid = call i32 @llvm.amdgcn.workitem.id.x()255 %load0 = load volatile i32, ptr addrspace(3) null256 %cmp0 = icmp eq i32 %tid, 0257 br i1 %cmp0, label %if, label %else258 259if:260 %load1 = load volatile i32, ptr addrspace(3) poison261 %val0 = add i32 %load0, %load1262 br label %endif263 264else:265 %load2 = load volatile i32, ptr addrspace(3) poison266 %val1 = sub i32 %load0, %load2267 br label %endif268 269endif:270 %result = phi i32 [ %val0, %if ], [ %val1, %else ]271 store i32 %result, ptr addrspace(1) %out272 ret void273}274 275declare i32 @llvm.amdgcn.workitem.id.x() #1276 277attributes #0 = { nounwind }278attributes #1 = { nounwind readnone }279 280!llvm.module.flags = !{!0}281!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}282