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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefix=GCN %s3 4; optnone disables AMDGPUAnnotateUniformValues, so no branch is known5; to be uniform during instruction selection. The custom selection for6; brcond was not checking if the branch was uniform, relying on the7; selection pattern to check that. That would fail, so then the branch8; would fail to select.9 10; GCN-LABEL: {{^}}copytoreg_divergent_brcond:11; GCN: s_branch12 13; GCN-DAG: v_cmp_lt_i3214; GCN-DAG: s_cmp_gt_i3215; GCN: s_and_b6416; GCN: s_mov_b64 exec17 18; GCN: s_or_b64 exec, exec19; GCN: {{[s|v]}}_cmp_eq_u3220; GCN: s_cbranch_execz21; GCN-NEXT: s_branch22define amdgpu_kernel void @copytoreg_divergent_brcond(i32 %arg, i32 %arg1, i32 %arg2) #0 {23bb:24 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()25 %tmp3 = zext i32 %tmp to i6426 %tmp5 = add i64 %tmp3, undef27 %tmp6 = trunc i64 %tmp5 to i3228 %tmp7 = mul nsw i32 %tmp6, %arg229 br label %bb830 31bb8.loopexit: ; preds = %bb1432 br label %bb833 34bb8: ; preds = %bb8.loopexit, %bb35 br label %bb936 37bb9: ; preds = %bb14, %bb838 %tmp10 = icmp slt i32 %tmp7, %arg139 %tmp11 = icmp sgt i32 %arg, 040 %tmp12 = and i1 %tmp10, %tmp1141 br i1 %tmp12, label %bb13, label %bb1442 43bb13: ; preds = %bb944 store volatile i32 0, ptr addrspace(1) poison, align 445 br label %bb1446 47bb14: ; preds = %bb13, %bb948 %tmp15 = icmp eq i32 %arg2, 149 br i1 %tmp15, label %bb8.loopexit, label %bb950}51 52declare i32 @llvm.amdgcn.workitem.id.x() #153 54attributes #0 = { nounwind optnone noinline }55attributes #1 = { nounwind readnone speculatable }56