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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx90a | FileCheck %s3 4define amdgpu_kernel void @copy_to_reg_frameindex(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {5; CHECK-LABEL: copy_to_reg_frameindex:6; CHECK: ; %bb.0: ; %entry7; CHECK-NEXT: s_cmp_lt_u32 0, 168; CHECK-NEXT: ; implicit-def: $vgpr09; CHECK-NEXT: .LBB0_1: ; %loop10; CHECK-NEXT: ; =>This Inner Loop Header: Depth=111; CHECK-NEXT: s_set_gpr_idx_on 0, gpr_idx(DST)12; CHECK-NEXT: v_mov_b32_e32 v0, 013; CHECK-NEXT: s_set_gpr_idx_off14; CHECK-NEXT: s_cbranch_scc1 .LBB0_115; CHECK-NEXT: ; %bb.2: ; %done16; CHECK-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2417; CHECK-NEXT: v_mov_b32_e32 v1, 018; CHECK-NEXT: s_waitcnt lgkmcnt(0)19; CHECK-NEXT: global_store_dword v1, v0, s[0:1]20; CHECK-NEXT: s_endpgm21entry:22 %B = srem i32 %c, -123 br label %loop24 25loop:26 %promotealloca = phi <16 x i32> [ poison, %entry ], [ %insert, %loop ]27 %inc = phi i32 [ 0, %entry ], [ %inc.i, %loop ]28 %insert = insertelement <16 x i32> %promotealloca, i32 %inc, i32 %inc29 %inc.i = add i32 %inc, %B30 %cnd = icmp uge i32 %inc.i, 1631 br i1 %cnd, label %done, label %loop32 33done:34 %extract.0 = extractelement <16 x i32> %insert, i32 035 store i32 %extract.0, ptr addrspace(1) %out, align 436 ret void37}38 39; When creating registers for %divergent.alloca.phi, we should report40; the CopyToReg as divergent values (not uniform just because the41; alloca is uniform)42define void @phi_with_alloca_and_divergent_copy_to_reg(ptr addrspace(5) %divergent.private, ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {43; CHECK-LABEL: phi_with_alloca_and_divergent_copy_to_reg:44; CHECK: ; %bb.0: ; %entry45; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)46; CHECK-NEXT: v_mov_b32_e32 v7, v247; CHECK-NEXT: v_mov_b32_e32 v6, v148; CHECK-NEXT: s_mov_b64 s[4:5], 049; CHECK-NEXT: v_lshrrev_b32_e64 v2, 6, s3250; CHECK-NEXT: .LBB1_1: ; %loop51; CHECK-NEXT: ; =>This Inner Loop Header: Depth=152; CHECK-NEXT: v_mov_b32_e32 v1, v253; CHECK-NEXT: v_lshl_add_u32 v2, v3, 2, v154; CHECK-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen55; CHECK-NEXT: v_add_u32_e32 v2, 1, v356; CHECK-NEXT: v_cmp_lt_u32_e32 vcc, 15, v257; CHECK-NEXT: s_or_b64 s[4:5], vcc, s[4:5]58; CHECK-NEXT: v_mov_b32_e32 v3, v459; CHECK-NEXT: v_mov_b32_e32 v2, v060; CHECK-NEXT: s_andn2_b64 exec, exec, s[4:5]61; CHECK-NEXT: s_cbranch_execnz .LBB1_162; CHECK-NEXT: ; %bb.2: ; %done63; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]64; CHECK-NEXT: buffer_load_dword v0, v1, s[0:3], 0 offen65; CHECK-NEXT: s_waitcnt vmcnt(0)66; CHECK-NEXT: global_store_dword v[6:7], v0, off67; CHECK-NEXT: s_waitcnt vmcnt(0)68; CHECK-NEXT: s_setpc_b64 s[30:31]69entry:70 %alloca0 = alloca [16 x i32], addrspace(5)71 br label %loop72 73loop:74 %inc = phi i32 [%a, %entry], [%b, %loop]75 %divergent.alloca.phi = phi ptr addrspace(5) [ %alloca0, %entry ], [ %divergent.private, %loop ]76 %ptr = getelementptr [16 x i32], ptr addrspace(5) %divergent.alloca.phi, i32 0, i32 %inc77 store i32 %inc, ptr addrspace(5) %ptr78 %inc.i = add i32 %inc, 179 %cnd = icmp uge i32 %inc.i, 1680 br i1 %cnd, label %done, label %loop81 82done:83 %tmp1 = load i32, ptr addrspace(5) %divergent.alloca.phi84 store i32 %tmp1, ptr addrspace(1) %out85 ret void86}87