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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -run-pass register-coalescer -verify-machineinstrs -o - %s | FileCheck -check-prefix GCN %s3#4---5name: _amdgpu_ps_main6alignment: 17tracksRegLiveness: true8registers:9 - { id: 0, class: sgpr_128 }10 - { id: 1, class: sreg_32_xm0, preferred-register: '%2' }11 - { id: 2, class: sreg_32_xm0, preferred-register: '%1' }12machineFunctionInfo:13 argumentInfo:14 privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }15 privateSegmentWaveByteOffset: { reg: '$sgpr33' }16body: |17 ; GCN-LABEL: name: _amdgpu_ps_main18 ; GCN: bb.0:19 ; GCN-NEXT: successors: %bb.1(0x80000000)20 ; GCN-NEXT: {{ $}}21 ; GCN-NEXT: [[V_TRUNC_F32_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_TRUNC_F32_e32 undef %4:vgpr_32, implicit $mode, implicit $exec22 ; GCN-NEXT: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 [[V_TRUNC_F32_e32_]], implicit $mode, implicit $exec23 ; GCN-NEXT: [[V_LSHRREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e32 4, [[V_CVT_U32_F32_e32_]], implicit $exec24 ; GCN-NEXT: undef [[V_MUL_LO_I32_e64_:%[0-9]+]].sub0:vreg_128 = V_MUL_LO_I32_e64 [[V_LSHRREV_B32_e32_]], 3, implicit $exec25 ; GCN-NEXT: [[V_MUL_LO_I32_e64_:%[0-9]+]].sub3:vreg_128 = COPY [[V_MUL_LO_I32_e64_]].sub026 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 027 ; GCN-NEXT: {{ $}}28 ; GCN-NEXT: bb.1:29 ; GCN-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)30 ; GCN-NEXT: {{ $}}31 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY [[V_MUL_LO_I32_e64_]]32 ; GCN-NEXT: [[V_MUL_LO_I32_e64_:%[0-9]+]].sub3:vreg_128 = V_ADD_U32_e32 target-flags(amdgpu-rel32-lo) 1, [[COPY]].sub3, implicit $exec33 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_ADD_I32 [[S_MOV_B32_]], 1, implicit-def dead $scc34 ; GCN-NEXT: S_CMP_LT_U32 [[S_MOV_B32_]], 3, implicit-def $scc35 ; GCN-NEXT: S_CBRANCH_SCC1 %bb.1, implicit killed $scc36 ; GCN-NEXT: S_BRANCH %bb.237 ; GCN-NEXT: {{ $}}38 ; GCN-NEXT: bb.2:39 ; GCN-NEXT: successors: %bb.5(0x40000000), %bb.3(0x40000000)40 ; GCN-NEXT: {{ $}}41 ; GCN-NEXT: S_CBRANCH_SCC1 %bb.5, implicit undef $scc42 ; GCN-NEXT: S_BRANCH %bb.343 ; GCN-NEXT: {{ $}}44 ; GCN-NEXT: bb.3:45 ; GCN-NEXT: successors: %bb.4(0x80000000)46 ; GCN-NEXT: {{ $}}47 ; GCN-NEXT: dead [[BUFFER_LOAD_FORMAT_XYZW_IDXEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN [[COPY]].sub3, undef %17:sgpr_128, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128) from constant-pool, align 1, addrspace 4)48 ; GCN-NEXT: dead [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec49 ; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 $exec, -1, implicit-def dead $scc50 ; GCN-NEXT: dead [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec51 ; GCN-NEXT: {{ $}}52 ; GCN-NEXT: bb.4:53 ; GCN-NEXT: successors: %bb.4(0x7c000000), %bb.6(0x04000000)54 ; GCN-NEXT: {{ $}}55 ; GCN-NEXT: $vcc = COPY [[S_AND_B64_]]56 ; GCN-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit killed $vcc57 ; GCN-NEXT: S_BRANCH %bb.658 ; GCN-NEXT: {{ $}}59 ; GCN-NEXT: bb.5:60 ; GCN-NEXT: [[V_MUL_F32_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_MUL_F32_e32 target-flags(amdgpu-gotprel) 0, [[V_MUL_LO_I32_e64_]].sub0, implicit $mode, implicit $exec61 ; GCN-NEXT: [[V_MIN_F32_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_MIN_F32_e32 1106771968, [[V_MUL_F32_e32_]], implicit $mode, implicit $exec62 ; GCN-NEXT: [[V_MAD_F32_e64_:%[0-9]+]]:vgpr_32 = nnan arcp contract reassoc nofpexcept V_MAD_F32_e64 0, [[V_MIN_F32_e32_]], 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec63 ; GCN-NEXT: [[V_MAD_F32_e64_1:%[0-9]+]]:vgpr_32 = nnan arcp contract reassoc nofpexcept V_MAD_F32_e64 0, [[V_MAD_F32_e64_]], 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec64 ; GCN-NEXT: [[V_MAD_F32_e64_2:%[0-9]+]]:vgpr_32 = nofpexcept V_MAD_F32_e64 0, [[V_MAD_F32_e64_1]], 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec65 ; GCN-NEXT: [[V_CVT_PKRTZ_F16_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, [[V_MAD_F32_e64_2]], 0, undef %27:vgpr_32, 0, 0, implicit $mode, implicit $exec66 ; GCN-NEXT: EXP_DONE 0, [[V_CVT_PKRTZ_F16_F32_e64_]], undef %28:vgpr_32, undef %29:vgpr_32, undef %30:vgpr_32, -1, -1, 15, implicit $exec67 ; GCN-NEXT: S_ENDPGM 068 ; GCN-NEXT: {{ $}}69 ; GCN-NEXT: bb.6:70 ; GCN-NEXT: S_ENDPGM 071 bb.0:72 %10:vgpr_32 = nofpexcept V_TRUNC_F32_e32 undef %11:vgpr_32, implicit $mode, implicit $exec73 %12:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 killed %10, implicit $mode, implicit $exec74 %50:vgpr_32 = V_LSHRREV_B32_e32 4, killed %12, implicit $exec75 %51:vgpr_32 = V_MUL_LO_I32_e64 killed %50, 3, implicit $exec76 undef %52.sub0:vreg_128 = COPY %5177 %52.sub3:vreg_128 = COPY %5178 %9:sreg_32_xm0 = S_MOV_B32 079 %70:sreg_32_xm0 = COPY killed %980 %71:vreg_128 = COPY killed %5281 82 bb.1:83 successors: %bb.1(0x7c000000), %bb.2(0x04000000)84 85 %53:vreg_128 = COPY killed %7186 %1:sreg_32_xm0 = COPY killed %7087 %57:vgpr_32 = V_ADD_U32_e32 target-flags(amdgpu-rel32-lo) 1, %53.sub3, implicit $exec88 %55:vreg_128 = COPY %5389 %55.sub3:vreg_128 = COPY killed %5790 %2:sreg_32_xm0 = S_ADD_I32 killed %1, 1, implicit-def dead $scc91 S_CMP_LT_U32 %2, 3, implicit-def $scc92 %54:vreg_128 = COPY %5593 %70:sreg_32_xm0 = COPY killed %294 %71:vreg_128 = COPY killed %5495 S_CBRANCH_SCC1 %bb.1, implicit killed $scc96 S_BRANCH %bb.297 98 bb.2:99 S_CBRANCH_SCC1 %bb.5, implicit undef $scc100 S_BRANCH %bb.3101 102 bb.3:103 dead %22:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %53.sub3, undef %24:sgpr_128, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128) from constant-pool, align 1, addrspace 4)104 dead %60:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec105 %36:sreg_64 = S_AND_B64 $exec, -1, implicit-def dead $scc106 dead %67:vgpr_32 = V_MOV_B32_e32 0, implicit $exec107 108 bb.4:109 successors: %bb.4(0x7c000000), %bb.6(0x04000000)110 111 $vcc = COPY %36112 S_CBRANCH_VCCNZ %bb.4, implicit killed $vcc113 S_BRANCH %bb.6114 115 bb.5:116 %39:vgpr_32 = nofpexcept V_MUL_F32_e32 target-flags(amdgpu-gotprel) 0, killed %55.sub0, implicit $mode, implicit $exec117 %41:vgpr_32 = nofpexcept V_MIN_F32_e32 1106771968, killed %39, implicit $mode, implicit $exec118 %42:vgpr_32 = nnan arcp contract reassoc nofpexcept V_MAD_F32_e64 0, killed %41, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec119 %43:vgpr_32 = nnan arcp contract reassoc nofpexcept V_MAD_F32_e64 0, killed %42, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec120 %44:vgpr_32 = nofpexcept V_MAD_F32_e64 0, killed %43, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec121 %45:vgpr_32 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, killed %44, 0, undef %46:vgpr_32, 0, 0, implicit $mode, implicit $exec122 EXP_DONE 0, killed %45, undef %47:vgpr_32, undef %48:vgpr_32, undef %49:vgpr_32, -1, -1, 15, implicit $exec123 S_ENDPGM 0124 125 bb.6:126 S_ENDPGM 0127 128...129