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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s -check-prefix=GCN3 4define i32 @test(i32 %val, i32 %cond) {5; GCN-LABEL: test:6; GCN: ; %bb.0: ; %entry7; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8; GCN-NEXT: s_xor_saveexec_b32 s4, -19; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 ; 4-byte Folded Spill10; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill11; GCN-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)12; GCN-NEXT: s_mov_b32 exec_lo, s413; GCN-NEXT: s_or_saveexec_b32 s4, -114; GCN-NEXT: v_mov_b32_e32 v2, 015; GCN-NEXT: v_cndmask_b32_e64 v3, 0, v0, s416; GCN-NEXT: v_mov_b32_dpp v2, v3 row_xmask:1 row_mask:0xf bank_mask:0xf17; GCN-NEXT: s_mov_b32 exec_lo, s418; GCN-NEXT: v_mov_b32_e32 v5, 019; GCN-NEXT: v_mov_b32_e32 v4, v220; GCN-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v121; GCN-NEXT: s_and_saveexec_b32 s4, vcc_lo22; GCN-NEXT: ; %bb.1: ; %if23; GCN-NEXT: s_or_saveexec_b32 s5, -124; GCN-NEXT: v_mov_b32_e32 v2, 025; GCN-NEXT: v_cndmask_b32_e64 v3, 0, v0, s526; GCN-NEXT: v_mov_b32_dpp v2, v3 row_xmask:1 row_mask:0xf bank_mask:0xf27; GCN-NEXT: s_mov_b32 exec_lo, s528; GCN-NEXT: v_mov_b32_e32 v5, v229; GCN-NEXT: ; %bb.2: ; %end30; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s431; GCN-NEXT: v_add_nc_u32_e32 v0, v4, v532; GCN-NEXT: s_xor_saveexec_b32 s4, -133; GCN-NEXT: s_clause 0x1 ; 8-byte Folded Reload34; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s3235; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:436; GCN-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)37; GCN-NEXT: s_mov_b32 exec_lo, s438; GCN-NEXT: s_waitcnt vmcnt(0)39; GCN-NEXT: s_setpc_b64 s[30:31]40entry:41 ; %x = subgroup operation over all lanes.42 %x1 = call i32 @llvm.amdgcn.set.inactive.i32(i32 %val, i32 0)43 %x2 = call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %x1, i32 353, i32 15, i32 15, i1 false)44 %x3 = call i32 @llvm.amdgcn.strict.wwm.i32(i32 %x2)45 %cmp = icmp eq i32 %cond, 046 br i1 %cmp, label %if, label %end47 48if:49 ; %y = subgroup operations over lanes satisfying %cond.50 %y1 = call i32 @llvm.amdgcn.set.inactive.i32(i32 %val, i32 0)51 %y2 = call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %y1, i32 353, i32 15, i32 15, i1 false)52 %y3 = call i32 @llvm.amdgcn.strict.wwm.i32(i32 %y2)53 br label %end54 55end:56 %y = phi i32 [0, %entry], [%y3, %if]57 %ret = add i32 %x3, %y58 ret i32 %ret59}60 61declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32)62declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32 immarg, i32 immarg, i32 immarg, i1 immarg)63declare i32 @llvm.amdgcn.strict.wwm.i32(i32)64