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1; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=gfx900 | FileCheck %s2 3; Check that the redundant immediate MOV instruction4; (by-product of handling phi nodes) is not found5; in the generated code.6 7; CHECK-LABEL: {{^}}mov_opt:8; CHECK: s_mov_b32 [[SREG:s[0-9]+]], 1.09; CHECK: %bb.1:10; CHECK-NOT: v_mov_b32_e32 {{v[0-9]+}}, 1.011; CHECK: BB0_3:12; CHECK: v_mov_b32_e32 v{{[0-9]+}}, [[SREG]]13 14define amdgpu_ps void @mov_opt(i32 %arg, i32 inreg %arg1, i32 inreg %arg2) local_unnamed_addr #0 {15bb:16 %tmp = icmp eq i32 %arg1, 017 br i1 %tmp, label %bb3, label %bb1018 19bb3: ; preds = %bb20 %tmp4 = icmp eq i32 %arg2, 021 br i1 %tmp4, label %bb5, label %bb1022 23bb5: ; preds = %bb324 %tmp6 = getelementptr <{ [4294967295 x i32] }>, ptr addrspace(6) null, i32 0, i32 0, i32 %arg25 %tmp7 = load i32, ptr addrspace(6) %tmp626 %tmp8 = icmp eq i32 %tmp7, 127 br i1 %tmp8, label %bb10, label %bb928 29bb9: ; preds = %bb530 br label %bb1031 32bb10: ; preds = %bb9, %bb5, %bb3, %bb33 %tmp11 = phi float [ 1.000000e+00, %bb3 ], [ 0.000000e+00, %bb9 ], [ 1.000000e+00, %bb ], [ poison, %bb5 ]34 call void @llvm.amdgcn.exp.f32(i32 40, i32 15, float %tmp11, float poison, float poison, float poison, i1 false, i1 false) #035 ret void36}37 38; Function Attrs: inaccessiblememonly nounwind39declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg) #140 41attributes #0 = { nounwind }42attributes #1 = { inaccessiblememonly nounwind }43