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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=amdgcn | FileCheck %s -enable-var-scope --check-prefix=SI3; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck %s -enable-var-scope --check-prefix=VI4; RUN: llc < %s -mtriple=r600 -mcpu=cypress | FileCheck %s -enable-var-scope --check-prefix=EG5; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 | FileCheck %s -enable-var-scope --check-prefix=GFX106; RUN: llc < %s -global-isel -mtriple=amdgcn -mcpu=gfx1010 | FileCheck %s -enable-var-scope --check-prefix=GFX10-GISEL7; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 | FileCheck %s -enable-var-scope --check-prefixes=GFX11,GFX11-TRUE168; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 | FileCheck %s -enable-var-scope --check-prefixes=GFX11,GFX11-FAKE169 10declare i7 @llvm.ctlz.i7(i7, i1) nounwind readnone11declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone12declare i16 @llvm.ctlz.i16(i16, i1) nounwind readnone13 14declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone15declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone16declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone17 18declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone19declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone20declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1) nounwind readnone21 22declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone23 24define amdgpu_kernel void @s_ctlz_i32(ptr addrspace(1) noalias %out, i32 %val) nounwind {25; SI-LABEL: s_ctlz_i32:26; SI: ; %bb.0:27; SI-NEXT: s_load_dword s2, s[4:5], 0xb28; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x929; SI-NEXT: s_mov_b32 s3, 0xf00030; SI-NEXT: s_waitcnt lgkmcnt(0)31; SI-NEXT: s_flbit_i32_b32 s2, s232; SI-NEXT: s_min_u32 s4, s2, 3233; SI-NEXT: s_mov_b32 s2, -134; SI-NEXT: v_mov_b32_e32 v0, s435; SI-NEXT: buffer_store_dword v0, off, s[0:3], 036; SI-NEXT: s_endpgm37;38; VI-LABEL: s_ctlz_i32:39; VI: ; %bb.0:40; VI-NEXT: s_load_dword s6, s[4:5], 0x2c41; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2442; VI-NEXT: s_mov_b32 s3, 0xf00043; VI-NEXT: s_mov_b32 s2, -144; VI-NEXT: s_waitcnt lgkmcnt(0)45; VI-NEXT: s_flbit_i32_b32 s4, s646; VI-NEXT: s_min_u32 s4, s4, 3247; VI-NEXT: v_mov_b32_e32 v0, s448; VI-NEXT: buffer_store_dword v0, off, s[0:3], 049; VI-NEXT: s_endpgm50;51; EG-LABEL: s_ctlz_i32:52; EG: ; %bb.0:53; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]54; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 155; EG-NEXT: CF_END56; EG-NEXT: PAD57; EG-NEXT: ALU clause starting at 4:58; EG-NEXT: FFBH_UINT * T0.W, KC0[2].Z,59; EG-NEXT: CNDE_INT T0.X, KC0[2].Z, literal.x, PV.W,60; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,61; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45)62;63; GFX10-LABEL: s_ctlz_i32:64; GFX10: ; %bb.0:65; GFX10-NEXT: s_clause 0x166; GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c67; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2468; GFX10-NEXT: v_mov_b32_e32 v0, 069; GFX10-NEXT: s_waitcnt lgkmcnt(0)70; GFX10-NEXT: s_flbit_i32_b32 s2, s271; GFX10-NEXT: s_min_u32 s2, s2, 3272; GFX10-NEXT: v_mov_b32_e32 v1, s273; GFX10-NEXT: global_store_dword v0, v1, s[0:1]74; GFX10-NEXT: s_endpgm75;76; GFX10-GISEL-LABEL: s_ctlz_i32:77; GFX10-GISEL: ; %bb.0:78; GFX10-GISEL-NEXT: s_clause 0x179; GFX10-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c80; GFX10-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2481; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 082; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)83; GFX10-GISEL-NEXT: s_flbit_i32_b32 s2, s284; GFX10-GISEL-NEXT: s_min_u32 s2, s2, 3285; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s286; GFX10-GISEL-NEXT: global_store_dword v1, v0, s[0:1]87; GFX10-GISEL-NEXT: s_endpgm88;89; GFX11-LABEL: s_ctlz_i32:90; GFX11: ; %bb.0:91; GFX11-NEXT: s_clause 0x192; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c93; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x2494; GFX11-NEXT: s_waitcnt lgkmcnt(0)95; GFX11-NEXT: s_clz_i32_u32 s2, s296; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)97; GFX11-NEXT: s_min_u32 s2, s2, 3298; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s299; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]100; GFX11-NEXT: s_endpgm101 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone102 store i32 %ctlz, ptr addrspace(1) %out, align 4103 ret void104}105 106define amdgpu_kernel void @v_ctlz_i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {107; SI-LABEL: v_ctlz_i32:108; SI: ; %bb.0:109; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9110; SI-NEXT: s_mov_b32 s7, 0xf000111; SI-NEXT: s_mov_b32 s10, 0112; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0113; SI-NEXT: v_mov_b32_e32 v1, 0114; SI-NEXT: s_mov_b32 s11, s7115; SI-NEXT: s_waitcnt lgkmcnt(0)116; SI-NEXT: s_mov_b64 s[8:9], s[2:3]117; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64118; SI-NEXT: s_mov_b32 s6, -1119; SI-NEXT: s_mov_b32 s4, s0120; SI-NEXT: s_mov_b32 s5, s1121; SI-NEXT: s_waitcnt vmcnt(0)122; SI-NEXT: v_ffbh_u32_e32 v0, v0123; SI-NEXT: v_min_u32_e32 v0, 32, v0124; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0125; SI-NEXT: s_endpgm126;127; VI-LABEL: v_ctlz_i32:128; VI: ; %bb.0:129; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24130; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0131; VI-NEXT: s_waitcnt lgkmcnt(0)132; VI-NEXT: v_mov_b32_e32 v1, s3133; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0134; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc135; VI-NEXT: flat_load_dword v0, v[0:1]136; VI-NEXT: s_mov_b32 s3, 0xf000137; VI-NEXT: s_mov_b32 s2, -1138; VI-NEXT: s_waitcnt vmcnt(0)139; VI-NEXT: v_ffbh_u32_e32 v0, v0140; VI-NEXT: v_min_u32_e32 v0, 32, v0141; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0142; VI-NEXT: s_endpgm143;144; EG-LABEL: v_ctlz_i32:145; EG: ; %bb.0:146; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]147; EG-NEXT: TEX 0 @6148; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[]149; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1150; EG-NEXT: CF_END151; EG-NEXT: PAD152; EG-NEXT: Fetch clause starting at 6:153; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1154; EG-NEXT: ALU clause starting at 8:155; EG-NEXT: LSHL * T0.W, T0.X, literal.x,156; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)157; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,158; EG-NEXT: ALU clause starting at 11:159; EG-NEXT: FFBH_UINT * T0.W, T0.X,160; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W,161; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,162; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45)163;164; GFX10-LABEL: v_ctlz_i32:165; GFX10: ; %bb.0:166; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24167; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0168; GFX10-NEXT: v_mov_b32_e32 v1, 0169; GFX10-NEXT: s_waitcnt lgkmcnt(0)170; GFX10-NEXT: global_load_dword v0, v0, s[2:3]171; GFX10-NEXT: s_waitcnt vmcnt(0)172; GFX10-NEXT: v_ffbh_u32_e32 v0, v0173; GFX10-NEXT: v_min_u32_e32 v0, 32, v0174; GFX10-NEXT: global_store_dword v1, v0, s[0:1]175; GFX10-NEXT: s_endpgm176;177; GFX10-GISEL-LABEL: v_ctlz_i32:178; GFX10-GISEL: ; %bb.0:179; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24180; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0181; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0182; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)183; GFX10-GISEL-NEXT: global_load_dword v0, v0, s[2:3]184; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)185; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v0, v0186; GFX10-GISEL-NEXT: v_min_u32_e32 v0, 32, v0187; GFX10-GISEL-NEXT: global_store_dword v1, v0, s[0:1]188; GFX10-GISEL-NEXT: s_endpgm189;190; GFX11-LABEL: v_ctlz_i32:191; GFX11: ; %bb.0:192; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24193; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0194; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)195; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0196; GFX11-NEXT: s_waitcnt lgkmcnt(0)197; GFX11-NEXT: global_load_b32 v0, v0, s[2:3]198; GFX11-NEXT: s_waitcnt vmcnt(0)199; GFX11-NEXT: v_clz_i32_u32_e32 v0, v0200; GFX11-NEXT: v_min_u32_e32 v0, 32, v0201; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]202; GFX11-NEXT: s_endpgm203 %tid = call i32 @llvm.amdgcn.workitem.id.x()204 %in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid205 %val = load i32, ptr addrspace(1) %in.gep, align 4206 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone207 store i32 %ctlz, ptr addrspace(1) %out, align 4208 ret void209}210 211define amdgpu_kernel void @v_ctlz_v2i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {212; SI-LABEL: v_ctlz_v2i32:213; SI: ; %bb.0:214; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9215; SI-NEXT: s_mov_b32 s7, 0xf000216; SI-NEXT: s_mov_b32 s10, 0217; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0218; SI-NEXT: v_mov_b32_e32 v1, 0219; SI-NEXT: s_mov_b32 s11, s7220; SI-NEXT: s_waitcnt lgkmcnt(0)221; SI-NEXT: s_mov_b64 s[8:9], s[2:3]222; SI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[8:11], 0 addr64223; SI-NEXT: s_mov_b32 s6, -1224; SI-NEXT: s_mov_b32 s4, s0225; SI-NEXT: s_mov_b32 s5, s1226; SI-NEXT: s_waitcnt vmcnt(0)227; SI-NEXT: v_ffbh_u32_e32 v1, v1228; SI-NEXT: v_ffbh_u32_e32 v0, v0229; SI-NEXT: v_min_u32_e32 v1, 32, v1230; SI-NEXT: v_min_u32_e32 v0, 32, v0231; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0232; SI-NEXT: s_endpgm233;234; VI-LABEL: v_ctlz_v2i32:235; VI: ; %bb.0:236; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24237; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0238; VI-NEXT: s_waitcnt lgkmcnt(0)239; VI-NEXT: v_mov_b32_e32 v1, s3240; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0241; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc242; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]243; VI-NEXT: s_mov_b32 s3, 0xf000244; VI-NEXT: s_mov_b32 s2, -1245; VI-NEXT: s_waitcnt vmcnt(0)246; VI-NEXT: v_ffbh_u32_e32 v1, v1247; VI-NEXT: v_ffbh_u32_e32 v0, v0248; VI-NEXT: v_min_u32_e32 v1, 32, v1249; VI-NEXT: v_min_u32_e32 v0, 32, v0250; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0251; VI-NEXT: s_endpgm252;253; EG-LABEL: v_ctlz_v2i32:254; EG: ; %bb.0:255; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]256; EG-NEXT: TEX 0 @6257; EG-NEXT: ALU 6, @11, KC0[CB0:0-32], KC1[]258; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1259; EG-NEXT: CF_END260; EG-NEXT: PAD261; EG-NEXT: Fetch clause starting at 6:262; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1263; EG-NEXT: ALU clause starting at 8:264; EG-NEXT: LSHL * T0.W, T0.X, literal.x,265; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)266; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,267; EG-NEXT: ALU clause starting at 11:268; EG-NEXT: FFBH_UINT * T0.W, T0.Y,269; EG-NEXT: CNDE_INT T0.Y, T0.Y, literal.x, PV.W,270; EG-NEXT: FFBH_UINT * T0.W, T0.X,271; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)272; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W,273; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,274; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45)275;276; GFX10-LABEL: v_ctlz_v2i32:277; GFX10: ; %bb.0:278; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24279; GFX10-NEXT: v_lshlrev_b32_e32 v0, 3, v0280; GFX10-NEXT: v_mov_b32_e32 v2, 0281; GFX10-NEXT: s_waitcnt lgkmcnt(0)282; GFX10-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3]283; GFX10-NEXT: s_waitcnt vmcnt(0)284; GFX10-NEXT: v_ffbh_u32_e32 v1, v1285; GFX10-NEXT: v_ffbh_u32_e32 v0, v0286; GFX10-NEXT: v_min_u32_e32 v1, 32, v1287; GFX10-NEXT: v_min_u32_e32 v0, 32, v0288; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]289; GFX10-NEXT: s_endpgm290;291; GFX10-GISEL-LABEL: v_ctlz_v2i32:292; GFX10-GISEL: ; %bb.0:293; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24294; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v0, 3, v0295; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0296; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)297; GFX10-GISEL-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3]298; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)299; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v0, v0300; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v1, v1301; GFX10-GISEL-NEXT: v_min_u32_e32 v0, 32, v0302; GFX10-GISEL-NEXT: v_min_u32_e32 v1, 32, v1303; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]304; GFX10-GISEL-NEXT: s_endpgm305;306; GFX11-LABEL: v_ctlz_v2i32:307; GFX11: ; %bb.0:308; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24309; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0310; GFX11-NEXT: v_mov_b32_e32 v2, 0311; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)312; GFX11-NEXT: v_lshlrev_b32_e32 v0, 3, v0313; GFX11-NEXT: s_waitcnt lgkmcnt(0)314; GFX11-NEXT: global_load_b64 v[0:1], v0, s[2:3]315; GFX11-NEXT: s_waitcnt vmcnt(0)316; GFX11-NEXT: v_clz_i32_u32_e32 v1, v1317; GFX11-NEXT: v_clz_i32_u32_e32 v0, v0318; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)319; GFX11-NEXT: v_min_u32_e32 v1, 32, v1320; GFX11-NEXT: v_min_u32_e32 v0, 32, v0321; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]322; GFX11-NEXT: s_endpgm323 %tid = call i32 @llvm.amdgcn.workitem.id.x()324 %in.gep = getelementptr <2 x i32>, ptr addrspace(1) %valptr, i32 %tid325 %val = load <2 x i32>, ptr addrspace(1) %in.gep, align 8326 %ctlz = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %val, i1 false) nounwind readnone327 store <2 x i32> %ctlz, ptr addrspace(1) %out, align 8328 ret void329}330 331define amdgpu_kernel void @v_ctlz_v4i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {332; SI-LABEL: v_ctlz_v4i32:333; SI: ; %bb.0:334; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9335; SI-NEXT: s_mov_b32 s7, 0xf000336; SI-NEXT: s_mov_b32 s10, 0337; SI-NEXT: v_lshlrev_b32_e32 v0, 4, v0338; SI-NEXT: v_mov_b32_e32 v1, 0339; SI-NEXT: s_mov_b32 s11, s7340; SI-NEXT: s_waitcnt lgkmcnt(0)341; SI-NEXT: s_mov_b64 s[8:9], s[2:3]342; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64343; SI-NEXT: s_mov_b32 s6, -1344; SI-NEXT: s_mov_b32 s4, s0345; SI-NEXT: s_mov_b32 s5, s1346; SI-NEXT: s_waitcnt vmcnt(0)347; SI-NEXT: v_ffbh_u32_e32 v3, v3348; SI-NEXT: v_ffbh_u32_e32 v2, v2349; SI-NEXT: v_ffbh_u32_e32 v1, v1350; SI-NEXT: v_ffbh_u32_e32 v0, v0351; SI-NEXT: v_min_u32_e32 v3, 32, v3352; SI-NEXT: v_min_u32_e32 v2, 32, v2353; SI-NEXT: v_min_u32_e32 v1, 32, v1354; SI-NEXT: v_min_u32_e32 v0, 32, v0355; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0356; SI-NEXT: s_endpgm357;358; VI-LABEL: v_ctlz_v4i32:359; VI: ; %bb.0:360; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24361; VI-NEXT: v_lshlrev_b32_e32 v0, 4, v0362; VI-NEXT: s_waitcnt lgkmcnt(0)363; VI-NEXT: v_mov_b32_e32 v1, s3364; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0365; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc366; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]367; VI-NEXT: s_mov_b32 s3, 0xf000368; VI-NEXT: s_mov_b32 s2, -1369; VI-NEXT: s_waitcnt vmcnt(0)370; VI-NEXT: v_ffbh_u32_e32 v3, v3371; VI-NEXT: v_ffbh_u32_e32 v2, v2372; VI-NEXT: v_ffbh_u32_e32 v1, v1373; VI-NEXT: v_ffbh_u32_e32 v0, v0374; VI-NEXT: v_min_u32_e32 v3, 32, v3375; VI-NEXT: v_min_u32_e32 v2, 32, v2376; VI-NEXT: v_min_u32_e32 v1, 32, v1377; VI-NEXT: v_min_u32_e32 v0, 32, v0378; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0379; VI-NEXT: s_endpgm380;381; EG-LABEL: v_ctlz_v4i32:382; EG: ; %bb.0:383; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]384; EG-NEXT: TEX 0 @6385; EG-NEXT: ALU 12, @11, KC0[CB0:0-32], KC1[]386; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1387; EG-NEXT: CF_END388; EG-NEXT: PAD389; EG-NEXT: Fetch clause starting at 6:390; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1391; EG-NEXT: ALU clause starting at 8:392; EG-NEXT: LSHL * T0.W, T0.X, literal.x,393; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)394; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,395; EG-NEXT: ALU clause starting at 11:396; EG-NEXT: FFBH_UINT * T1.W, T0.W,397; EG-NEXT: FFBH_UINT T2.W, T0.Z,398; EG-NEXT: CNDE_INT * T0.W, T0.W, literal.x, PV.W, BS:VEC_021/SCL_122399; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)400; EG-NEXT: CNDE_INT T0.Z, T0.Z, literal.x, PV.W,401; EG-NEXT: FFBH_UINT * T1.W, T0.Y,402; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)403; EG-NEXT: CNDE_INT T0.Y, T0.Y, literal.x, PV.W,404; EG-NEXT: FFBH_UINT * T1.W, T0.X,405; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)406; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W,407; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,408; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45)409;410; GFX10-LABEL: v_ctlz_v4i32:411; GFX10: ; %bb.0:412; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24413; GFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0414; GFX10-NEXT: v_mov_b32_e32 v4, 0415; GFX10-NEXT: s_waitcnt lgkmcnt(0)416; GFX10-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3]417; GFX10-NEXT: s_waitcnt vmcnt(0)418; GFX10-NEXT: v_ffbh_u32_e32 v3, v3419; GFX10-NEXT: v_ffbh_u32_e32 v2, v2420; GFX10-NEXT: v_ffbh_u32_e32 v1, v1421; GFX10-NEXT: v_ffbh_u32_e32 v0, v0422; GFX10-NEXT: v_min_u32_e32 v3, 32, v3423; GFX10-NEXT: v_min_u32_e32 v2, 32, v2424; GFX10-NEXT: v_min_u32_e32 v1, 32, v1425; GFX10-NEXT: v_min_u32_e32 v0, 32, v0426; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]427; GFX10-NEXT: s_endpgm428;429; GFX10-GISEL-LABEL: v_ctlz_v4i32:430; GFX10-GISEL: ; %bb.0:431; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24432; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v0, 4, v0433; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0434; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)435; GFX10-GISEL-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3]436; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)437; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v0, v0438; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v1, v1439; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v2, v2440; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v3, v3441; GFX10-GISEL-NEXT: v_min_u32_e32 v0, 32, v0442; GFX10-GISEL-NEXT: v_min_u32_e32 v1, 32, v1443; GFX10-GISEL-NEXT: v_min_u32_e32 v2, 32, v2444; GFX10-GISEL-NEXT: v_min_u32_e32 v3, 32, v3445; GFX10-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]446; GFX10-GISEL-NEXT: s_endpgm447;448; GFX11-LABEL: v_ctlz_v4i32:449; GFX11: ; %bb.0:450; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24451; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0452; GFX11-NEXT: v_mov_b32_e32 v4, 0453; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)454; GFX11-NEXT: v_lshlrev_b32_e32 v0, 4, v0455; GFX11-NEXT: s_waitcnt lgkmcnt(0)456; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3]457; GFX11-NEXT: s_waitcnt vmcnt(0)458; GFX11-NEXT: v_clz_i32_u32_e32 v3, v3459; GFX11-NEXT: v_clz_i32_u32_e32 v2, v2460; GFX11-NEXT: v_clz_i32_u32_e32 v1, v1461; GFX11-NEXT: v_clz_i32_u32_e32 v0, v0462; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)463; GFX11-NEXT: v_min_u32_e32 v3, 32, v3464; GFX11-NEXT: v_min_u32_e32 v2, 32, v2465; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)466; GFX11-NEXT: v_min_u32_e32 v1, 32, v1467; GFX11-NEXT: v_min_u32_e32 v0, 32, v0468; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]469; GFX11-NEXT: s_endpgm470 %tid = call i32 @llvm.amdgcn.workitem.id.x()471 %in.gep = getelementptr <4 x i32>, ptr addrspace(1) %valptr, i32 %tid472 %val = load <4 x i32>, ptr addrspace(1) %in.gep, align 16473 %ctlz = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %val, i1 false) nounwind readnone474 store <4 x i32> %ctlz, ptr addrspace(1) %out, align 16475 ret void476}477 478define amdgpu_kernel void @v_ctlz_i8(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {479; SI-LABEL: v_ctlz_i8:480; SI: ; %bb.0:481; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9482; SI-NEXT: s_mov_b32 s7, 0xf000483; SI-NEXT: s_mov_b32 s6, -1484; SI-NEXT: s_mov_b32 s10, s6485; SI-NEXT: s_mov_b32 s11, s7486; SI-NEXT: s_waitcnt lgkmcnt(0)487; SI-NEXT: s_mov_b32 s8, s2488; SI-NEXT: s_mov_b32 s9, s3489; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0490; SI-NEXT: s_mov_b32 s4, s0491; SI-NEXT: s_mov_b32 s5, s1492; SI-NEXT: s_waitcnt vmcnt(0)493; SI-NEXT: v_ffbh_u32_e32 v0, v0494; SI-NEXT: v_min_u32_e32 v0, 32, v0495; SI-NEXT: v_subrev_i32_e32 v0, vcc, 24, v0496; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0497; SI-NEXT: s_endpgm498;499; VI-LABEL: v_ctlz_i8:500; VI: ; %bb.0:501; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24502; VI-NEXT: s_mov_b32 s7, 0xf000503; VI-NEXT: s_mov_b32 s6, -1504; VI-NEXT: s_mov_b32 s10, s6505; VI-NEXT: s_mov_b32 s11, s7506; VI-NEXT: s_waitcnt lgkmcnt(0)507; VI-NEXT: s_mov_b32 s8, s2508; VI-NEXT: s_mov_b32 s9, s3509; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0510; VI-NEXT: s_mov_b32 s4, s0511; VI-NEXT: s_mov_b32 s5, s1512; VI-NEXT: s_waitcnt vmcnt(0)513; VI-NEXT: v_ffbh_u32_e32 v0, v0514; VI-NEXT: v_min_u32_e32 v0, 32, v0515; VI-NEXT: v_subrev_u32_e32 v0, vcc, 24, v0516; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0517; VI-NEXT: s_endpgm518;519; EG-LABEL: v_ctlz_i8:520; EG: ; %bb.0:521; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]522; EG-NEXT: TEX 0 @6523; EG-NEXT: ALU 15, @9, KC0[CB0:0-32], KC1[]524; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X525; EG-NEXT: CF_END526; EG-NEXT: PAD527; EG-NEXT: Fetch clause starting at 6:528; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1529; EG-NEXT: ALU clause starting at 8:530; EG-NEXT: MOV * T0.X, KC0[2].Z,531; EG-NEXT: ALU clause starting at 9:532; EG-NEXT: FFBH_UINT * T0.W, T0.X,533; EG-NEXT: CNDE_INT T0.W, T0.X, literal.x, PV.W,534; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,535; EG-NEXT: 32(4.484155e-44), 3(4.203895e-45)536; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,537; EG-NEXT: -24(nan), 0(0.000000e+00)538; EG-NEXT: AND_INT T0.W, PV.W, literal.x,539; EG-NEXT: LSHL * T1.W, T1.W, literal.y,540; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)541; EG-NEXT: LSHL T0.X, PV.W, PS,542; EG-NEXT: LSHL * T0.W, literal.x, PS,543; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)544; EG-NEXT: MOV T0.Y, 0.0,545; EG-NEXT: MOV * T0.Z, 0.0,546; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,547; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)548;549; GFX10-LABEL: v_ctlz_i8:550; GFX10: ; %bb.0:551; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24552; GFX10-NEXT: v_mov_b32_e32 v0, 0553; GFX10-NEXT: s_waitcnt lgkmcnt(0)554; GFX10-NEXT: global_load_ubyte v1, v0, s[2:3]555; GFX10-NEXT: s_waitcnt vmcnt(0)556; GFX10-NEXT: v_ffbh_u32_e32 v1, v1557; GFX10-NEXT: v_min_u32_e32 v1, 32, v1558; GFX10-NEXT: v_subrev_nc_u32_e32 v1, 24, v1559; GFX10-NEXT: global_store_byte v0, v1, s[0:1]560; GFX10-NEXT: s_endpgm561;562; GFX10-GISEL-LABEL: v_ctlz_i8:563; GFX10-GISEL: ; %bb.0:564; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24565; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, 0566; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)567; GFX10-GISEL-NEXT: global_load_ubyte v1, v0, s[2:3]568; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)569; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v1, v1570; GFX10-GISEL-NEXT: v_min_u32_e32 v1, 32, v1571; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v1, 0xffffffe8, v1572; GFX10-GISEL-NEXT: global_store_byte v0, v1, s[0:1]573; GFX10-GISEL-NEXT: s_endpgm574;575; GFX11-LABEL: v_ctlz_i8:576; GFX11: ; %bb.0:577; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24578; GFX11-NEXT: v_mov_b32_e32 v0, 0579; GFX11-NEXT: s_waitcnt lgkmcnt(0)580; GFX11-NEXT: global_load_u8 v1, v0, s[2:3]581; GFX11-NEXT: s_waitcnt vmcnt(0)582; GFX11-NEXT: v_clz_i32_u32_e32 v1, v1583; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)584; GFX11-NEXT: v_min_u32_e32 v1, 32, v1585; GFX11-NEXT: v_subrev_nc_u32_e32 v1, 24, v1586; GFX11-NEXT: global_store_b8 v0, v1, s[0:1]587; GFX11-NEXT: s_endpgm588 %val = load i8, ptr addrspace(1) %valptr589 %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 false) nounwind readnone590 store i8 %ctlz, ptr addrspace(1) %out591 ret void592}593 594define amdgpu_kernel void @s_ctlz_i64(ptr addrspace(1) noalias %out, [8 x i32], i64 %val) nounwind {595; SI-LABEL: s_ctlz_i64:596; SI: ; %bb.0:597; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x13598; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9599; SI-NEXT: s_mov_b32 s3, 0xf000600; SI-NEXT: s_mov_b32 s2, -1601; SI-NEXT: s_waitcnt lgkmcnt(0)602; SI-NEXT: s_flbit_i32_b64 s4, s[6:7]603; SI-NEXT: s_min_u32 s4, s4, 64604; SI-NEXT: v_mov_b32_e32 v1, 0605; SI-NEXT: v_mov_b32_e32 v0, s4606; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0607; SI-NEXT: s_endpgm608;609; VI-LABEL: s_ctlz_i64:610; VI: ; %bb.0:611; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x4c612; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24613; VI-NEXT: s_mov_b32 s3, 0xf000614; VI-NEXT: s_mov_b32 s2, -1615; VI-NEXT: v_mov_b32_e32 v1, 0616; VI-NEXT: s_waitcnt lgkmcnt(0)617; VI-NEXT: s_flbit_i32_b64 s4, s[6:7]618; VI-NEXT: s_min_u32 s4, s4, 64619; VI-NEXT: v_mov_b32_e32 v0, s4620; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0621; VI-NEXT: s_endpgm622;623; EG-LABEL: s_ctlz_i64:624; EG: ; %bb.0:625; EG-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]626; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1627; EG-NEXT: CF_END628; EG-NEXT: PAD629; EG-NEXT: ALU clause starting at 4:630; EG-NEXT: FFBH_UINT * T0.W, KC0[4].W,631; EG-NEXT: CNDE_INT * T0.W, KC0[4].W, literal.x, PV.W,632; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)633; EG-NEXT: FFBH_UINT T1.W, KC0[5].X,634; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,635; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)636; EG-NEXT: CNDE_INT T0.X, KC0[5].X, PS, PV.W,637; EG-NEXT: MOV T0.Y, 0.0,638; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,639; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)640;641; GFX10-LABEL: s_ctlz_i64:642; GFX10: ; %bb.0:643; GFX10-NEXT: s_clause 0x1644; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x4c645; GFX10-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24646; GFX10-NEXT: v_mov_b32_e32 v1, 0647; GFX10-NEXT: s_waitcnt lgkmcnt(0)648; GFX10-NEXT: s_flbit_i32_b64 s0, s[0:1]649; GFX10-NEXT: s_min_u32 s0, s0, 64650; GFX10-NEXT: v_mov_b32_e32 v0, s0651; GFX10-NEXT: global_store_dwordx2 v1, v[0:1], s[2:3]652; GFX10-NEXT: s_endpgm653;654; GFX10-GISEL-LABEL: s_ctlz_i64:655; GFX10-GISEL: ; %bb.0:656; GFX10-GISEL-NEXT: s_clause 0x1657; GFX10-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x4c658; GFX10-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24659; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0660; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)661; GFX10-GISEL-NEXT: s_flbit_i32_b64 s0, s[0:1]662; GFX10-GISEL-NEXT: s_mov_b32 s1, 0663; GFX10-GISEL-NEXT: s_min_u32 s0, s0, 64664; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0665; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1666; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]667; GFX10-GISEL-NEXT: s_endpgm668;669; GFX11-LABEL: s_ctlz_i64:670; GFX11: ; %bb.0:671; GFX11-NEXT: s_clause 0x1672; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x4c673; GFX11-NEXT: s_load_b64 s[2:3], s[4:5], 0x24674; GFX11-NEXT: s_waitcnt lgkmcnt(0)675; GFX11-NEXT: s_clz_i32_u64 s0, s[0:1]676; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)677; GFX11-NEXT: s_min_u32 s0, s0, 64678; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0679; GFX11-NEXT: global_store_b64 v1, v[0:1], s[2:3]680; GFX11-NEXT: s_endpgm681 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 false)682 store i64 %ctlz, ptr addrspace(1) %out683 ret void684}685 686define amdgpu_kernel void @s_ctlz_i64_trunc(ptr addrspace(1) noalias %out, i64 %val) nounwind {687; SI-LABEL: s_ctlz_i64_trunc:688; SI: ; %bb.0:689; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9690; SI-NEXT: s_mov_b32 s7, 0xf000691; SI-NEXT: s_waitcnt lgkmcnt(0)692; SI-NEXT: s_flbit_i32_b64 s2, s[2:3]693; SI-NEXT: s_min_u32 s2, s2, 64694; SI-NEXT: s_mov_b32 s6, -1695; SI-NEXT: s_mov_b32 s4, s0696; SI-NEXT: s_mov_b32 s5, s1697; SI-NEXT: v_mov_b32_e32 v0, s2698; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0699; SI-NEXT: s_endpgm700;701; VI-LABEL: s_ctlz_i64_trunc:702; VI: ; %bb.0:703; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24704; VI-NEXT: s_mov_b32 s7, 0xf000705; VI-NEXT: s_mov_b32 s6, -1706; VI-NEXT: s_waitcnt lgkmcnt(0)707; VI-NEXT: s_mov_b32 s4, s0708; VI-NEXT: s_flbit_i32_b64 s0, s[2:3]709; VI-NEXT: s_min_u32 s0, s0, 64710; VI-NEXT: s_mov_b32 s5, s1711; VI-NEXT: v_mov_b32_e32 v0, s0712; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0713; VI-NEXT: s_endpgm714;715; EG-LABEL: s_ctlz_i64_trunc:716; EG: ; %bb.0:717; EG-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[]718; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1719; EG-NEXT: CF_END720; EG-NEXT: PAD721; EG-NEXT: ALU clause starting at 4:722; EG-NEXT: FFBH_UINT * T0.W, KC0[2].W,723; EG-NEXT: CNDE_INT * T0.W, KC0[2].W, literal.x, PV.W,724; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)725; EG-NEXT: FFBH_UINT T1.W, KC0[3].X,726; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,727; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)728; EG-NEXT: CNDE_INT T0.X, KC0[3].X, PS, PV.W,729; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,730; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)731;732; GFX10-LABEL: s_ctlz_i64_trunc:733; GFX10: ; %bb.0:734; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24735; GFX10-NEXT: v_mov_b32_e32 v0, 0736; GFX10-NEXT: s_waitcnt lgkmcnt(0)737; GFX10-NEXT: s_flbit_i32_b64 s2, s[2:3]738; GFX10-NEXT: s_min_u32 s2, s2, 64739; GFX10-NEXT: v_mov_b32_e32 v1, s2740; GFX10-NEXT: global_store_dword v0, v1, s[0:1]741; GFX10-NEXT: s_endpgm742;743; GFX10-GISEL-LABEL: s_ctlz_i64_trunc:744; GFX10-GISEL: ; %bb.0:745; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24746; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0747; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)748; GFX10-GISEL-NEXT: s_flbit_i32_b64 s2, s[2:3]749; GFX10-GISEL-NEXT: s_min_u32 s2, s2, 64750; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2751; GFX10-GISEL-NEXT: global_store_dword v1, v0, s[0:1]752; GFX10-GISEL-NEXT: s_endpgm753;754; GFX11-LABEL: s_ctlz_i64_trunc:755; GFX11: ; %bb.0:756; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24757; GFX11-NEXT: s_waitcnt lgkmcnt(0)758; GFX11-NEXT: s_clz_i32_u64 s2, s[2:3]759; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)760; GFX11-NEXT: s_min_u32 s2, s2, 64761; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2762; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]763; GFX11-NEXT: s_endpgm764 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 false)765 %trunc = trunc i64 %ctlz to i32766 store i32 %trunc, ptr addrspace(1) %out767 ret void768}769 770define amdgpu_kernel void @v_ctlz_i64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {771; SI-LABEL: v_ctlz_i64:772; SI: ; %bb.0:773; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9774; SI-NEXT: s_mov_b32 s7, 0xf000775; SI-NEXT: s_mov_b32 s6, 0776; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0777; SI-NEXT: v_mov_b32_e32 v1, 0778; SI-NEXT: s_waitcnt lgkmcnt(0)779; SI-NEXT: s_mov_b64 s[4:5], s[2:3]780; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64781; SI-NEXT: s_mov_b64 s[2:3], s[6:7]782; SI-NEXT: s_waitcnt vmcnt(0)783; SI-NEXT: v_ffbh_u32_e32 v2, v2784; SI-NEXT: v_min_u32_e32 v2, 0xffffffdf, v2785; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v2786; SI-NEXT: v_ffbh_u32_e32 v3, v3787; SI-NEXT: v_min3_u32 v2, v2, v3, 64788; SI-NEXT: v_mov_b32_e32 v3, v1789; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64790; SI-NEXT: s_endpgm791;792; VI-LABEL: v_ctlz_i64:793; VI: ; %bb.0:794; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24795; VI-NEXT: v_lshlrev_b32_e32 v3, 3, v0796; VI-NEXT: v_mov_b32_e32 v2, 0797; VI-NEXT: s_waitcnt lgkmcnt(0)798; VI-NEXT: v_mov_b32_e32 v1, s3799; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v3800; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc801; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]802; VI-NEXT: v_mov_b32_e32 v4, s1803; VI-NEXT: v_add_u32_e32 v3, vcc, s0, v3804; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc805; VI-NEXT: s_waitcnt vmcnt(0)806; VI-NEXT: v_ffbh_u32_e32 v0, v0807; VI-NEXT: v_add_u32_e64 v0, s[0:1], v0, 32 clamp808; VI-NEXT: v_ffbh_u32_e32 v1, v1809; VI-NEXT: v_min3_u32 v1, v0, v1, 64810; VI-NEXT: flat_store_dwordx2 v[3:4], v[1:2]811; VI-NEXT: s_endpgm812;813; EG-LABEL: v_ctlz_i64:814; EG: ; %bb.0:815; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]816; EG-NEXT: TEX 0 @6817; EG-NEXT: ALU 10, @11, KC0[CB0:0-32], KC1[]818; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1819; EG-NEXT: CF_END820; EG-NEXT: PAD821; EG-NEXT: Fetch clause starting at 6:822; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1823; EG-NEXT: ALU clause starting at 8:824; EG-NEXT: LSHL * T0.W, T0.X, literal.x,825; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)826; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,827; EG-NEXT: ALU clause starting at 11:828; EG-NEXT: FFBH_UINT * T1.W, T0.X,829; EG-NEXT: CNDE_INT * T1.W, T0.X, literal.x, PV.W,830; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)831; EG-NEXT: FFBH_UINT T2.W, T0.Y,832; EG-NEXT: ADD_INT * T1.W, PV.W, literal.x,833; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)834; EG-NEXT: CNDE_INT T0.X, T0.Y, PS, PV.W,835; EG-NEXT: MOV T0.Y, 0.0,836; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,837; EG-NEXT: LSHR * T1.X, PV.W, literal.x,838; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)839;840; GFX10-LABEL: v_ctlz_i64:841; GFX10: ; %bb.0:842; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24843; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v0844; GFX10-NEXT: s_waitcnt lgkmcnt(0)845; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3]846; GFX10-NEXT: s_waitcnt vmcnt(0)847; GFX10-NEXT: v_ffbh_u32_e32 v0, v0848; GFX10-NEXT: v_ffbh_u32_e32 v1, v1849; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, 32 clamp850; GFX10-NEXT: v_min3_u32 v0, v0, v1, 64851; GFX10-NEXT: v_mov_b32_e32 v1, 0852; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]853; GFX10-NEXT: s_endpgm854;855; GFX10-GISEL-LABEL: v_ctlz_i64:856; GFX10-GISEL: ; %bb.0:857; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24858; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v2, 3, v0859; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)860; GFX10-GISEL-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3]861; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)862; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v0, v0863; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v1, v1864; GFX10-GISEL-NEXT: v_add_nc_u32_e64 v0, v0, 32 clamp865; GFX10-GISEL-NEXT: v_min_u32_e32 v0, v1, v0866; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0867; GFX10-GISEL-NEXT: v_min_u32_e32 v0, 64, v0868; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]869; GFX10-GISEL-NEXT: s_endpgm870;871; GFX11-LABEL: v_ctlz_i64:872; GFX11: ; %bb.0:873; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24874; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0875; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)876; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0877; GFX11-NEXT: s_waitcnt lgkmcnt(0)878; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3]879; GFX11-NEXT: s_waitcnt vmcnt(0)880; GFX11-NEXT: v_clz_i32_u32_e32 v0, v0881; GFX11-NEXT: v_clz_i32_u32_e32 v1, v1882; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)883; GFX11-NEXT: v_add_nc_u32_e64 v0, v0, 32 clamp884; GFX11-NEXT: v_min3_u32 v0, v0, v1, 64885; GFX11-NEXT: v_mov_b32_e32 v1, 0886; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]887; GFX11-NEXT: s_endpgm888 %tid = call i32 @llvm.amdgcn.workitem.id.x()889 %in.gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid890 %out.gep = getelementptr i64, ptr addrspace(1) %out, i32 %tid891 %val = load i64, ptr addrspace(1) %in.gep892 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 false)893 store i64 %ctlz, ptr addrspace(1) %out.gep894 ret void895}896 897define amdgpu_kernel void @v_ctlz_i64_trunc(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {898; SI-LABEL: v_ctlz_i64_trunc:899; SI: ; %bb.0:900; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9901; SI-NEXT: s_mov_b32 s7, 0xf000902; SI-NEXT: s_mov_b32 s6, 0903; SI-NEXT: v_lshlrev_b32_e32 v1, 3, v0904; SI-NEXT: v_mov_b32_e32 v2, 0905; SI-NEXT: s_waitcnt lgkmcnt(0)906; SI-NEXT: s_mov_b64 s[4:5], s[2:3]907; SI-NEXT: buffer_load_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr64908; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v0909; SI-NEXT: s_mov_b64 s[2:3], s[6:7]910; SI-NEXT: s_waitcnt vmcnt(0)911; SI-NEXT: v_ffbh_u32_e32 v0, v3912; SI-NEXT: v_min_u32_e32 v0, 0xffffffdf, v0913; SI-NEXT: v_add_i32_e32 v0, vcc, 32, v0914; SI-NEXT: v_ffbh_u32_e32 v3, v4915; SI-NEXT: v_min3_u32 v0, v0, v3, 64916; SI-NEXT: buffer_store_dword v0, v[1:2], s[0:3], 0 addr64917; SI-NEXT: s_endpgm918;919; VI-LABEL: v_ctlz_i64_trunc:920; VI: ; %bb.0:921; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24922; VI-NEXT: v_lshlrev_b32_e32 v1, 3, v0923; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0924; VI-NEXT: s_waitcnt lgkmcnt(0)925; VI-NEXT: v_mov_b32_e32 v2, s3926; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v1927; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc928; VI-NEXT: flat_load_dwordx2 v[1:2], v[1:2]929; VI-NEXT: v_add_u32_e32 v3, vcc, s0, v0930; VI-NEXT: v_mov_b32_e32 v4, s1931; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc932; VI-NEXT: s_waitcnt vmcnt(0)933; VI-NEXT: v_ffbh_u32_e32 v0, v1934; VI-NEXT: v_add_u32_e64 v0, s[0:1], v0, 32 clamp935; VI-NEXT: v_ffbh_u32_e32 v1, v2936; VI-NEXT: v_min3_u32 v0, v0, v1, 64937; VI-NEXT: flat_store_dword v[3:4], v0938; VI-NEXT: s_endpgm939;940; EG-LABEL: v_ctlz_i64_trunc:941; EG: ; %bb.0:942; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]943; EG-NEXT: TEX 0 @6944; EG-NEXT: ALU 10, @11, KC0[CB0:0-32], KC1[]945; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1946; EG-NEXT: CF_END947; EG-NEXT: PAD948; EG-NEXT: Fetch clause starting at 6:949; EG-NEXT: VTX_READ_64 T1.XY, T1.X, 0, #1950; EG-NEXT: ALU clause starting at 8:951; EG-NEXT: LSHL * T0.W, T0.X, literal.x,952; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)953; EG-NEXT: ADD_INT * T1.X, KC0[2].Z, PV.W,954; EG-NEXT: ALU clause starting at 11:955; EG-NEXT: FFBH_UINT * T0.W, T1.X,956; EG-NEXT: CNDE_INT * T0.W, T1.X, literal.x, PV.W,957; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)958; EG-NEXT: LSHL T0.Z, T0.X, literal.x,959; EG-NEXT: FFBH_UINT T1.W, T1.Y,960; EG-NEXT: ADD_INT * T0.W, PV.W, literal.y,961; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)962; EG-NEXT: CNDE_INT T0.X, T1.Y, PS, PV.W,963; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, PV.Z,964; EG-NEXT: LSHR * T1.X, PV.W, literal.x,965; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)966;967; GFX10-LABEL: v_ctlz_i64_trunc:968; GFX10: ; %bb.0:969; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24970; GFX10-NEXT: v_lshlrev_b32_e32 v1, 3, v0971; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0972; GFX10-NEXT: s_waitcnt lgkmcnt(0)973; GFX10-NEXT: global_load_dwordx2 v[1:2], v1, s[2:3]974; GFX10-NEXT: s_waitcnt vmcnt(0)975; GFX10-NEXT: v_ffbh_u32_e32 v1, v1976; GFX10-NEXT: v_ffbh_u32_e32 v2, v2977; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, 32 clamp978; GFX10-NEXT: v_min3_u32 v1, v1, v2, 64979; GFX10-NEXT: global_store_dword v0, v1, s[0:1]980; GFX10-NEXT: s_endpgm981;982; GFX10-GISEL-LABEL: v_ctlz_i64_trunc:983; GFX10-GISEL: ; %bb.0:984; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24985; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v1, 3, v0986; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0987; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)988; GFX10-GISEL-NEXT: global_load_dwordx2 v[1:2], v1, s[2:3]989; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)990; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v1, v1991; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v2, v2992; GFX10-GISEL-NEXT: v_add_nc_u32_e64 v1, v1, 32 clamp993; GFX10-GISEL-NEXT: v_min_u32_e32 v1, v2, v1994; GFX10-GISEL-NEXT: v_min_u32_e32 v1, 64, v1995; GFX10-GISEL-NEXT: global_store_dword v0, v1, s[0:1]996; GFX10-GISEL-NEXT: s_endpgm997;998; GFX11-LABEL: v_ctlz_i64_trunc:999; GFX11: ; %bb.0:1000; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241001; GFX11-NEXT: v_and_b32_e32 v2, 0x3ff, v01002; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1003; GFX11-NEXT: v_lshlrev_b32_e32 v0, 3, v21004; GFX11-NEXT: v_lshlrev_b32_e32 v2, 2, v21005; GFX11-NEXT: s_waitcnt lgkmcnt(0)1006; GFX11-NEXT: global_load_b64 v[0:1], v0, s[2:3]1007; GFX11-NEXT: s_waitcnt vmcnt(0)1008; GFX11-NEXT: v_clz_i32_u32_e32 v0, v01009; GFX11-NEXT: v_clz_i32_u32_e32 v1, v11010; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1011; GFX11-NEXT: v_add_nc_u32_e64 v0, v0, 32 clamp1012; GFX11-NEXT: v_min3_u32 v0, v0, v1, 641013; GFX11-NEXT: global_store_b32 v2, v0, s[0:1]1014; GFX11-NEXT: s_endpgm1015 %tid = call i32 @llvm.amdgcn.workitem.id.x()1016 %in.gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid1017 %out.gep = getelementptr i32, ptr addrspace(1) %out, i32 %tid1018 %val = load i64, ptr addrspace(1) %in.gep1019 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 false)1020 %trunc = trunc i64 %ctlz to i321021 store i32 %trunc, ptr addrspace(1) %out.gep1022 ret void1023}1024 1025define amdgpu_kernel void @v_ctlz_i32_sel_eq_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {1026; SI-LABEL: v_ctlz_i32_sel_eq_neg1:1027; SI: ; %bb.0:1028; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91029; SI-NEXT: s_mov_b32 s7, 0xf0001030; SI-NEXT: s_mov_b32 s10, 01031; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v01032; SI-NEXT: v_mov_b32_e32 v1, 01033; SI-NEXT: s_mov_b32 s11, s71034; SI-NEXT: s_waitcnt lgkmcnt(0)1035; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1036; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr641037; SI-NEXT: s_mov_b32 s6, -11038; SI-NEXT: s_mov_b32 s4, s01039; SI-NEXT: s_mov_b32 s5, s11040; SI-NEXT: s_waitcnt vmcnt(0)1041; SI-NEXT: v_ffbh_u32_e32 v0, v01042; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01043; SI-NEXT: s_endpgm1044;1045; VI-LABEL: v_ctlz_i32_sel_eq_neg1:1046; VI: ; %bb.0:1047; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241048; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v01049; VI-NEXT: s_waitcnt lgkmcnt(0)1050; VI-NEXT: v_mov_b32_e32 v1, s31051; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01052; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1053; VI-NEXT: flat_load_dword v0, v[0:1]1054; VI-NEXT: s_mov_b32 s3, 0xf0001055; VI-NEXT: s_mov_b32 s2, -11056; VI-NEXT: s_waitcnt vmcnt(0)1057; VI-NEXT: v_ffbh_u32_e32 v0, v01058; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01059; VI-NEXT: s_endpgm1060;1061; EG-LABEL: v_ctlz_i32_sel_eq_neg1:1062; EG: ; %bb.0:1063; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]1064; EG-NEXT: TEX 0 @61065; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]1066; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11067; EG-NEXT: CF_END1068; EG-NEXT: PAD1069; EG-NEXT: Fetch clause starting at 6:1070; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11071; EG-NEXT: ALU clause starting at 8:1072; EG-NEXT: LSHL * T0.W, T0.X, literal.x,1073; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1074; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1075; EG-NEXT: ALU clause starting at 11:1076; EG-NEXT: FFBH_UINT * T0.W, T0.X,1077; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W,1078; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1079; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W,1080; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,1081; EG-NEXT: -1(nan), 2(2.802597e-45)1082;1083; GFX10-LABEL: v_ctlz_i32_sel_eq_neg1:1084; GFX10: ; %bb.0:1085; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241086; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v01087; GFX10-NEXT: v_mov_b32_e32 v1, 01088; GFX10-NEXT: s_waitcnt lgkmcnt(0)1089; GFX10-NEXT: global_load_dword v0, v0, s[2:3]1090; GFX10-NEXT: s_waitcnt vmcnt(0)1091; GFX10-NEXT: v_ffbh_u32_e32 v0, v01092; GFX10-NEXT: global_store_dword v1, v0, s[0:1]1093; GFX10-NEXT: s_endpgm1094;1095; GFX10-GISEL-LABEL: v_ctlz_i32_sel_eq_neg1:1096; GFX10-GISEL: ; %bb.0:1097; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241098; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v01099; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)1100; GFX10-GISEL-NEXT: global_load_dword v0, v0, s[2:3]1101; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)1102; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v1, v01103; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v01104; GFX10-GISEL-NEXT: v_min_u32_e32 v1, 32, v11105; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, -1, vcc_lo1106; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 01107; GFX10-GISEL-NEXT: global_store_dword v1, v0, s[0:1]1108; GFX10-GISEL-NEXT: s_endpgm1109;1110; GFX11-LABEL: v_ctlz_i32_sel_eq_neg1:1111; GFX11: ; %bb.0:1112; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241113; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v01114; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1115; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v01116; GFX11-NEXT: s_waitcnt lgkmcnt(0)1117; GFX11-NEXT: global_load_b32 v0, v0, s[2:3]1118; GFX11-NEXT: s_waitcnt vmcnt(0)1119; GFX11-NEXT: v_clz_i32_u32_e32 v0, v01120; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]1121; GFX11-NEXT: s_endpgm1122 %tid = call i32 @llvm.amdgcn.workitem.id.x()1123 %in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid1124 %val = load i32, ptr addrspace(1) %in.gep1125 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone1126 %cmp = icmp eq i32 %val, 01127 %sel = select i1 %cmp, i32 -1, i32 %ctlz1128 store i32 %sel, ptr addrspace(1) %out1129 ret void1130}1131 1132define amdgpu_kernel void @v_ctlz_i32_sel_ne_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {1133; SI-LABEL: v_ctlz_i32_sel_ne_neg1:1134; SI: ; %bb.0:1135; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91136; SI-NEXT: s_mov_b32 s7, 0xf0001137; SI-NEXT: s_mov_b32 s10, 01138; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v01139; SI-NEXT: v_mov_b32_e32 v1, 01140; SI-NEXT: s_mov_b32 s11, s71141; SI-NEXT: s_waitcnt lgkmcnt(0)1142; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1143; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr641144; SI-NEXT: s_mov_b32 s6, -11145; SI-NEXT: s_mov_b32 s4, s01146; SI-NEXT: s_mov_b32 s5, s11147; SI-NEXT: s_waitcnt vmcnt(0)1148; SI-NEXT: v_ffbh_u32_e32 v0, v01149; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01150; SI-NEXT: s_endpgm1151;1152; VI-LABEL: v_ctlz_i32_sel_ne_neg1:1153; VI: ; %bb.0:1154; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241155; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v01156; VI-NEXT: s_waitcnt lgkmcnt(0)1157; VI-NEXT: v_mov_b32_e32 v1, s31158; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01159; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1160; VI-NEXT: flat_load_dword v0, v[0:1]1161; VI-NEXT: s_mov_b32 s3, 0xf0001162; VI-NEXT: s_mov_b32 s2, -11163; VI-NEXT: s_waitcnt vmcnt(0)1164; VI-NEXT: v_ffbh_u32_e32 v0, v01165; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01166; VI-NEXT: s_endpgm1167;1168; EG-LABEL: v_ctlz_i32_sel_ne_neg1:1169; EG: ; %bb.0:1170; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]1171; EG-NEXT: TEX 0 @61172; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]1173; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11174; EG-NEXT: CF_END1175; EG-NEXT: PAD1176; EG-NEXT: Fetch clause starting at 6:1177; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11178; EG-NEXT: ALU clause starting at 8:1179; EG-NEXT: LSHL * T0.W, T0.X, literal.x,1180; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1181; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1182; EG-NEXT: ALU clause starting at 11:1183; EG-NEXT: FFBH_UINT * T0.W, T0.X,1184; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W,1185; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1186; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W,1187; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,1188; EG-NEXT: -1(nan), 2(2.802597e-45)1189;1190; GFX10-LABEL: v_ctlz_i32_sel_ne_neg1:1191; GFX10: ; %bb.0:1192; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241193; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v01194; GFX10-NEXT: v_mov_b32_e32 v1, 01195; GFX10-NEXT: s_waitcnt lgkmcnt(0)1196; GFX10-NEXT: global_load_dword v0, v0, s[2:3]1197; GFX10-NEXT: s_waitcnt vmcnt(0)1198; GFX10-NEXT: v_ffbh_u32_e32 v0, v01199; GFX10-NEXT: global_store_dword v1, v0, s[0:1]1200; GFX10-NEXT: s_endpgm1201;1202; GFX10-GISEL-LABEL: v_ctlz_i32_sel_ne_neg1:1203; GFX10-GISEL: ; %bb.0:1204; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241205; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v01206; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)1207; GFX10-GISEL-NEXT: global_load_dword v0, v0, s[2:3]1208; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)1209; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v1, v01210; GFX10-GISEL-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v01211; GFX10-GISEL-NEXT: v_min_u32_e32 v1, 32, v11212; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, -1, v1, vcc_lo1213; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 01214; GFX10-GISEL-NEXT: global_store_dword v1, v0, s[0:1]1215; GFX10-GISEL-NEXT: s_endpgm1216;1217; GFX11-LABEL: v_ctlz_i32_sel_ne_neg1:1218; GFX11: ; %bb.0:1219; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241220; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v01221; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1222; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v01223; GFX11-NEXT: s_waitcnt lgkmcnt(0)1224; GFX11-NEXT: global_load_b32 v0, v0, s[2:3]1225; GFX11-NEXT: s_waitcnt vmcnt(0)1226; GFX11-NEXT: v_clz_i32_u32_e32 v0, v01227; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]1228; GFX11-NEXT: s_endpgm1229 %tid = call i32 @llvm.amdgcn.workitem.id.x()1230 %in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid1231 %val = load i32, ptr addrspace(1) %in.gep1232 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone1233 %cmp = icmp ne i32 %val, 01234 %sel = select i1 %cmp, i32 %ctlz, i32 -11235 store i32 %sel, ptr addrspace(1) %out1236 ret void1237}1238 1239; TODO: Should be able to eliminate select here as well.1240define amdgpu_kernel void @v_ctlz_i32_sel_eq_bitwidth(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {1241; SI-LABEL: v_ctlz_i32_sel_eq_bitwidth:1242; SI: ; %bb.0:1243; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91244; SI-NEXT: s_mov_b32 s7, 0xf0001245; SI-NEXT: s_mov_b32 s10, 01246; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v01247; SI-NEXT: v_mov_b32_e32 v1, 01248; SI-NEXT: s_mov_b32 s11, s71249; SI-NEXT: s_waitcnt lgkmcnt(0)1250; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1251; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr641252; SI-NEXT: s_mov_b32 s6, -11253; SI-NEXT: s_mov_b32 s4, s01254; SI-NEXT: s_mov_b32 s5, s11255; SI-NEXT: s_waitcnt vmcnt(0)1256; SI-NEXT: v_ffbh_u32_e32 v0, v01257; SI-NEXT: v_min_u32_e32 v0, 32, v01258; SI-NEXT: v_cmp_ne_u32_e32 vcc, 32, v01259; SI-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc1260; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01261; SI-NEXT: s_endpgm1262;1263; VI-LABEL: v_ctlz_i32_sel_eq_bitwidth:1264; VI: ; %bb.0:1265; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241266; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v01267; VI-NEXT: s_waitcnt lgkmcnt(0)1268; VI-NEXT: v_mov_b32_e32 v1, s31269; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01270; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1271; VI-NEXT: flat_load_dword v0, v[0:1]1272; VI-NEXT: s_mov_b32 s3, 0xf0001273; VI-NEXT: s_mov_b32 s2, -11274; VI-NEXT: s_waitcnt vmcnt(0)1275; VI-NEXT: v_ffbh_u32_e32 v0, v01276; VI-NEXT: v_min_u32_e32 v0, 32, v01277; VI-NEXT: v_cmp_ne_u32_e32 vcc, 32, v01278; VI-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc1279; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01280; VI-NEXT: s_endpgm1281;1282; EG-LABEL: v_ctlz_i32_sel_eq_bitwidth:1283; EG: ; %bb.0:1284; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]1285; EG-NEXT: TEX 0 @61286; EG-NEXT: ALU 7, @11, KC0[CB0:0-32], KC1[]1287; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11288; EG-NEXT: CF_END1289; EG-NEXT: PAD1290; EG-NEXT: Fetch clause starting at 6:1291; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11292; EG-NEXT: ALU clause starting at 8:1293; EG-NEXT: LSHL * T0.W, T0.X, literal.x,1294; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1295; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1296; EG-NEXT: ALU clause starting at 11:1297; EG-NEXT: FFBH_UINT * T0.W, T0.X,1298; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W,1299; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1300; EG-NEXT: SETE_INT * T1.W, PV.W, literal.x,1301; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1302; EG-NEXT: CNDE_INT T0.X, PV.W, T0.W, literal.x,1303; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,1304; EG-NEXT: -1(nan), 2(2.802597e-45)1305;1306; GFX10-LABEL: v_ctlz_i32_sel_eq_bitwidth:1307; GFX10: ; %bb.0:1308; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241309; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v01310; GFX10-NEXT: v_mov_b32_e32 v1, 01311; GFX10-NEXT: s_waitcnt lgkmcnt(0)1312; GFX10-NEXT: global_load_dword v0, v0, s[2:3]1313; GFX10-NEXT: s_waitcnt vmcnt(0)1314; GFX10-NEXT: v_ffbh_u32_e32 v0, v01315; GFX10-NEXT: v_min_u32_e32 v0, 32, v01316; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 32, v01317; GFX10-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc_lo1318; GFX10-NEXT: global_store_dword v1, v0, s[0:1]1319; GFX10-NEXT: s_endpgm1320;1321; GFX10-GISEL-LABEL: v_ctlz_i32_sel_eq_bitwidth:1322; GFX10-GISEL: ; %bb.0:1323; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241324; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v01325; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 01326; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)1327; GFX10-GISEL-NEXT: global_load_dword v0, v0, s[2:3]1328; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)1329; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v0, v01330; GFX10-GISEL-NEXT: v_min_u32_e32 v0, 32, v01331; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 32, v01332; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc_lo1333; GFX10-GISEL-NEXT: global_store_dword v1, v0, s[0:1]1334; GFX10-GISEL-NEXT: s_endpgm1335;1336; GFX11-LABEL: v_ctlz_i32_sel_eq_bitwidth:1337; GFX11: ; %bb.0:1338; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241339; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v01340; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)1341; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v01342; GFX11-NEXT: s_waitcnt lgkmcnt(0)1343; GFX11-NEXT: global_load_b32 v0, v0, s[2:3]1344; GFX11-NEXT: s_waitcnt vmcnt(0)1345; GFX11-NEXT: v_clz_i32_u32_e32 v0, v01346; GFX11-NEXT: v_min_u32_e32 v0, 32, v01347; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1348; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 32, v01349; GFX11-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc_lo1350; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]1351; GFX11-NEXT: s_endpgm1352 %tid = call i32 @llvm.amdgcn.workitem.id.x()1353 %in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid1354 %val = load i32, ptr addrspace(1) %in.gep1355 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone1356 %cmp = icmp eq i32 %ctlz, 321357 %sel = select i1 %cmp, i32 -1, i32 %ctlz1358 store i32 %sel, ptr addrspace(1) %out1359 ret void1360}1361 1362define amdgpu_kernel void @v_ctlz_i32_sel_ne_bitwidth(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {1363; SI-LABEL: v_ctlz_i32_sel_ne_bitwidth:1364; SI: ; %bb.0:1365; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91366; SI-NEXT: s_mov_b32 s7, 0xf0001367; SI-NEXT: s_mov_b32 s10, 01368; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v01369; SI-NEXT: v_mov_b32_e32 v1, 01370; SI-NEXT: s_mov_b32 s11, s71371; SI-NEXT: s_waitcnt lgkmcnt(0)1372; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1373; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr641374; SI-NEXT: s_mov_b32 s6, -11375; SI-NEXT: s_mov_b32 s4, s01376; SI-NEXT: s_mov_b32 s5, s11377; SI-NEXT: s_waitcnt vmcnt(0)1378; SI-NEXT: v_ffbh_u32_e32 v0, v01379; SI-NEXT: v_min_u32_e32 v0, 32, v01380; SI-NEXT: v_cmp_ne_u32_e32 vcc, 32, v01381; SI-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc1382; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01383; SI-NEXT: s_endpgm1384;1385; VI-LABEL: v_ctlz_i32_sel_ne_bitwidth:1386; VI: ; %bb.0:1387; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241388; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v01389; VI-NEXT: s_waitcnt lgkmcnt(0)1390; VI-NEXT: v_mov_b32_e32 v1, s31391; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01392; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1393; VI-NEXT: flat_load_dword v0, v[0:1]1394; VI-NEXT: s_mov_b32 s3, 0xf0001395; VI-NEXT: s_mov_b32 s2, -11396; VI-NEXT: s_waitcnt vmcnt(0)1397; VI-NEXT: v_ffbh_u32_e32 v0, v01398; VI-NEXT: v_min_u32_e32 v0, 32, v01399; VI-NEXT: v_cmp_ne_u32_e32 vcc, 32, v01400; VI-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc1401; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01402; VI-NEXT: s_endpgm1403;1404; EG-LABEL: v_ctlz_i32_sel_ne_bitwidth:1405; EG: ; %bb.0:1406; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]1407; EG-NEXT: TEX 0 @61408; EG-NEXT: ALU 7, @11, KC0[CB0:0-32], KC1[]1409; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11410; EG-NEXT: CF_END1411; EG-NEXT: PAD1412; EG-NEXT: Fetch clause starting at 6:1413; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11414; EG-NEXT: ALU clause starting at 8:1415; EG-NEXT: LSHL * T0.W, T0.X, literal.x,1416; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1417; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1418; EG-NEXT: ALU clause starting at 11:1419; EG-NEXT: FFBH_UINT * T0.W, T0.X,1420; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W,1421; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1422; EG-NEXT: SETNE_INT * T1.W, PV.W, literal.x,1423; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1424; EG-NEXT: CNDE_INT T0.X, PV.W, literal.x, T0.W,1425; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,1426; EG-NEXT: -1(nan), 2(2.802597e-45)1427;1428; GFX10-LABEL: v_ctlz_i32_sel_ne_bitwidth:1429; GFX10: ; %bb.0:1430; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241431; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v01432; GFX10-NEXT: v_mov_b32_e32 v1, 01433; GFX10-NEXT: s_waitcnt lgkmcnt(0)1434; GFX10-NEXT: global_load_dword v0, v0, s[2:3]1435; GFX10-NEXT: s_waitcnt vmcnt(0)1436; GFX10-NEXT: v_ffbh_u32_e32 v0, v01437; GFX10-NEXT: v_min_u32_e32 v0, 32, v01438; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 32, v01439; GFX10-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc_lo1440; GFX10-NEXT: global_store_dword v1, v0, s[0:1]1441; GFX10-NEXT: s_endpgm1442;1443; GFX10-GISEL-LABEL: v_ctlz_i32_sel_ne_bitwidth:1444; GFX10-GISEL: ; %bb.0:1445; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241446; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v01447; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 01448; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)1449; GFX10-GISEL-NEXT: global_load_dword v0, v0, s[2:3]1450; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)1451; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v0, v01452; GFX10-GISEL-NEXT: v_min_u32_e32 v0, 32, v01453; GFX10-GISEL-NEXT: v_cmp_ne_u32_e32 vcc_lo, 32, v01454; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc_lo1455; GFX10-GISEL-NEXT: global_store_dword v1, v0, s[0:1]1456; GFX10-GISEL-NEXT: s_endpgm1457;1458; GFX11-LABEL: v_ctlz_i32_sel_ne_bitwidth:1459; GFX11: ; %bb.0:1460; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241461; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v01462; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)1463; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v01464; GFX11-NEXT: s_waitcnt lgkmcnt(0)1465; GFX11-NEXT: global_load_b32 v0, v0, s[2:3]1466; GFX11-NEXT: s_waitcnt vmcnt(0)1467; GFX11-NEXT: v_clz_i32_u32_e32 v0, v01468; GFX11-NEXT: v_min_u32_e32 v0, 32, v01469; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1470; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 32, v01471; GFX11-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc_lo1472; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]1473; GFX11-NEXT: s_endpgm1474 %tid = call i32 @llvm.amdgcn.workitem.id.x()1475 %in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid1476 %val = load i32, ptr addrspace(1) %in.gep1477 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone1478 %cmp = icmp ne i32 %ctlz, 321479 %sel = select i1 %cmp, i32 %ctlz, i32 -11480 store i32 %sel, ptr addrspace(1) %out1481 ret void1482}1483 1484 define amdgpu_kernel void @v_ctlz_i8_sel_eq_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {1485; SI-LABEL: v_ctlz_i8_sel_eq_neg1:1486; SI: ; %bb.0:1487; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91488; SI-NEXT: s_mov_b32 s7, 0xf0001489; SI-NEXT: v_mov_b32_e32 v1, 01490; SI-NEXT: s_mov_b32 s10, 01491; SI-NEXT: s_mov_b32 s11, s71492; SI-NEXT: s_waitcnt lgkmcnt(0)1493; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1494; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[8:11], 0 addr641495; SI-NEXT: s_mov_b32 s6, -11496; SI-NEXT: s_mov_b32 s4, s01497; SI-NEXT: s_mov_b32 s5, s11498; SI-NEXT: s_waitcnt vmcnt(0)1499; SI-NEXT: v_ffbh_u32_e32 v0, v01500; SI-NEXT: buffer_store_byte v0, off, s[4:7], 01501; SI-NEXT: s_endpgm1502;1503; VI-LABEL: v_ctlz_i8_sel_eq_neg1:1504; VI: ; %bb.0:1505; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241506; VI-NEXT: s_waitcnt lgkmcnt(0)1507; VI-NEXT: v_mov_b32_e32 v1, s31508; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01509; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1510; VI-NEXT: flat_load_ubyte v0, v[0:1]1511; VI-NEXT: s_mov_b32 s3, 0xf0001512; VI-NEXT: s_mov_b32 s2, -11513; VI-NEXT: s_waitcnt vmcnt(0)1514; VI-NEXT: v_ffbh_u32_e32 v0, v01515; VI-NEXT: buffer_store_byte v0, off, s[0:3], 01516; VI-NEXT: s_endpgm1517;1518; EG-LABEL: v_ctlz_i8_sel_eq_neg1:1519; EG: ; %bb.0:1520; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]1521; EG-NEXT: TEX 0 @61522; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[]1523; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1524; EG-NEXT: CF_END1525; EG-NEXT: PAD1526; EG-NEXT: Fetch clause starting at 6:1527; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #11528; EG-NEXT: ALU clause starting at 8:1529; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, T0.X,1530; EG-NEXT: ALU clause starting at 9:1531; EG-NEXT: FFBH_UINT T0.W, T0.X,1532; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,1533; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1534; EG-NEXT: AND_INT T0.W, PV.W, literal.x,1535; EG-NEXT: LSHL * T1.W, PS, literal.y,1536; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)1537; EG-NEXT: LSHL T0.X, PV.W, PS,1538; EG-NEXT: LSHL * T0.W, literal.x, PS,1539; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)1540; EG-NEXT: MOV T0.Y, 0.0,1541; EG-NEXT: MOV * T0.Z, 0.0,1542; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1543; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1544;1545; GFX10-LABEL: v_ctlz_i8_sel_eq_neg1:1546; GFX10: ; %bb.0:1547; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241548; GFX10-NEXT: v_mov_b32_e32 v1, 01549; GFX10-NEXT: s_waitcnt lgkmcnt(0)1550; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3]1551; GFX10-NEXT: s_waitcnt vmcnt(0)1552; GFX10-NEXT: v_ffbh_u32_e32 v0, v01553; GFX10-NEXT: global_store_byte v1, v0, s[0:1]1554; GFX10-NEXT: s_endpgm1555;1556; GFX10-GISEL-LABEL: v_ctlz_i8_sel_eq_neg1:1557; GFX10-GISEL: ; %bb.0:1558; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241559; GFX10-GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v01560; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)1561; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s21562; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s31563; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v1, v01564; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v2, v3, vcc_lo1565; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off1566; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)1567; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v1, v01568; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v01569; GFX10-GISEL-NEXT: v_min_u32_e32 v1, 32, v11570; GFX10-GISEL-NEXT: v_add_nc_u16 v1, 0xffe8, v11571; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0xffff, vcc_lo1572; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 01573; GFX10-GISEL-NEXT: global_store_byte v1, v0, s[0:1]1574; GFX10-GISEL-NEXT: s_endpgm1575;1576; GFX11-LABEL: v_ctlz_i8_sel_eq_neg1:1577; GFX11: ; %bb.0:1578; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241579; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v01580; GFX11-NEXT: s_waitcnt lgkmcnt(0)1581; GFX11-NEXT: global_load_u8 v0, v0, s[2:3]1582; GFX11-NEXT: s_waitcnt vmcnt(0)1583; GFX11-NEXT: v_clz_i32_u32_e32 v0, v01584; GFX11-NEXT: global_store_b8 v1, v0, s[0:1]1585; GFX11-NEXT: s_endpgm1586 %tid = call i32 @llvm.amdgcn.workitem.id.x()1587 %valptr.gep = getelementptr i8, ptr addrspace(1) %valptr, i32 %tid1588 %val = load i8, ptr addrspace(1) %valptr.gep1589 %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 false) nounwind readnone1590 %cmp = icmp eq i8 %val, 01591 %sel = select i1 %cmp, i8 -1, i8 %ctlz1592 store i8 %sel, ptr addrspace(1) %out1593 ret void1594}1595 1596 define amdgpu_kernel void @v_ctlz_i16_sel_eq_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {1597; SI-LABEL: v_ctlz_i16_sel_eq_neg1:1598; SI: ; %bb.0:1599; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91600; SI-NEXT: s_mov_b32 s7, 0xf0001601; SI-NEXT: s_mov_b32 s6, -11602; SI-NEXT: s_mov_b32 s10, s61603; SI-NEXT: s_mov_b32 s11, s71604; SI-NEXT: s_waitcnt lgkmcnt(0)1605; SI-NEXT: s_mov_b32 s8, s21606; SI-NEXT: s_mov_b32 s9, s31607; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 01608; SI-NEXT: s_mov_b32 s4, s01609; SI-NEXT: s_mov_b32 s5, s11610; SI-NEXT: s_waitcnt vmcnt(0)1611; SI-NEXT: v_ffbh_u32_e32 v0, v01612; SI-NEXT: buffer_store_short v0, off, s[4:7], 01613; SI-NEXT: s_endpgm1614;1615; VI-LABEL: v_ctlz_i16_sel_eq_neg1:1616; VI: ; %bb.0:1617; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241618; VI-NEXT: s_mov_b32 s7, 0xf0001619; VI-NEXT: s_mov_b32 s6, -11620; VI-NEXT: s_mov_b32 s10, s61621; VI-NEXT: s_mov_b32 s11, s71622; VI-NEXT: s_waitcnt lgkmcnt(0)1623; VI-NEXT: s_mov_b32 s8, s21624; VI-NEXT: s_mov_b32 s9, s31625; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 01626; VI-NEXT: s_mov_b32 s4, s01627; VI-NEXT: s_mov_b32 s5, s11628; VI-NEXT: s_waitcnt vmcnt(0)1629; VI-NEXT: v_ffbh_u32_e32 v0, v01630; VI-NEXT: buffer_store_short v0, off, s[4:7], 01631; VI-NEXT: s_endpgm1632;1633; EG-LABEL: v_ctlz_i16_sel_eq_neg1:1634; EG: ; %bb.0:1635; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]1636; EG-NEXT: TEX 0 @61637; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[]1638; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1639; EG-NEXT: CF_END1640; EG-NEXT: PAD1641; EG-NEXT: Fetch clause starting at 6:1642; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #11643; EG-NEXT: ALU clause starting at 8:1644; EG-NEXT: MOV * T0.X, KC0[2].Z,1645; EG-NEXT: ALU clause starting at 9:1646; EG-NEXT: FFBH_UINT T0.W, T0.X,1647; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,1648; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1649; EG-NEXT: AND_INT T0.W, PV.W, literal.x,1650; EG-NEXT: LSHL * T1.W, PS, literal.y,1651; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)1652; EG-NEXT: LSHL T0.X, PV.W, PS,1653; EG-NEXT: LSHL * T0.W, literal.x, PS,1654; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1655; EG-NEXT: MOV T0.Y, 0.0,1656; EG-NEXT: MOV * T0.Z, 0.0,1657; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1658; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1659;1660; GFX10-LABEL: v_ctlz_i16_sel_eq_neg1:1661; GFX10: ; %bb.0:1662; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241663; GFX10-NEXT: v_mov_b32_e32 v0, 01664; GFX10-NEXT: s_waitcnt lgkmcnt(0)1665; GFX10-NEXT: global_load_ushort v1, v0, s[2:3]1666; GFX10-NEXT: s_waitcnt vmcnt(0)1667; GFX10-NEXT: v_ffbh_u32_e32 v1, v11668; GFX10-NEXT: global_store_short v0, v1, s[0:1]1669; GFX10-NEXT: s_endpgm1670;1671; GFX10-GISEL-LABEL: v_ctlz_i16_sel_eq_neg1:1672; GFX10-GISEL: ; %bb.0:1673; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241674; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, 01675; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)1676; GFX10-GISEL-NEXT: global_load_ushort v1, v0, s[2:3]1677; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)1678; GFX10-GISEL-NEXT: v_ffbh_u32_sdwa v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_01679; GFX10-GISEL-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11680; GFX10-GISEL-NEXT: v_min_u32_e32 v2, 32, v21681; GFX10-GISEL-NEXT: v_add_nc_u16 v2, v2, -161682; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v2, 0xffff, vcc_lo1683; GFX10-GISEL-NEXT: global_store_short v0, v1, s[0:1]1684; GFX10-GISEL-NEXT: s_endpgm1685;1686; GFX11-LABEL: v_ctlz_i16_sel_eq_neg1:1687; GFX11: ; %bb.0:1688; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241689; GFX11-NEXT: v_mov_b32_e32 v0, 01690; GFX11-NEXT: s_waitcnt lgkmcnt(0)1691; GFX11-NEXT: global_load_u16 v1, v0, s[2:3]1692; GFX11-NEXT: s_waitcnt vmcnt(0)1693; GFX11-NEXT: v_clz_i32_u32_e32 v1, v11694; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]1695; GFX11-NEXT: s_endpgm1696 %val = load i16, ptr addrspace(1) %valptr1697 %ctlz = call i16 @llvm.ctlz.i16(i16 %val, i1 false) nounwind readnone1698 %cmp = icmp eq i16 %val, 01699 %sel = select i1 %cmp, i16 -1, i16 %ctlz1700 store i16 %sel, ptr addrspace(1) %out1701 ret void1702}1703 1704; FIXME: Need to handle non-uniform case for function below (load without gep).1705define amdgpu_kernel void @v_ctlz_i7_sel_eq_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {1706; SI-LABEL: v_ctlz_i7_sel_eq_neg1:1707; SI: ; %bb.0:1708; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91709; SI-NEXT: s_mov_b32 s7, 0xf0001710; SI-NEXT: v_mov_b32_e32 v1, 01711; SI-NEXT: s_mov_b32 s10, 01712; SI-NEXT: s_mov_b32 s11, s71713; SI-NEXT: s_waitcnt lgkmcnt(0)1714; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1715; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[8:11], 0 addr641716; SI-NEXT: s_mov_b32 s6, -11717; SI-NEXT: s_mov_b32 s4, s01718; SI-NEXT: s_mov_b32 s5, s11719; SI-NEXT: s_waitcnt vmcnt(0)1720; SI-NEXT: v_ffbh_u32_e32 v0, v01721; SI-NEXT: v_and_b32_e32 v0, 0x7f, v01722; SI-NEXT: buffer_store_byte v0, off, s[4:7], 01723; SI-NEXT: s_endpgm1724;1725; VI-LABEL: v_ctlz_i7_sel_eq_neg1:1726; VI: ; %bb.0:1727; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241728; VI-NEXT: s_waitcnt lgkmcnt(0)1729; VI-NEXT: v_mov_b32_e32 v1, s31730; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01731; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1732; VI-NEXT: flat_load_ubyte v0, v[0:1]1733; VI-NEXT: s_mov_b32 s3, 0xf0001734; VI-NEXT: s_mov_b32 s2, -11735; VI-NEXT: s_waitcnt vmcnt(0)1736; VI-NEXT: v_ffbh_u32_e32 v0, v01737; VI-NEXT: v_and_b32_e32 v0, 0x7f, v01738; VI-NEXT: buffer_store_byte v0, off, s[0:3], 01739; VI-NEXT: s_endpgm1740;1741; EG-LABEL: v_ctlz_i7_sel_eq_neg1:1742; EG: ; %bb.0:1743; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]1744; EG-NEXT: TEX 0 @61745; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[]1746; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1747; EG-NEXT: CF_END1748; EG-NEXT: PAD1749; EG-NEXT: Fetch clause starting at 6:1750; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #11751; EG-NEXT: ALU clause starting at 8:1752; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, T0.X,1753; EG-NEXT: ALU clause starting at 9:1754; EG-NEXT: FFBH_UINT T0.W, T0.X,1755; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,1756; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1757; EG-NEXT: AND_INT T0.W, PV.W, literal.x,1758; EG-NEXT: LSHL * T1.W, PS, literal.y,1759; EG-NEXT: 127(1.779649e-43), 3(4.203895e-45)1760; EG-NEXT: LSHL T0.X, PV.W, PS,1761; EG-NEXT: LSHL * T0.W, literal.x, PS,1762; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)1763; EG-NEXT: MOV T0.Y, 0.0,1764; EG-NEXT: MOV * T0.Z, 0.0,1765; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1766; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1767;1768; GFX10-LABEL: v_ctlz_i7_sel_eq_neg1:1769; GFX10: ; %bb.0:1770; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241771; GFX10-NEXT: v_mov_b32_e32 v1, 01772; GFX10-NEXT: s_waitcnt lgkmcnt(0)1773; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3]1774; GFX10-NEXT: s_waitcnt vmcnt(0)1775; GFX10-NEXT: v_ffbh_u32_e32 v0, v01776; GFX10-NEXT: v_and_b32_e32 v0, 0x7f, v01777; GFX10-NEXT: global_store_byte v1, v0, s[0:1]1778; GFX10-NEXT: s_endpgm1779;1780; GFX10-GISEL-LABEL: v_ctlz_i7_sel_eq_neg1:1781; GFX10-GISEL: ; %bb.0:1782; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241783; GFX10-GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v01784; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)1785; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s21786; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s31787; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v1, v01788; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v2, v3, vcc_lo1789; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off1790; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)1791; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0x7f, v01792; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v1, v01793; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v01794; GFX10-GISEL-NEXT: v_min_u32_e32 v1, 32, v11795; GFX10-GISEL-NEXT: v_add_nc_u16 v1, 0xffe7, v11796; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0x7f, vcc_lo1797; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 01798; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0x7f, v01799; GFX10-GISEL-NEXT: global_store_byte v1, v0, s[0:1]1800; GFX10-GISEL-NEXT: s_endpgm1801;1802; GFX11-TRUE16-LABEL: v_ctlz_i7_sel_eq_neg1:1803; GFX11-TRUE16: ; %bb.0:1804; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x241805; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v01806; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)1807; GFX11-TRUE16-NEXT: global_load_u8 v0, v0, s[2:3]1808; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)1809; GFX11-TRUE16-NEXT: v_clz_i32_u32_e32 v0, v01810; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1811; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0x7f, v0.l1812; GFX11-TRUE16-NEXT: global_store_b8 v1, v0, s[0:1]1813; GFX11-TRUE16-NEXT: s_endpgm1814;1815; GFX11-FAKE16-LABEL: v_ctlz_i7_sel_eq_neg1:1816; GFX11-FAKE16: ; %bb.0:1817; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x241818; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v01819; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)1820; GFX11-FAKE16-NEXT: global_load_u8 v0, v0, s[2:3]1821; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)1822; GFX11-FAKE16-NEXT: v_clz_i32_u32_e32 v0, v01823; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1824; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0x7f, v01825; GFX11-FAKE16-NEXT: global_store_b8 v1, v0, s[0:1]1826; GFX11-FAKE16-NEXT: s_endpgm1827 %tid = call i32 @llvm.amdgcn.workitem.id.x()1828 %valptr.gep = getelementptr i7, ptr addrspace(1) %valptr, i32 %tid1829 %val = load i7, ptr addrspace(1) %valptr.gep1830 %ctlz = call i7 @llvm.ctlz.i7(i7 %val, i1 false) nounwind readnone1831 %cmp = icmp eq i7 %val, 01832 %sel = select i1 %cmp, i7 -1, i7 %ctlz1833 store i7 %sel, ptr addrspace(1) %out1834 ret void1835}1836