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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefixes=SI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s4; RUN: llc -mtriple=r600 -mcpu=cypress < %s | FileCheck -check-prefixes=EG %s5; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9-GISEL %s6 7declare i7 @llvm.ctlz.i7(i7, i1) nounwind readnone8declare <2 x i7> @llvm.ctlz.v2i7(<2 x i7>, i1) nounwind readnone9declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone10declare <2 x i8> @llvm.ctlz.v2i8(<2 x i8>, i1) nounwind readnone11 12declare i16 @llvm.ctlz.i16(i16, i1) nounwind readnone13declare i18 @llvm.ctlz.i18(i18, i1) nounwind readnone14 15declare <2 x i16> @llvm.ctlz.v2i16(<2 x i16>, i1) nounwind readnone16declare <3 x i16> @llvm.ctlz.v3i16(<3 x i16>, i1) nounwind readnone17declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>, i1) nounwind readnone18 19declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone20declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone21declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone22 23declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone24declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone25declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1) nounwind readnone26 27declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone28 29define amdgpu_kernel void @s_ctlz_zero_undef_i32(ptr addrspace(1) noalias %out, i32 %val) nounwind {30; SI-LABEL: s_ctlz_zero_undef_i32:31; SI: ; %bb.0:32; SI-NEXT: s_load_dword s2, s[4:5], 0xb33; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x934; SI-NEXT: s_mov_b32 s3, 0xf00035; SI-NEXT: s_waitcnt lgkmcnt(0)36; SI-NEXT: s_flbit_i32_b32 s4, s237; SI-NEXT: s_mov_b32 s2, -138; SI-NEXT: v_mov_b32_e32 v0, s439; SI-NEXT: buffer_store_dword v0, off, s[0:3], 040; SI-NEXT: s_endpgm41;42; VI-LABEL: s_ctlz_zero_undef_i32:43; VI: ; %bb.0:44; VI-NEXT: s_load_dword s2, s[4:5], 0x2c45; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2446; VI-NEXT: s_waitcnt lgkmcnt(0)47; VI-NEXT: s_flbit_i32_b32 s2, s248; VI-NEXT: v_mov_b32_e32 v0, s049; VI-NEXT: v_mov_b32_e32 v1, s150; VI-NEXT: v_mov_b32_e32 v2, s251; VI-NEXT: flat_store_dword v[0:1], v252; VI-NEXT: s_endpgm53;54; EG-LABEL: s_ctlz_zero_undef_i32:55; EG: ; %bb.0:56; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]57; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 158; EG-NEXT: CF_END59; EG-NEXT: PAD60; EG-NEXT: ALU clause starting at 4:61; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,62; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)63; EG-NEXT: FFBH_UINT * T1.X, KC0[2].Z,64;65; GFX9-GISEL-LABEL: s_ctlz_zero_undef_i32:66; GFX9-GISEL: ; %bb.0:67; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c68; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2469; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 070; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)71; GFX9-GISEL-NEXT: s_flbit_i32_b32 s2, s272; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s273; GFX9-GISEL-NEXT: global_store_dword v1, v0, s[0:1]74; GFX9-GISEL-NEXT: s_endpgm75 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone76 store i32 %ctlz, ptr addrspace(1) %out, align 477 ret void78}79 80define amdgpu_kernel void @v_ctlz_zero_undef_i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {81; SI-LABEL: v_ctlz_zero_undef_i32:82; SI: ; %bb.0:83; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x984; SI-NEXT: s_mov_b32 s7, 0xf00085; SI-NEXT: s_mov_b32 s10, 086; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v087; SI-NEXT: v_mov_b32_e32 v1, 088; SI-NEXT: s_mov_b32 s11, s789; SI-NEXT: s_waitcnt lgkmcnt(0)90; SI-NEXT: s_mov_b64 s[8:9], s[2:3]91; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr6492; SI-NEXT: s_mov_b32 s6, -193; SI-NEXT: s_mov_b32 s4, s094; SI-NEXT: s_mov_b32 s5, s195; SI-NEXT: s_waitcnt vmcnt(0)96; SI-NEXT: v_ffbh_u32_e32 v0, v097; SI-NEXT: buffer_store_dword v0, off, s[4:7], 098; SI-NEXT: s_endpgm99;100; VI-LABEL: v_ctlz_zero_undef_i32:101; VI: ; %bb.0:102; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24103; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0104; VI-NEXT: s_waitcnt lgkmcnt(0)105; VI-NEXT: v_mov_b32_e32 v1, s3106; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0107; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc108; VI-NEXT: flat_load_dword v0, v[0:1]109; VI-NEXT: s_waitcnt vmcnt(0)110; VI-NEXT: v_ffbh_u32_e32 v2, v0111; VI-NEXT: v_mov_b32_e32 v0, s0112; VI-NEXT: v_mov_b32_e32 v1, s1113; VI-NEXT: flat_store_dword v[0:1], v2114; VI-NEXT: s_endpgm115;116; EG-LABEL: v_ctlz_zero_undef_i32:117; EG: ; %bb.0:118; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]119; EG-NEXT: TEX 0 @6120; EG-NEXT: ALU 2, @11, KC0[CB0:0-32], KC1[]121; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1122; EG-NEXT: CF_END123; EG-NEXT: PAD124; EG-NEXT: Fetch clause starting at 6:125; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1126; EG-NEXT: ALU clause starting at 8:127; EG-NEXT: LSHL * T0.W, T0.X, literal.x,128; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)129; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,130; EG-NEXT: ALU clause starting at 11:131; EG-NEXT: FFBH_UINT T0.X, T0.X,132; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,133; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)134;135; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i32:136; GFX9-GISEL: ; %bb.0:137; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24138; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0139; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0140; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)141; GFX9-GISEL-NEXT: global_load_dword v0, v0, s[2:3]142; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)143; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v0, v0144; GFX9-GISEL-NEXT: global_store_dword v1, v0, s[0:1]145; GFX9-GISEL-NEXT: s_endpgm146 %tid = call i32 @llvm.amdgcn.workitem.id.x()147 %in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid148 %val = load i32, ptr addrspace(1) %in.gep, align 4149 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone150 store i32 %ctlz, ptr addrspace(1) %out, align 4151 ret void152}153 154define amdgpu_kernel void @v_ctlz_zero_undef_v2i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {155; SI-LABEL: v_ctlz_zero_undef_v2i32:156; SI: ; %bb.0:157; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9158; SI-NEXT: s_mov_b32 s7, 0xf000159; SI-NEXT: s_mov_b32 s10, 0160; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0161; SI-NEXT: v_mov_b32_e32 v1, 0162; SI-NEXT: s_mov_b32 s11, s7163; SI-NEXT: s_waitcnt lgkmcnt(0)164; SI-NEXT: s_mov_b64 s[8:9], s[2:3]165; SI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[8:11], 0 addr64166; SI-NEXT: s_mov_b32 s6, -1167; SI-NEXT: s_mov_b32 s4, s0168; SI-NEXT: s_mov_b32 s5, s1169; SI-NEXT: s_waitcnt vmcnt(0)170; SI-NEXT: v_ffbh_u32_e32 v1, v1171; SI-NEXT: v_ffbh_u32_e32 v0, v0172; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0173; SI-NEXT: s_endpgm174;175; VI-LABEL: v_ctlz_zero_undef_v2i32:176; VI: ; %bb.0:177; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24178; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0179; VI-NEXT: s_waitcnt lgkmcnt(0)180; VI-NEXT: v_mov_b32_e32 v1, s3181; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0182; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc183; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]184; VI-NEXT: v_mov_b32_e32 v3, s1185; VI-NEXT: v_mov_b32_e32 v2, s0186; VI-NEXT: s_waitcnt vmcnt(0)187; VI-NEXT: v_ffbh_u32_e32 v1, v1188; VI-NEXT: v_ffbh_u32_e32 v0, v0189; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]190; VI-NEXT: s_endpgm191;192; EG-LABEL: v_ctlz_zero_undef_v2i32:193; EG: ; %bb.0:194; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]195; EG-NEXT: TEX 0 @6196; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[]197; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1198; EG-NEXT: CF_END199; EG-NEXT: PAD200; EG-NEXT: Fetch clause starting at 6:201; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1202; EG-NEXT: ALU clause starting at 8:203; EG-NEXT: LSHL * T0.W, T0.X, literal.x,204; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)205; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,206; EG-NEXT: ALU clause starting at 11:207; EG-NEXT: FFBH_UINT * T0.Y, T0.Y,208; EG-NEXT: FFBH_UINT T0.X, T0.X,209; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,210; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)211;212; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v2i32:213; GFX9-GISEL: ; %bb.0:214; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24215; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 3, v0216; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0217; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)218; GFX9-GISEL-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3]219; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)220; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v0, v0221; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v1, v1222; GFX9-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]223; GFX9-GISEL-NEXT: s_endpgm224 %tid = call i32 @llvm.amdgcn.workitem.id.x()225 %in.gep = getelementptr <2 x i32>, ptr addrspace(1) %valptr, i32 %tid226 %val = load <2 x i32>, ptr addrspace(1) %in.gep, align 8227 %ctlz = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %val, i1 true) nounwind readnone228 store <2 x i32> %ctlz, ptr addrspace(1) %out, align 8229 ret void230}231 232define amdgpu_kernel void @v_ctlz_zero_undef_v4i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {233; SI-LABEL: v_ctlz_zero_undef_v4i32:234; SI: ; %bb.0:235; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9236; SI-NEXT: s_mov_b32 s7, 0xf000237; SI-NEXT: s_mov_b32 s10, 0238; SI-NEXT: v_lshlrev_b32_e32 v0, 4, v0239; SI-NEXT: v_mov_b32_e32 v1, 0240; SI-NEXT: s_mov_b32 s11, s7241; SI-NEXT: s_waitcnt lgkmcnt(0)242; SI-NEXT: s_mov_b64 s[8:9], s[2:3]243; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64244; SI-NEXT: s_mov_b32 s6, -1245; SI-NEXT: s_mov_b32 s4, s0246; SI-NEXT: s_mov_b32 s5, s1247; SI-NEXT: s_waitcnt vmcnt(0)248; SI-NEXT: v_ffbh_u32_e32 v3, v3249; SI-NEXT: v_ffbh_u32_e32 v2, v2250; SI-NEXT: v_ffbh_u32_e32 v1, v1251; SI-NEXT: v_ffbh_u32_e32 v0, v0252; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0253; SI-NEXT: s_endpgm254;255; VI-LABEL: v_ctlz_zero_undef_v4i32:256; VI: ; %bb.0:257; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24258; VI-NEXT: v_lshlrev_b32_e32 v0, 4, v0259; VI-NEXT: s_waitcnt lgkmcnt(0)260; VI-NEXT: v_mov_b32_e32 v1, s3261; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0262; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc263; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]264; VI-NEXT: v_mov_b32_e32 v5, s1265; VI-NEXT: v_mov_b32_e32 v4, s0266; VI-NEXT: s_waitcnt vmcnt(0)267; VI-NEXT: v_ffbh_u32_e32 v3, v3268; VI-NEXT: v_ffbh_u32_e32 v2, v2269; VI-NEXT: v_ffbh_u32_e32 v1, v1270; VI-NEXT: v_ffbh_u32_e32 v0, v0271; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]272; VI-NEXT: s_endpgm273;274; EG-LABEL: v_ctlz_zero_undef_v4i32:275; EG: ; %bb.0:276; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]277; EG-NEXT: TEX 0 @6278; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]279; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1280; EG-NEXT: CF_END281; EG-NEXT: PAD282; EG-NEXT: Fetch clause starting at 6:283; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1284; EG-NEXT: ALU clause starting at 8:285; EG-NEXT: LSHL * T0.W, T0.X, literal.x,286; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)287; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,288; EG-NEXT: ALU clause starting at 11:289; EG-NEXT: FFBH_UINT * T0.W, T0.W,290; EG-NEXT: FFBH_UINT * T0.Z, T0.Z,291; EG-NEXT: FFBH_UINT * T0.Y, T0.Y,292; EG-NEXT: FFBH_UINT T0.X, T0.X,293; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,294; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)295;296; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v4i32:297; GFX9-GISEL: ; %bb.0:298; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24299; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 4, v0300; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0301; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)302; GFX9-GISEL-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3]303; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)304; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v0, v0305; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v1, v1306; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v2, v2307; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v3, v3308; GFX9-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]309; GFX9-GISEL-NEXT: s_endpgm310 %tid = call i32 @llvm.amdgcn.workitem.id.x()311 %in.gep = getelementptr <4 x i32>, ptr addrspace(1) %valptr, i32 %tid312 %val = load <4 x i32>, ptr addrspace(1) %in.gep, align 16313 %ctlz = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %val, i1 true) nounwind readnone314 store <4 x i32> %ctlz, ptr addrspace(1) %out, align 16315 ret void316}317 318define amdgpu_kernel void @s_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noalias %out, i8 %val) nounwind {319; SI-LABEL: s_ctlz_zero_undef_i8_with_select:320; SI: ; %bb.0:321; SI-NEXT: s_load_dword s2, s[4:5], 0xb322; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9323; SI-NEXT: s_mov_b32 s3, 0xf000324; SI-NEXT: s_waitcnt lgkmcnt(0)325; SI-NEXT: s_lshl_b32 s2, s2, 24326; SI-NEXT: s_flbit_i32_b32 s4, s2327; SI-NEXT: s_mov_b32 s2, -1328; SI-NEXT: v_mov_b32_e32 v0, s4329; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0330; SI-NEXT: s_endpgm331;332; VI-LABEL: s_ctlz_zero_undef_i8_with_select:333; VI: ; %bb.0:334; VI-NEXT: s_load_dword s2, s[4:5], 0x2c335; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24336; VI-NEXT: s_waitcnt lgkmcnt(0)337; VI-NEXT: s_lshl_b32 s2, s2, 24338; VI-NEXT: s_flbit_i32_b32 s2, s2339; VI-NEXT: v_mov_b32_e32 v0, s0340; VI-NEXT: v_mov_b32_e32 v1, s1341; VI-NEXT: v_mov_b32_e32 v2, s2342; VI-NEXT: flat_store_byte v[0:1], v2343; VI-NEXT: s_endpgm344;345; EG-LABEL: s_ctlz_zero_undef_i8_with_select:346; EG: ; %bb.0:347; EG-NEXT: ALU 0, @8, KC0[], KC1[]348; EG-NEXT: TEX 0 @6349; EG-NEXT: ALU 14, @9, KC0[CB0:0-32], KC1[]350; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X351; EG-NEXT: CF_END352; EG-NEXT: PAD353; EG-NEXT: Fetch clause starting at 6:354; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3355; EG-NEXT: ALU clause starting at 8:356; EG-NEXT: MOV * T0.X, 0.0,357; EG-NEXT: ALU clause starting at 9:358; EG-NEXT: LSHL * T0.W, T0.X, literal.x,359; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)360; EG-NEXT: FFBH_UINT T0.W, PV.W,361; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,362; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)363; EG-NEXT: AND_INT T0.W, PV.W, literal.x,364; EG-NEXT: LSHL * T1.W, PS, literal.y,365; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)366; EG-NEXT: LSHL T0.X, PV.W, PS,367; EG-NEXT: LSHL * T0.W, literal.x, PS,368; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)369; EG-NEXT: MOV T0.Y, 0.0,370; EG-NEXT: MOV * T0.Z, 0.0,371; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,372; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)373;374; GFX9-GISEL-LABEL: s_ctlz_zero_undef_i8_with_select:375; GFX9-GISEL: ; %bb.0:376; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c377; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24378; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0379; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)380; GFX9-GISEL-NEXT: s_lshl_b32 s2, s2, 24381; GFX9-GISEL-NEXT: s_flbit_i32_b32 s2, s2382; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2383; GFX9-GISEL-NEXT: global_store_byte v1, v0, s[0:1]384; GFX9-GISEL-NEXT: s_endpgm385 %ctlz = tail call i8 @llvm.ctlz.i8(i8 %val, i1 true) nounwind readnone386 %ctlz_ret = icmp ne i8 %val, 0387 %ret = select i1 %ctlz_ret, i8 %ctlz, i8 32388 store i8 %ctlz, ptr addrspace(1) %out, align 4389 ret void390}391 392define amdgpu_kernel void @s_ctlz_zero_undef_i16_with_select(ptr addrspace(1) noalias %out, i16 %val) nounwind {393; SI-LABEL: s_ctlz_zero_undef_i16_with_select:394; SI: ; %bb.0:395; SI-NEXT: s_load_dword s2, s[4:5], 0xb396; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9397; SI-NEXT: s_mov_b32 s3, 0xf000398; SI-NEXT: s_waitcnt lgkmcnt(0)399; SI-NEXT: s_lshl_b32 s2, s2, 16400; SI-NEXT: s_flbit_i32_b32 s4, s2401; SI-NEXT: s_mov_b32 s2, -1402; SI-NEXT: v_mov_b32_e32 v0, s4403; SI-NEXT: buffer_store_short v0, off, s[0:3], 0404; SI-NEXT: s_endpgm405;406; VI-LABEL: s_ctlz_zero_undef_i16_with_select:407; VI: ; %bb.0:408; VI-NEXT: s_load_dword s2, s[4:5], 0x2c409; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24410; VI-NEXT: s_waitcnt lgkmcnt(0)411; VI-NEXT: s_lshl_b32 s2, s2, 16412; VI-NEXT: s_flbit_i32_b32 s2, s2413; VI-NEXT: v_mov_b32_e32 v0, s0414; VI-NEXT: v_mov_b32_e32 v1, s1415; VI-NEXT: v_mov_b32_e32 v2, s2416; VI-NEXT: flat_store_short v[0:1], v2417; VI-NEXT: s_endpgm418;419; EG-LABEL: s_ctlz_zero_undef_i16_with_select:420; EG: ; %bb.0:421; EG-NEXT: ALU 0, @8, KC0[], KC1[]422; EG-NEXT: TEX 0 @6423; EG-NEXT: ALU 14, @9, KC0[CB0:0-32], KC1[]424; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X425; EG-NEXT: CF_END426; EG-NEXT: PAD427; EG-NEXT: Fetch clause starting at 6:428; EG-NEXT: VTX_READ_16 T0.X, T0.X, 40, #3429; EG-NEXT: ALU clause starting at 8:430; EG-NEXT: MOV * T0.X, 0.0,431; EG-NEXT: ALU clause starting at 9:432; EG-NEXT: LSHL * T0.W, T0.X, literal.x,433; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)434; EG-NEXT: FFBH_UINT T0.W, PV.W,435; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,436; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)437; EG-NEXT: AND_INT T0.W, PV.W, literal.x,438; EG-NEXT: LSHL * T1.W, PS, literal.y,439; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)440; EG-NEXT: LSHL T0.X, PV.W, PS,441; EG-NEXT: LSHL * T0.W, literal.x, PS,442; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)443; EG-NEXT: MOV T0.Y, 0.0,444; EG-NEXT: MOV * T0.Z, 0.0,445; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,446; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)447;448; GFX9-GISEL-LABEL: s_ctlz_zero_undef_i16_with_select:449; GFX9-GISEL: ; %bb.0:450; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c451; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24452; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0453; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)454; GFX9-GISEL-NEXT: s_lshl_b32 s2, s2, 16455; GFX9-GISEL-NEXT: s_flbit_i32_b32 s2, s2456; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2457; GFX9-GISEL-NEXT: global_store_short v1, v0, s[0:1]458; GFX9-GISEL-NEXT: s_endpgm459 %ctlz = tail call i16 @llvm.ctlz.i16(i16 %val, i1 true) nounwind readnone460 %ctlz_ret = icmp ne i16 %val, 0461 %ret = select i1 %ctlz_ret, i16 %ctlz, i16 32462 store i16 %ctlz, ptr addrspace(1) %out, align 4463 ret void464}465 466define amdgpu_kernel void @s_ctlz_zero_undef_i32_with_select(ptr addrspace(1) noalias %out, i32 %val) nounwind {467; SI-LABEL: s_ctlz_zero_undef_i32_with_select:468; SI: ; %bb.0:469; SI-NEXT: s_load_dword s2, s[4:5], 0xb470; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9471; SI-NEXT: s_mov_b32 s3, 0xf000472; SI-NEXT: s_waitcnt lgkmcnt(0)473; SI-NEXT: s_flbit_i32_b32 s4, s2474; SI-NEXT: s_mov_b32 s2, -1475; SI-NEXT: v_mov_b32_e32 v0, s4476; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0477; SI-NEXT: s_endpgm478;479; VI-LABEL: s_ctlz_zero_undef_i32_with_select:480; VI: ; %bb.0:481; VI-NEXT: s_load_dword s2, s[4:5], 0x2c482; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24483; VI-NEXT: s_waitcnt lgkmcnt(0)484; VI-NEXT: s_flbit_i32_b32 s2, s2485; VI-NEXT: v_mov_b32_e32 v0, s0486; VI-NEXT: v_mov_b32_e32 v1, s1487; VI-NEXT: v_mov_b32_e32 v2, s2488; VI-NEXT: flat_store_dword v[0:1], v2489; VI-NEXT: s_endpgm490;491; EG-LABEL: s_ctlz_zero_undef_i32_with_select:492; EG: ; %bb.0:493; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]494; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1495; EG-NEXT: CF_END496; EG-NEXT: PAD497; EG-NEXT: ALU clause starting at 4:498; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,499; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)500; EG-NEXT: FFBH_UINT * T1.X, KC0[2].Z,501;502; GFX9-GISEL-LABEL: s_ctlz_zero_undef_i32_with_select:503; GFX9-GISEL: ; %bb.0:504; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c505; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24506; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0507; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)508; GFX9-GISEL-NEXT: s_flbit_i32_b32 s2, s2509; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2510; GFX9-GISEL-NEXT: global_store_dword v1, v0, s[0:1]511; GFX9-GISEL-NEXT: s_endpgm512 %ctlz = tail call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone513 %ctlz_ret = icmp ne i32 %val, 0514 %ret = select i1 %ctlz_ret, i32 %ctlz, i32 32515 store i32 %ctlz, ptr addrspace(1) %out, align 4516 ret void517}518 519define amdgpu_kernel void @s_ctlz_zero_undef_i64_with_select(ptr addrspace(1) noalias %out, i64 %val) nounwind {520; SI-LABEL: s_ctlz_zero_undef_i64_with_select:521; SI: ; %bb.0:522; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9523; SI-NEXT: s_mov_b32 s7, 0xf000524; SI-NEXT: s_mov_b32 s6, -1525; SI-NEXT: s_waitcnt lgkmcnt(0)526; SI-NEXT: s_flbit_i32_b64 s2, s[2:3]527; SI-NEXT: v_mov_b32_e32 v1, 0528; SI-NEXT: s_mov_b32 s4, s0529; SI-NEXT: s_mov_b32 s5, s1530; SI-NEXT: v_mov_b32_e32 v0, s2531; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0532; SI-NEXT: s_endpgm533;534; VI-LABEL: s_ctlz_zero_undef_i64_with_select:535; VI: ; %bb.0:536; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24537; VI-NEXT: v_mov_b32_e32 v1, 0538; VI-NEXT: s_waitcnt lgkmcnt(0)539; VI-NEXT: s_flbit_i32_b64 s2, s[2:3]540; VI-NEXT: v_mov_b32_e32 v3, s1541; VI-NEXT: v_mov_b32_e32 v0, s2542; VI-NEXT: v_mov_b32_e32 v2, s0543; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]544; VI-NEXT: s_endpgm545;546; EG-LABEL: s_ctlz_zero_undef_i64_with_select:547; EG: ; %bb.0:548; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]549; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1550; EG-NEXT: CF_END551; EG-NEXT: PAD552; EG-NEXT: ALU clause starting at 4:553; EG-NEXT: FFBH_UINT * T0.W, KC0[2].W,554; EG-NEXT: FFBH_UINT T1.W, KC0[3].X,555; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,556; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)557; EG-NEXT: CNDE_INT T0.X, KC0[3].X, PS, PV.W,558; EG-NEXT: MOV T0.Y, 0.0,559; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,560; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)561;562; GFX9-GISEL-LABEL: s_ctlz_zero_undef_i64_with_select:563; GFX9-GISEL: ; %bb.0:564; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24565; GFX9-GISEL-NEXT: s_mov_b32 s5, 0566; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0567; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)568; GFX9-GISEL-NEXT: s_flbit_i32_b64 s4, s[2:3]569; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s4570; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s5571; GFX9-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]572; GFX9-GISEL-NEXT: s_endpgm573 %ctlz = tail call i64 @llvm.ctlz.i64(i64 %val, i1 true) nounwind readnone574 %ctlz_ret = icmp ne i64 %val, 0575 %ret = select i1 %ctlz_ret, i64 %ctlz, i64 32576 store i64 %ctlz, ptr addrspace(1) %out, align 4577 ret void578}579 580define amdgpu_kernel void @v_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {581; SI-LABEL: v_ctlz_zero_undef_i8_with_select:582; SI: ; %bb.0:583; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9584; SI-NEXT: s_mov_b32 s7, 0xf000585; SI-NEXT: s_mov_b32 s6, -1586; SI-NEXT: s_mov_b32 s10, s6587; SI-NEXT: s_mov_b32 s11, s7588; SI-NEXT: s_waitcnt lgkmcnt(0)589; SI-NEXT: s_mov_b32 s8, s2590; SI-NEXT: s_mov_b32 s9, s3591; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0592; SI-NEXT: s_mov_b32 s4, s0593; SI-NEXT: s_mov_b32 s5, s1594; SI-NEXT: s_waitcnt vmcnt(0)595; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v0596; SI-NEXT: v_ffbh_u32_e32 v1, v1597; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0598; SI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc599; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0600; SI-NEXT: s_endpgm601;602; VI-LABEL: v_ctlz_zero_undef_i8_with_select:603; VI: ; %bb.0:604; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24605; VI-NEXT: s_waitcnt lgkmcnt(0)606; VI-NEXT: v_mov_b32_e32 v0, s2607; VI-NEXT: v_mov_b32_e32 v1, s3608; VI-NEXT: flat_load_ubyte v0, v[0:1]609; VI-NEXT: s_waitcnt vmcnt(0)610; VI-NEXT: v_lshlrev_b32_e32 v1, 24, v0611; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0612; VI-NEXT: v_ffbh_u32_e32 v1, v1613; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0614; VI-NEXT: v_cndmask_b32_e32 v2, 32, v1, vcc615; VI-NEXT: v_mov_b32_e32 v0, s0616; VI-NEXT: v_mov_b32_e32 v1, s1617; VI-NEXT: flat_store_byte v[0:1], v2618; VI-NEXT: s_endpgm619;620; EG-LABEL: v_ctlz_zero_undef_i8_with_select:621; EG: ; %bb.0:622; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]623; EG-NEXT: TEX 0 @6624; EG-NEXT: ALU 16, @9, KC0[CB0:0-32], KC1[]625; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X626; EG-NEXT: CF_END627; EG-NEXT: PAD628; EG-NEXT: Fetch clause starting at 6:629; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1630; EG-NEXT: ALU clause starting at 8:631; EG-NEXT: MOV * T0.X, KC0[2].Z,632; EG-NEXT: ALU clause starting at 9:633; EG-NEXT: LSHL * T0.W, T0.X, literal.x,634; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)635; EG-NEXT: FFBH_UINT T0.W, PV.W,636; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,637; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)638; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W,639; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)640; EG-NEXT: AND_INT T0.W, PV.W, literal.x,641; EG-NEXT: LSHL * T1.W, T1.W, literal.y,642; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)643; EG-NEXT: LSHL T0.X, PV.W, PS,644; EG-NEXT: LSHL * T0.W, literal.x, PS,645; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)646; EG-NEXT: MOV T0.Y, 0.0,647; EG-NEXT: MOV * T0.Z, 0.0,648; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,649; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)650;651; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i8_with_select:652; GFX9-GISEL: ; %bb.0:653; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24654; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0655; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)656; GFX9-GISEL-NEXT: global_load_ubyte v1, v0, s[2:3]657; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)658; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v1659; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v2, v2660; GFX9-GISEL-NEXT: v_cmp_ne_u32_sdwa vcc, v1, v0 src0_sel:BYTE_0 src1_sel:DWORD661; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, 32, v2, vcc662; GFX9-GISEL-NEXT: global_store_byte v0, v1, s[0:1]663; GFX9-GISEL-NEXT: s_endpgm664 %val = load i8, ptr addrspace(1) %arrayidx, align 1665 %ctlz = tail call i8 @llvm.ctlz.i8(i8 %val, i1 true) nounwind readnone666 %ctlz_ret = icmp ne i8 %val, 0667 %ret = select i1 %ctlz_ret, i8 %ctlz, i8 32668 store i8 %ret, ptr addrspace(1) %out, align 4669 ret void670}671 672define amdgpu_kernel void @v_ctlz_zero_undef_i16_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {673; SI-LABEL: v_ctlz_zero_undef_i16_with_select:674; SI: ; %bb.0:675; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9676; SI-NEXT: s_mov_b32 s7, 0xf000677; SI-NEXT: s_mov_b32 s6, -1678; SI-NEXT: s_mov_b32 s10, s6679; SI-NEXT: s_mov_b32 s11, s7680; SI-NEXT: s_waitcnt lgkmcnt(0)681; SI-NEXT: s_mov_b32 s8, s2682; SI-NEXT: s_mov_b32 s9, s3683; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:1684; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0685; SI-NEXT: s_mov_b32 s4, s0686; SI-NEXT: s_mov_b32 s5, s1687; SI-NEXT: s_waitcnt vmcnt(1)688; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0689; SI-NEXT: s_waitcnt vmcnt(0)690; SI-NEXT: v_or_b32_e32 v0, v0, v1691; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v0692; SI-NEXT: v_ffbh_u32_e32 v1, v1693; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0694; SI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc695; SI-NEXT: buffer_store_short v0, off, s[4:7], 0696; SI-NEXT: s_endpgm697;698; VI-LABEL: v_ctlz_zero_undef_i16_with_select:699; VI: ; %bb.0:700; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24701; VI-NEXT: s_waitcnt lgkmcnt(0)702; VI-NEXT: s_add_u32 s4, s2, 1703; VI-NEXT: s_addc_u32 s5, s3, 0704; VI-NEXT: v_mov_b32_e32 v2, s4705; VI-NEXT: v_mov_b32_e32 v0, s2706; VI-NEXT: v_mov_b32_e32 v3, s5707; VI-NEXT: v_mov_b32_e32 v1, s3708; VI-NEXT: flat_load_ubyte v2, v[2:3]709; VI-NEXT: flat_load_ubyte v0, v[0:1]710; VI-NEXT: s_waitcnt vmcnt(1)711; VI-NEXT: v_readfirstlane_b32 s2, v2712; VI-NEXT: s_waitcnt vmcnt(0)713; VI-NEXT: v_readfirstlane_b32 s3, v0714; VI-NEXT: s_lshl_b32 s2, s2, 8715; VI-NEXT: s_or_b32 s2, s2, s3716; VI-NEXT: s_lshl_b32 s3, s2, 16717; VI-NEXT: s_flbit_i32_b32 s3, s3718; VI-NEXT: s_and_b32 s2, s2, 0xffff719; VI-NEXT: s_cselect_b32 s2, s3, 32720; VI-NEXT: v_mov_b32_e32 v0, s0721; VI-NEXT: v_mov_b32_e32 v1, s1722; VI-NEXT: v_mov_b32_e32 v2, s2723; VI-NEXT: flat_store_short v[0:1], v2724; VI-NEXT: s_endpgm725;726; EG-LABEL: v_ctlz_zero_undef_i16_with_select:727; EG: ; %bb.0:728; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]729; EG-NEXT: TEX 0 @6730; EG-NEXT: ALU 16, @9, KC0[CB0:0-32], KC1[]731; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X732; EG-NEXT: CF_END733; EG-NEXT: PAD734; EG-NEXT: Fetch clause starting at 6:735; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #1736; EG-NEXT: ALU clause starting at 8:737; EG-NEXT: MOV * T0.X, KC0[2].Z,738; EG-NEXT: ALU clause starting at 9:739; EG-NEXT: LSHL * T0.W, T0.X, literal.x,740; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)741; EG-NEXT: FFBH_UINT T0.W, PV.W,742; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,743; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)744; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W,745; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)746; EG-NEXT: AND_INT T0.W, PV.W, literal.x,747; EG-NEXT: LSHL * T1.W, T1.W, literal.y,748; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)749; EG-NEXT: LSHL T0.X, PV.W, PS,750; EG-NEXT: LSHL * T0.W, literal.x, PS,751; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)752; EG-NEXT: MOV T0.Y, 0.0,753; EG-NEXT: MOV * T0.Z, 0.0,754; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,755; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)756;757; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i16_with_select:758; GFX9-GISEL: ; %bb.0:759; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24760; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0761; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)762; GFX9-GISEL-NEXT: global_load_ubyte v1, v0, s[2:3]763; GFX9-GISEL-NEXT: global_load_ubyte v2, v0, s[2:3] offset:1764; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)765; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, v2, 8, v1766; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v2, 16, v1767; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v2, v2768; GFX9-GISEL-NEXT: v_cmp_ne_u16_e32 vcc, 0, v1769; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, 32, v2, vcc770; GFX9-GISEL-NEXT: global_store_short v0, v1, s[0:1]771; GFX9-GISEL-NEXT: s_endpgm772 %val = load i16, ptr addrspace(1) %arrayidx, align 1773 %ctlz = tail call i16 @llvm.ctlz.i16(i16 %val, i1 true) nounwind readnone774 %ctlz_ret = icmp ne i16 %val, 0775 %ret = select i1 %ctlz_ret, i16 %ctlz, i16 32776 store i16 %ret, ptr addrspace(1) %out, align 4777 ret void778}779 780define amdgpu_kernel void @v_ctlz_zero_undef_i32_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {781; SI-LABEL: v_ctlz_zero_undef_i32_with_select:782; SI: ; %bb.0:783; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9784; SI-NEXT: s_mov_b32 s7, 0xf000785; SI-NEXT: s_mov_b32 s6, -1786; SI-NEXT: s_mov_b32 s10, s6787; SI-NEXT: s_mov_b32 s11, s7788; SI-NEXT: s_waitcnt lgkmcnt(0)789; SI-NEXT: s_mov_b32 s8, s2790; SI-NEXT: s_mov_b32 s9, s3791; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:1792; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:3793; SI-NEXT: buffer_load_ubyte v2, off, s[8:11], 0794; SI-NEXT: buffer_load_ubyte v3, off, s[8:11], 0 offset:2795; SI-NEXT: s_mov_b32 s4, s0796; SI-NEXT: s_mov_b32 s5, s1797; SI-NEXT: s_waitcnt vmcnt(3)798; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0799; SI-NEXT: s_waitcnt vmcnt(2)800; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1801; SI-NEXT: s_waitcnt vmcnt(1)802; SI-NEXT: v_or_b32_e32 v0, v0, v2803; SI-NEXT: s_waitcnt vmcnt(0)804; SI-NEXT: v_or_b32_e32 v1, v1, v3805; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1806; SI-NEXT: v_or_b32_e32 v0, v1, v0807; SI-NEXT: v_ffbh_u32_e32 v0, v0808; SI-NEXT: v_min_u32_e32 v0, 32, v0809; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0810; SI-NEXT: s_endpgm811;812; VI-LABEL: v_ctlz_zero_undef_i32_with_select:813; VI: ; %bb.0:814; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24815; VI-NEXT: s_waitcnt lgkmcnt(0)816; VI-NEXT: s_add_u32 s4, s2, 3817; VI-NEXT: s_addc_u32 s5, s3, 0818; VI-NEXT: v_mov_b32_e32 v2, s4819; VI-NEXT: v_mov_b32_e32 v3, s5820; VI-NEXT: s_add_u32 s4, s2, 2821; VI-NEXT: v_mov_b32_e32 v0, s2822; VI-NEXT: s_addc_u32 s5, s3, 0823; VI-NEXT: v_mov_b32_e32 v1, s3824; VI-NEXT: s_add_u32 s2, s2, 1825; VI-NEXT: s_addc_u32 s3, s3, 0826; VI-NEXT: v_mov_b32_e32 v4, s4827; VI-NEXT: v_mov_b32_e32 v7, s3828; VI-NEXT: v_mov_b32_e32 v5, s5829; VI-NEXT: v_mov_b32_e32 v6, s2830; VI-NEXT: flat_load_ubyte v2, v[2:3]831; VI-NEXT: flat_load_ubyte v3, v[4:5]832; VI-NEXT: flat_load_ubyte v4, v[6:7]833; VI-NEXT: flat_load_ubyte v0, v[0:1]834; VI-NEXT: s_waitcnt vmcnt(3)835; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v2836; VI-NEXT: s_waitcnt vmcnt(2)837; VI-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD838; VI-NEXT: s_waitcnt vmcnt(1)839; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v4840; VI-NEXT: s_waitcnt vmcnt(0)841; VI-NEXT: v_or_b32_e32 v0, v2, v0842; VI-NEXT: v_or_b32_e32 v0, v1, v0843; VI-NEXT: v_ffbh_u32_e32 v0, v0844; VI-NEXT: v_min_u32_e32 v2, 32, v0845; VI-NEXT: v_mov_b32_e32 v0, s0846; VI-NEXT: v_mov_b32_e32 v1, s1847; VI-NEXT: flat_store_dword v[0:1], v2848; VI-NEXT: s_endpgm849;850; EG-LABEL: v_ctlz_zero_undef_i32_with_select:851; EG: ; %bb.0:852; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]853; EG-NEXT: TEX 1 @6854; EG-NEXT: ALU 6, @11, KC0[CB0:0-32], KC1[]855; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1856; EG-NEXT: CF_END857; EG-NEXT: PAD858; EG-NEXT: Fetch clause starting at 6:859; EG-NEXT: VTX_READ_16 T1.X, T0.X, 2, #1860; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #1861; EG-NEXT: ALU clause starting at 10:862; EG-NEXT: MOV * T0.X, KC0[2].Z,863; EG-NEXT: ALU clause starting at 11:864; EG-NEXT: LSHL * T0.W, T1.X, literal.x,865; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)866; EG-NEXT: OR_INT * T0.W, PV.W, T0.X,867; EG-NEXT: FFBH_UINT * T1.W, PV.W,868; EG-NEXT: CNDE_INT T0.X, T0.W, literal.x, PV.W,869; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,870; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45)871;872; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i32_with_select:873; GFX9-GISEL: ; %bb.0:874; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24875; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0876; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)877; GFX9-GISEL-NEXT: global_load_ubyte v1, v0, s[2:3]878; GFX9-GISEL-NEXT: global_load_ubyte v2, v0, s[2:3] offset:1879; GFX9-GISEL-NEXT: global_load_ubyte v3, v0, s[2:3] offset:3880; GFX9-GISEL-NEXT: global_load_ubyte v4, v0, s[2:3] offset:2881; GFX9-GISEL-NEXT: s_waitcnt vmcnt(2)882; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, v2, 8, v1883; GFX9-GISEL-NEXT: s_waitcnt vmcnt(1)884; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v3885; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)886; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v4887; GFX9-GISEL-NEXT: v_or3_b32 v1, v2, v3, v1888; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v2, v1889; GFX9-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1890; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, 32, v2, vcc891; GFX9-GISEL-NEXT: global_store_dword v0, v1, s[0:1]892; GFX9-GISEL-NEXT: s_endpgm893 %val = load i32, ptr addrspace(1) %arrayidx, align 1894 %ctlz = tail call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone895 %ctlz_ret = icmp ne i32 %val, 0896 %ret = select i1 %ctlz_ret, i32 %ctlz, i32 32897 store i32 %ret, ptr addrspace(1) %out, align 4898 ret void899}900 901define amdgpu_kernel void @v_ctlz_zero_undef_i64_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {902; SI-LABEL: v_ctlz_zero_undef_i64_with_select:903; SI: ; %bb.0:904; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9905; SI-NEXT: s_mov_b32 s3, 0xf000906; SI-NEXT: s_mov_b32 s2, -1907; SI-NEXT: s_mov_b32 s10, s2908; SI-NEXT: s_mov_b32 s11, s3909; SI-NEXT: s_waitcnt lgkmcnt(0)910; SI-NEXT: s_mov_b32 s8, s6911; SI-NEXT: s_mov_b32 s9, s7912; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0913; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:1914; SI-NEXT: buffer_load_ubyte v2, off, s[8:11], 0 offset:2915; SI-NEXT: buffer_load_ubyte v3, off, s[8:11], 0 offset:3916; SI-NEXT: buffer_load_ubyte v4, off, s[8:11], 0 offset:5917; SI-NEXT: buffer_load_ubyte v5, off, s[8:11], 0 offset:7918; SI-NEXT: buffer_load_ubyte v6, off, s[8:11], 0 offset:4919; SI-NEXT: buffer_load_ubyte v7, off, s[8:11], 0 offset:6920; SI-NEXT: s_mov_b32 s0, s4921; SI-NEXT: s_mov_b32 s1, s5922; SI-NEXT: s_waitcnt vmcnt(3)923; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4924; SI-NEXT: s_waitcnt vmcnt(2)925; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5926; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1927; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3928; SI-NEXT: s_waitcnt vmcnt(1)929; SI-NEXT: v_or_b32_e32 v4, v4, v6930; SI-NEXT: s_waitcnt vmcnt(0)931; SI-NEXT: v_or_b32_e32 v5, v5, v7932; SI-NEXT: v_or_b32_e32 v0, v1, v0933; SI-NEXT: v_or_b32_e32 v1, v3, v2934; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v5935; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1936; SI-NEXT: v_or_b32_e32 v2, v2, v4937; SI-NEXT: v_or_b32_e32 v0, v1, v0938; SI-NEXT: v_ffbh_u32_e32 v0, v0939; SI-NEXT: v_ffbh_u32_e32 v1, v2940; SI-NEXT: v_add_i32_e32 v0, vcc, 32, v0941; SI-NEXT: v_min_u32_e32 v0, v0, v1942; SI-NEXT: v_min_u32_e32 v0, 64, v0943; SI-NEXT: v_mov_b32_e32 v1, 0944; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0945; SI-NEXT: s_endpgm946;947; VI-LABEL: v_ctlz_zero_undef_i64_with_select:948; VI: ; %bb.0:949; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24950; VI-NEXT: s_waitcnt lgkmcnt(0)951; VI-NEXT: s_add_u32 s4, s2, 5952; VI-NEXT: s_addc_u32 s5, s3, 0953; VI-NEXT: v_mov_b32_e32 v0, s4954; VI-NEXT: v_mov_b32_e32 v1, s5955; VI-NEXT: s_add_u32 s4, s2, 4956; VI-NEXT: s_addc_u32 s5, s3, 0957; VI-NEXT: v_mov_b32_e32 v2, s4958; VI-NEXT: v_mov_b32_e32 v3, s5959; VI-NEXT: s_add_u32 s4, s2, 7960; VI-NEXT: s_addc_u32 s5, s3, 0961; VI-NEXT: v_mov_b32_e32 v4, s4962; VI-NEXT: v_mov_b32_e32 v5, s5963; VI-NEXT: s_add_u32 s4, s2, 6964; VI-NEXT: s_addc_u32 s5, s3, 0965; VI-NEXT: v_mov_b32_e32 v7, s5966; VI-NEXT: v_mov_b32_e32 v6, s4967; VI-NEXT: s_add_u32 s4, s2, 3968; VI-NEXT: s_addc_u32 s5, s3, 0969; VI-NEXT: v_mov_b32_e32 v9, s5970; VI-NEXT: v_mov_b32_e32 v8, s4971; VI-NEXT: s_add_u32 s4, s2, 2972; VI-NEXT: flat_load_ubyte v10, v[0:1]973; VI-NEXT: flat_load_ubyte v11, v[2:3]974; VI-NEXT: flat_load_ubyte v12, v[4:5]975; VI-NEXT: flat_load_ubyte v6, v[6:7]976; VI-NEXT: flat_load_ubyte v7, v[8:9]977; VI-NEXT: s_addc_u32 s5, s3, 0978; VI-NEXT: v_mov_b32_e32 v0, s4979; VI-NEXT: v_mov_b32_e32 v1, s5980; VI-NEXT: s_add_u32 s4, s2, 1981; VI-NEXT: s_addc_u32 s5, s3, 0982; VI-NEXT: v_mov_b32_e32 v2, s4983; VI-NEXT: v_mov_b32_e32 v3, s5984; VI-NEXT: v_mov_b32_e32 v5, s3985; VI-NEXT: v_mov_b32_e32 v4, s2986; VI-NEXT: flat_load_ubyte v0, v[0:1]987; VI-NEXT: flat_load_ubyte v2, v[2:3]988; VI-NEXT: flat_load_ubyte v3, v[4:5]989; VI-NEXT: v_mov_b32_e32 v1, 0990; VI-NEXT: s_waitcnt vmcnt(7)991; VI-NEXT: v_lshlrev_b32_e32 v4, 8, v10992; VI-NEXT: s_waitcnt vmcnt(6)993; VI-NEXT: v_or_b32_e32 v4, v4, v11994; VI-NEXT: s_waitcnt vmcnt(5)995; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v12996; VI-NEXT: s_waitcnt vmcnt(4)997; VI-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD998; VI-NEXT: v_or_b32_e32 v4, v5, v4999; VI-NEXT: s_waitcnt vmcnt(3)1000; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v71001; VI-NEXT: v_ffbh_u32_e32 v4, v41002; VI-NEXT: s_waitcnt vmcnt(2)1003; VI-NEXT: v_or_b32_sdwa v0, v5, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1004; VI-NEXT: s_waitcnt vmcnt(1)1005; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v21006; VI-NEXT: s_waitcnt vmcnt(0)1007; VI-NEXT: v_or_b32_e32 v2, v2, v31008; VI-NEXT: v_or_b32_e32 v0, v0, v21009; VI-NEXT: v_ffbh_u32_e32 v0, v01010; VI-NEXT: v_add_u32_e32 v0, vcc, 32, v01011; VI-NEXT: v_min_u32_e32 v0, v0, v41012; VI-NEXT: v_mov_b32_e32 v3, s11013; VI-NEXT: v_min_u32_e32 v0, 64, v01014; VI-NEXT: v_mov_b32_e32 v2, s01015; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]1016; VI-NEXT: s_endpgm1017;1018; EG-LABEL: v_ctlz_zero_undef_i64_with_select:1019; EG: ; %bb.0:1020; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]1021; EG-NEXT: TEX 3 @61022; EG-NEXT: ALU 15, @15, KC0[CB0:0-32], KC1[]1023; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11024; EG-NEXT: CF_END1025; EG-NEXT: PAD1026; EG-NEXT: Fetch clause starting at 6:1027; EG-NEXT: VTX_READ_16 T1.X, T0.X, 2, #11028; EG-NEXT: VTX_READ_16 T2.X, T0.X, 4, #11029; EG-NEXT: VTX_READ_16 T3.X, T0.X, 6, #11030; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #11031; EG-NEXT: ALU clause starting at 14:1032; EG-NEXT: MOV * T0.X, KC0[2].Z,1033; EG-NEXT: ALU clause starting at 15:1034; EG-NEXT: LSHL * T0.W, T1.X, literal.x,1035; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)1036; EG-NEXT: OR_INT * T0.W, PV.W, T0.X,1037; EG-NEXT: FFBH_UINT T1.W, PV.W,1038; EG-NEXT: LSHL * T2.W, T3.X, literal.x,1039; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)1040; EG-NEXT: CNDE_INT T0.W, T0.W, literal.x, PV.W,1041; EG-NEXT: OR_INT * T1.W, PS, T2.X,1042; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1043; EG-NEXT: FFBH_UINT T2.W, PS,1044; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,1045; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1046; EG-NEXT: CNDE_INT T0.X, T1.W, PS, PV.W,1047; EG-NEXT: MOV T0.Y, 0.0,1048; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1049; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1050;1051; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i64_with_select:1052; GFX9-GISEL: ; %bb.0:1053; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241054; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 01055; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)1056; GFX9-GISEL-NEXT: global_load_ubyte v0, v1, s[2:3]1057; GFX9-GISEL-NEXT: global_load_ubyte v2, v1, s[2:3] offset:11058; GFX9-GISEL-NEXT: global_load_ubyte v3, v1, s[2:3] offset:21059; GFX9-GISEL-NEXT: global_load_ubyte v4, v1, s[2:3] offset:31060; GFX9-GISEL-NEXT: global_load_ubyte v5, v1, s[2:3] offset:41061; GFX9-GISEL-NEXT: global_load_ubyte v6, v1, s[2:3] offset:51062; GFX9-GISEL-NEXT: global_load_ubyte v7, v1, s[2:3] offset:71063; GFX9-GISEL-NEXT: global_load_ubyte v8, v1, s[2:3] offset:61064; GFX9-GISEL-NEXT: s_waitcnt vmcnt(6)1065; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v2, 8, v01066; GFX9-GISEL-NEXT: s_waitcnt vmcnt(5)1067; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v31068; GFX9-GISEL-NEXT: s_waitcnt vmcnt(4)1069; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v41070; GFX9-GISEL-NEXT: v_or3_b32 v2, v2, v3, v01071; GFX9-GISEL-NEXT: s_waitcnt vmcnt(2)1072; GFX9-GISEL-NEXT: v_lshl_or_b32 v4, v6, 8, v51073; GFX9-GISEL-NEXT: s_waitcnt vmcnt(1)1074; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v5, 24, v71075; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)1076; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v6, 16, v81077; GFX9-GISEL-NEXT: v_or3_b32 v3, v5, v6, v41078; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v4, v21079; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v0, v31080; GFX9-GISEL-NEXT: v_add_u32_e32 v4, 32, v41081; GFX9-GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]1082; GFX9-GISEL-NEXT: v_min_u32_e32 v0, v0, v41083; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 64, v0, vcc1084; GFX9-GISEL-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]1085; GFX9-GISEL-NEXT: s_endpgm1086 %val = load i64, ptr addrspace(1) %arrayidx, align 11087 %ctlz = tail call i64 @llvm.ctlz.i64(i64 %val, i1 true) nounwind readnone1088 %ctlz_ret = icmp ne i64 %val, 01089 %ret = select i1 %ctlz_ret, i64 %ctlz, i64 641090 store i64 %ret, ptr addrspace(1) %out, align 41091 ret void1092}1093 1094define amdgpu_kernel void @v_ctlz_zero_undef_i8(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {1095; SI-LABEL: v_ctlz_zero_undef_i8:1096; SI: ; %bb.0:1097; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91098; SI-NEXT: s_mov_b32 s7, 0xf0001099; SI-NEXT: v_mov_b32_e32 v1, 01100; SI-NEXT: s_mov_b32 s10, 01101; SI-NEXT: s_mov_b32 s11, s71102; SI-NEXT: s_waitcnt lgkmcnt(0)1103; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1104; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[8:11], 0 addr641105; SI-NEXT: s_mov_b32 s6, -11106; SI-NEXT: s_mov_b32 s4, s01107; SI-NEXT: s_mov_b32 s5, s11108; SI-NEXT: s_waitcnt vmcnt(0)1109; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v01110; SI-NEXT: v_ffbh_u32_e32 v0, v01111; SI-NEXT: buffer_store_byte v0, off, s[4:7], 01112; SI-NEXT: s_endpgm1113;1114; VI-LABEL: v_ctlz_zero_undef_i8:1115; VI: ; %bb.0:1116; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241117; VI-NEXT: s_waitcnt lgkmcnt(0)1118; VI-NEXT: v_mov_b32_e32 v1, s31119; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01120; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1121; VI-NEXT: flat_load_ubyte v0, v[0:1]1122; VI-NEXT: s_waitcnt vmcnt(0)1123; VI-NEXT: v_lshlrev_b32_e32 v0, 24, v01124; VI-NEXT: v_ffbh_u32_e32 v2, v01125; VI-NEXT: v_mov_b32_e32 v0, s01126; VI-NEXT: v_mov_b32_e32 v1, s11127; VI-NEXT: flat_store_byte v[0:1], v21128; VI-NEXT: s_endpgm1129;1130; EG-LABEL: v_ctlz_zero_undef_i8:1131; EG: ; %bb.0:1132; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]1133; EG-NEXT: TEX 0 @61134; EG-NEXT: ALU 14, @9, KC0[CB0:0-32], KC1[]1135; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1136; EG-NEXT: CF_END1137; EG-NEXT: PAD1138; EG-NEXT: Fetch clause starting at 6:1139; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #11140; EG-NEXT: ALU clause starting at 8:1141; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, T0.X,1142; EG-NEXT: ALU clause starting at 9:1143; EG-NEXT: LSHL * T0.W, T0.X, literal.x,1144; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)1145; EG-NEXT: FFBH_UINT T0.W, PV.W,1146; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,1147; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1148; EG-NEXT: AND_INT T0.W, PV.W, literal.x,1149; EG-NEXT: LSHL * T1.W, PS, literal.y,1150; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)1151; EG-NEXT: LSHL T0.X, PV.W, PS,1152; EG-NEXT: LSHL * T0.W, literal.x, PS,1153; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)1154; EG-NEXT: MOV T0.Y, 0.0,1155; EG-NEXT: MOV * T0.Z, 0.0,1156; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1157; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1158;1159; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i8:1160; GFX9-GISEL: ; %bb.0:1161; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241162; GFX9-GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v01163; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)1164; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s21165; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s31166; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v1, v01167; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v3, vcc1168; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off1169; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 01170; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)1171; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 24, v01172; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v0, v01173; GFX9-GISEL-NEXT: global_store_byte v1, v0, s[0:1]1174; GFX9-GISEL-NEXT: s_endpgm1175 %tid = call i32 @llvm.amdgcn.workitem.id.x()1176 %in.gep = getelementptr i8, ptr addrspace(1) %valptr, i32 %tid1177 %val = load i8, ptr addrspace(1) %in.gep1178 %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 true) nounwind readnone1179 store i8 %ctlz, ptr addrspace(1) %out1180 ret void1181}1182 1183define amdgpu_kernel void @s_ctlz_zero_undef_i64(ptr addrspace(1) noalias %out, [8 x i32], i64 %val) nounwind {1184; SI-LABEL: s_ctlz_zero_undef_i64:1185; SI: ; %bb.0:1186; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x131187; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91188; SI-NEXT: s_mov_b32 s3, 0xf0001189; SI-NEXT: s_mov_b32 s2, -11190; SI-NEXT: s_waitcnt lgkmcnt(0)1191; SI-NEXT: s_flbit_i32_b64 s4, s[6:7]1192; SI-NEXT: v_mov_b32_e32 v1, 01193; SI-NEXT: v_mov_b32_e32 v0, s41194; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01195; SI-NEXT: s_endpgm1196;1197; VI-LABEL: s_ctlz_zero_undef_i64:1198; VI: ; %bb.0:1199; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x4c1200; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x241201; VI-NEXT: v_mov_b32_e32 v1, 01202; VI-NEXT: s_waitcnt lgkmcnt(0)1203; VI-NEXT: s_flbit_i32_b64 s0, s[0:1]1204; VI-NEXT: v_mov_b32_e32 v2, s21205; VI-NEXT: v_mov_b32_e32 v0, s01206; VI-NEXT: v_mov_b32_e32 v3, s31207; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]1208; VI-NEXT: s_endpgm1209;1210; EG-LABEL: s_ctlz_zero_undef_i64:1211; EG: ; %bb.0:1212; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]1213; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11214; EG-NEXT: CF_END1215; EG-NEXT: PAD1216; EG-NEXT: ALU clause starting at 4:1217; EG-NEXT: FFBH_UINT * T0.W, KC0[4].W,1218; EG-NEXT: FFBH_UINT T1.W, KC0[5].X,1219; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,1220; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1221; EG-NEXT: CNDE_INT T0.X, KC0[5].X, PS, PV.W,1222; EG-NEXT: MOV T0.Y, 0.0,1223; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1224; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1225;1226; GFX9-GISEL-LABEL: s_ctlz_zero_undef_i64:1227; GFX9-GISEL: ; %bb.0:1228; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x4c1229; GFX9-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x241230; GFX9-GISEL-NEXT: s_mov_b32 s5, 01231; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 01232; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)1233; GFX9-GISEL-NEXT: s_flbit_i32_b64 s4, s[0:1]1234; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s41235; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s51236; GFX9-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]1237; GFX9-GISEL-NEXT: s_endpgm1238 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true)1239 store i64 %ctlz, ptr addrspace(1) %out1240 ret void1241}1242 1243define amdgpu_kernel void @s_ctlz_zero_undef_i64_trunc(ptr addrspace(1) noalias %out, i64 %val) nounwind {1244; SI-LABEL: s_ctlz_zero_undef_i64_trunc:1245; SI: ; %bb.0:1246; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91247; SI-NEXT: s_mov_b32 s7, 0xf0001248; SI-NEXT: s_waitcnt lgkmcnt(0)1249; SI-NEXT: s_flbit_i32_b64 s2, s[2:3]1250; SI-NEXT: s_mov_b32 s6, -11251; SI-NEXT: s_mov_b32 s4, s01252; SI-NEXT: s_mov_b32 s5, s11253; SI-NEXT: v_mov_b32_e32 v0, s21254; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01255; SI-NEXT: s_endpgm1256;1257; VI-LABEL: s_ctlz_zero_undef_i64_trunc:1258; VI: ; %bb.0:1259; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241260; VI-NEXT: s_waitcnt lgkmcnt(0)1261; VI-NEXT: s_flbit_i32_b64 s2, s[2:3]1262; VI-NEXT: v_mov_b32_e32 v0, s01263; VI-NEXT: v_mov_b32_e32 v1, s11264; VI-NEXT: v_mov_b32_e32 v2, s21265; VI-NEXT: flat_store_dword v[0:1], v21266; VI-NEXT: s_endpgm1267;1268; EG-LABEL: s_ctlz_zero_undef_i64_trunc:1269; EG: ; %bb.0:1270; EG-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[]1271; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11272; EG-NEXT: CF_END1273; EG-NEXT: PAD1274; EG-NEXT: ALU clause starting at 4:1275; EG-NEXT: FFBH_UINT * T0.W, KC0[2].W,1276; EG-NEXT: FFBH_UINT T1.W, KC0[3].X,1277; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,1278; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1279; EG-NEXT: CNDE_INT T0.X, KC0[3].X, PS, PV.W,1280; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1281; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1282;1283; GFX9-GISEL-LABEL: s_ctlz_zero_undef_i64_trunc:1284; GFX9-GISEL: ; %bb.0:1285; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241286; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 01287; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)1288; GFX9-GISEL-NEXT: s_flbit_i32_b64 s2, s[2:3]1289; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s21290; GFX9-GISEL-NEXT: global_store_dword v1, v0, s[0:1]1291; GFX9-GISEL-NEXT: s_endpgm1292 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true)1293 %trunc = trunc i64 %ctlz to i321294 store i32 %trunc, ptr addrspace(1) %out1295 ret void1296}1297 1298define amdgpu_kernel void @v_ctlz_zero_undef_i64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {1299; SI-LABEL: v_ctlz_zero_undef_i64:1300; SI: ; %bb.0:1301; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91302; SI-NEXT: s_mov_b32 s7, 0xf0001303; SI-NEXT: s_mov_b32 s6, 01304; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v01305; SI-NEXT: v_mov_b32_e32 v1, 01306; SI-NEXT: s_waitcnt lgkmcnt(0)1307; SI-NEXT: s_mov_b64 s[4:5], s[2:3]1308; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr641309; SI-NEXT: s_mov_b64 s[2:3], s[6:7]1310; SI-NEXT: s_waitcnt vmcnt(0)1311; SI-NEXT: v_ffbh_u32_e32 v2, v21312; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v21313; SI-NEXT: v_ffbh_u32_e32 v3, v31314; SI-NEXT: v_min_u32_e32 v2, v2, v31315; SI-NEXT: v_mov_b32_e32 v3, v11316; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr641317; SI-NEXT: s_endpgm1318;1319; VI-LABEL: v_ctlz_zero_undef_i64:1320; VI: ; %bb.0:1321; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241322; VI-NEXT: v_lshlrev_b32_e32 v3, 3, v01323; VI-NEXT: v_mov_b32_e32 v2, 01324; VI-NEXT: s_waitcnt lgkmcnt(0)1325; VI-NEXT: v_mov_b32_e32 v1, s31326; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v31327; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1328; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]1329; VI-NEXT: v_mov_b32_e32 v4, s11330; VI-NEXT: v_add_u32_e32 v3, vcc, s0, v31331; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc1332; VI-NEXT: s_waitcnt vmcnt(0)1333; VI-NEXT: v_ffbh_u32_e32 v0, v01334; VI-NEXT: v_add_u32_e32 v0, vcc, 32, v01335; VI-NEXT: v_ffbh_u32_e32 v1, v11336; VI-NEXT: v_min_u32_e32 v1, v0, v11337; VI-NEXT: flat_store_dwordx2 v[3:4], v[1:2]1338; VI-NEXT: s_endpgm1339;1340; EG-LABEL: v_ctlz_zero_undef_i64:1341; EG: ; %bb.0:1342; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]1343; EG-NEXT: TEX 0 @61344; EG-NEXT: ALU 8, @11, KC0[CB0:0-32], KC1[]1345; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11346; EG-NEXT: CF_END1347; EG-NEXT: PAD1348; EG-NEXT: Fetch clause starting at 6:1349; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #11350; EG-NEXT: ALU clause starting at 8:1351; EG-NEXT: LSHL * T0.W, T0.X, literal.x,1352; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1353; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1354; EG-NEXT: ALU clause starting at 11:1355; EG-NEXT: FFBH_UINT * T1.W, T0.X,1356; EG-NEXT: FFBH_UINT T2.W, T0.Y,1357; EG-NEXT: ADD_INT * T1.W, PV.W, literal.x,1358; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1359; EG-NEXT: CNDE_INT T0.X, T0.Y, PS, PV.W,1360; EG-NEXT: MOV T0.Y, 0.0,1361; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,1362; EG-NEXT: LSHR * T1.X, PV.W, literal.x,1363; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1364;1365; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i64:1366; GFX9-GISEL: ; %bb.0:1367; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241368; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v2, 3, v01369; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)1370; GFX9-GISEL-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3]1371; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)1372; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v0, v01373; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v1, v11374; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 32, v01375; GFX9-GISEL-NEXT: v_min_u32_e32 v0, v1, v01376; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 01377; GFX9-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]1378; GFX9-GISEL-NEXT: s_endpgm1379 %tid = call i32 @llvm.amdgcn.workitem.id.x()1380 %in.gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid1381 %out.gep = getelementptr i64, ptr addrspace(1) %out, i32 %tid1382 %val = load i64, ptr addrspace(1) %in.gep1383 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true)1384 store i64 %ctlz, ptr addrspace(1) %out.gep1385 ret void1386}1387 1388define amdgpu_kernel void @v_ctlz_zero_undef_i64_trunc(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {1389; SI-LABEL: v_ctlz_zero_undef_i64_trunc:1390; SI: ; %bb.0:1391; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91392; SI-NEXT: s_mov_b32 s7, 0xf0001393; SI-NEXT: s_mov_b32 s6, 01394; SI-NEXT: v_lshlrev_b32_e32 v1, 3, v01395; SI-NEXT: v_mov_b32_e32 v2, 01396; SI-NEXT: s_waitcnt lgkmcnt(0)1397; SI-NEXT: s_mov_b64 s[4:5], s[2:3]1398; SI-NEXT: buffer_load_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr641399; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v01400; SI-NEXT: s_mov_b64 s[2:3], s[6:7]1401; SI-NEXT: s_waitcnt vmcnt(0)1402; SI-NEXT: v_ffbh_u32_e32 v0, v31403; SI-NEXT: v_add_i32_e32 v0, vcc, 32, v01404; SI-NEXT: v_ffbh_u32_e32 v3, v41405; SI-NEXT: v_min_u32_e32 v0, v0, v31406; SI-NEXT: buffer_store_dword v0, v[1:2], s[0:3], 0 addr641407; SI-NEXT: s_endpgm1408;1409; VI-LABEL: v_ctlz_zero_undef_i64_trunc:1410; VI: ; %bb.0:1411; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241412; VI-NEXT: v_lshlrev_b32_e32 v1, 3, v01413; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v01414; VI-NEXT: s_waitcnt lgkmcnt(0)1415; VI-NEXT: v_mov_b32_e32 v2, s31416; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v11417; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc1418; VI-NEXT: flat_load_dwordx2 v[1:2], v[1:2]1419; VI-NEXT: v_mov_b32_e32 v4, s11420; VI-NEXT: v_add_u32_e32 v3, vcc, s0, v01421; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc1422; VI-NEXT: s_waitcnt vmcnt(0)1423; VI-NEXT: v_ffbh_u32_e32 v0, v11424; VI-NEXT: v_add_u32_e32 v0, vcc, 32, v01425; VI-NEXT: v_ffbh_u32_e32 v1, v21426; VI-NEXT: v_min_u32_e32 v0, v0, v11427; VI-NEXT: flat_store_dword v[3:4], v01428; VI-NEXT: s_endpgm1429;1430; EG-LABEL: v_ctlz_zero_undef_i64_trunc:1431; EG: ; %bb.0:1432; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]1433; EG-NEXT: TEX 0 @61434; EG-NEXT: ALU 8, @11, KC0[CB0:0-32], KC1[]1435; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11436; EG-NEXT: CF_END1437; EG-NEXT: PAD1438; EG-NEXT: Fetch clause starting at 6:1439; EG-NEXT: VTX_READ_64 T1.XY, T1.X, 0, #11440; EG-NEXT: ALU clause starting at 8:1441; EG-NEXT: LSHL * T0.W, T0.X, literal.x,1442; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1443; EG-NEXT: ADD_INT * T1.X, KC0[2].Z, PV.W,1444; EG-NEXT: ALU clause starting at 11:1445; EG-NEXT: FFBH_UINT * T0.W, T1.X,1446; EG-NEXT: LSHL T0.Z, T0.X, literal.x,1447; EG-NEXT: FFBH_UINT T1.W, T1.Y,1448; EG-NEXT: ADD_INT * T0.W, PV.W, literal.y,1449; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)1450; EG-NEXT: CNDE_INT T0.X, T1.Y, PS, PV.W,1451; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, PV.Z,1452; EG-NEXT: LSHR * T1.X, PV.W, literal.x,1453; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1454;1455; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i64_trunc:1456; GFX9-GISEL: ; %bb.0:1457; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241458; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v1, 3, v01459; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v01460; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)1461; GFX9-GISEL-NEXT: global_load_dwordx2 v[1:2], v1, s[2:3]1462; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)1463; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v1, v11464; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v2, v21465; GFX9-GISEL-NEXT: v_add_u32_e32 v1, 32, v11466; GFX9-GISEL-NEXT: v_min_u32_e32 v1, v2, v11467; GFX9-GISEL-NEXT: global_store_dword v0, v1, s[0:1]1468; GFX9-GISEL-NEXT: s_endpgm1469 %tid = call i32 @llvm.amdgcn.workitem.id.x()1470 %in.gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid1471 %out.gep = getelementptr i32, ptr addrspace(1) %out, i32 %tid1472 %val = load i64, ptr addrspace(1) %in.gep1473 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true)1474 %trunc = trunc i64 %ctlz to i321475 store i32 %trunc, ptr addrspace(1) %out.gep1476 ret void1477}1478 1479define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {1480; SI-LABEL: v_ctlz_zero_undef_i32_sel_eq_neg1:1481; SI: ; %bb.0:1482; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91483; SI-NEXT: s_mov_b32 s7, 0xf0001484; SI-NEXT: s_mov_b32 s10, 01485; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v01486; SI-NEXT: v_mov_b32_e32 v1, 01487; SI-NEXT: s_mov_b32 s11, s71488; SI-NEXT: s_waitcnt lgkmcnt(0)1489; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1490; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr641491; SI-NEXT: s_mov_b32 s6, -11492; SI-NEXT: s_mov_b32 s4, s01493; SI-NEXT: s_mov_b32 s5, s11494; SI-NEXT: s_waitcnt vmcnt(0)1495; SI-NEXT: v_ffbh_u32_e32 v0, v01496; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01497; SI-NEXT: s_endpgm1498;1499; VI-LABEL: v_ctlz_zero_undef_i32_sel_eq_neg1:1500; VI: ; %bb.0:1501; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241502; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v01503; VI-NEXT: s_waitcnt lgkmcnt(0)1504; VI-NEXT: v_mov_b32_e32 v1, s31505; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01506; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1507; VI-NEXT: flat_load_dword v0, v[0:1]1508; VI-NEXT: s_waitcnt vmcnt(0)1509; VI-NEXT: v_ffbh_u32_e32 v2, v01510; VI-NEXT: v_mov_b32_e32 v0, s01511; VI-NEXT: v_mov_b32_e32 v1, s11512; VI-NEXT: flat_store_dword v[0:1], v21513; VI-NEXT: s_endpgm1514;1515; EG-LABEL: v_ctlz_zero_undef_i32_sel_eq_neg1:1516; EG: ; %bb.0:1517; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]1518; EG-NEXT: TEX 0 @61519; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[]1520; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11521; EG-NEXT: CF_END1522; EG-NEXT: PAD1523; EG-NEXT: Fetch clause starting at 6:1524; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11525; EG-NEXT: ALU clause starting at 8:1526; EG-NEXT: LSHL * T0.W, T0.X, literal.x,1527; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1528; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1529; EG-NEXT: ALU clause starting at 11:1530; EG-NEXT: FFBH_UINT * T0.W, T0.X,1531; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W,1532; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,1533; EG-NEXT: -1(nan), 2(2.802597e-45)1534;1535; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i32_sel_eq_neg1:1536; GFX9-GISEL: ; %bb.0:1537; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241538; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v01539; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)1540; GFX9-GISEL-NEXT: global_load_dword v0, v0, s[2:3]1541; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)1542; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v1, v01543; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v01544; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, -1, vcc1545; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 01546; GFX9-GISEL-NEXT: global_store_dword v1, v0, s[0:1]1547; GFX9-GISEL-NEXT: s_endpgm1548 %tid = call i32 @llvm.amdgcn.workitem.id.x()1549 %in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid1550 %val = load i32, ptr addrspace(1) %in.gep1551 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone1552 %cmp = icmp eq i32 %val, 01553 %sel = select i1 %cmp, i32 -1, i32 %ctlz1554 store i32 %sel, ptr addrspace(1) %out1555 ret void1556}1557 1558define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {1559; SI-LABEL: v_ctlz_zero_undef_i32_sel_ne_neg1:1560; SI: ; %bb.0:1561; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91562; SI-NEXT: s_mov_b32 s7, 0xf0001563; SI-NEXT: s_mov_b32 s10, 01564; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v01565; SI-NEXT: v_mov_b32_e32 v1, 01566; SI-NEXT: s_mov_b32 s11, s71567; SI-NEXT: s_waitcnt lgkmcnt(0)1568; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1569; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr641570; SI-NEXT: s_mov_b32 s6, -11571; SI-NEXT: s_mov_b32 s4, s01572; SI-NEXT: s_mov_b32 s5, s11573; SI-NEXT: s_waitcnt vmcnt(0)1574; SI-NEXT: v_ffbh_u32_e32 v0, v01575; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01576; SI-NEXT: s_endpgm1577;1578; VI-LABEL: v_ctlz_zero_undef_i32_sel_ne_neg1:1579; VI: ; %bb.0:1580; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241581; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v01582; VI-NEXT: s_waitcnt lgkmcnt(0)1583; VI-NEXT: v_mov_b32_e32 v1, s31584; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01585; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1586; VI-NEXT: flat_load_dword v0, v[0:1]1587; VI-NEXT: s_waitcnt vmcnt(0)1588; VI-NEXT: v_ffbh_u32_e32 v2, v01589; VI-NEXT: v_mov_b32_e32 v0, s01590; VI-NEXT: v_mov_b32_e32 v1, s11591; VI-NEXT: flat_store_dword v[0:1], v21592; VI-NEXT: s_endpgm1593;1594; EG-LABEL: v_ctlz_zero_undef_i32_sel_ne_neg1:1595; EG: ; %bb.0:1596; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]1597; EG-NEXT: TEX 0 @61598; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[]1599; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11600; EG-NEXT: CF_END1601; EG-NEXT: PAD1602; EG-NEXT: Fetch clause starting at 6:1603; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11604; EG-NEXT: ALU clause starting at 8:1605; EG-NEXT: LSHL * T0.W, T0.X, literal.x,1606; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1607; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1608; EG-NEXT: ALU clause starting at 11:1609; EG-NEXT: FFBH_UINT * T0.W, T0.X,1610; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W,1611; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,1612; EG-NEXT: -1(nan), 2(2.802597e-45)1613;1614; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i32_sel_ne_neg1:1615; GFX9-GISEL: ; %bb.0:1616; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241617; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v01618; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)1619; GFX9-GISEL-NEXT: global_load_dword v0, v0, s[2:3]1620; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)1621; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v1, v01622; GFX9-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v01623; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, -1, v1, vcc1624; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 01625; GFX9-GISEL-NEXT: global_store_dword v1, v0, s[0:1]1626; GFX9-GISEL-NEXT: s_endpgm1627 %tid = call i32 @llvm.amdgcn.workitem.id.x()1628 %in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid1629 %val = load i32, ptr addrspace(1) %in.gep1630 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone1631 %cmp = icmp ne i32 %val, 01632 %sel = select i1 %cmp, i32 %ctlz, i32 -11633 store i32 %sel, ptr addrspace(1) %out1634 ret void1635}1636 1637define amdgpu_kernel void @v_ctlz_zero_undef_i8_sel_eq_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {1638; SI-LABEL: v_ctlz_zero_undef_i8_sel_eq_neg1:1639; SI: ; %bb.0:1640; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91641; SI-NEXT: s_mov_b32 s7, 0xf0001642; SI-NEXT: v_mov_b32_e32 v1, 01643; SI-NEXT: s_mov_b32 s10, 01644; SI-NEXT: s_mov_b32 s11, s71645; SI-NEXT: s_waitcnt lgkmcnt(0)1646; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1647; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[8:11], 0 addr641648; SI-NEXT: s_mov_b32 s6, -11649; SI-NEXT: s_mov_b32 s4, s01650; SI-NEXT: s_mov_b32 s5, s11651; SI-NEXT: s_waitcnt vmcnt(0)1652; SI-NEXT: v_ffbh_u32_e32 v0, v01653; SI-NEXT: buffer_store_byte v0, off, s[4:7], 01654; SI-NEXT: s_endpgm1655;1656; VI-LABEL: v_ctlz_zero_undef_i8_sel_eq_neg1:1657; VI: ; %bb.0:1658; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241659; VI-NEXT: s_waitcnt lgkmcnt(0)1660; VI-NEXT: v_mov_b32_e32 v1, s31661; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01662; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1663; VI-NEXT: flat_load_ubyte v0, v[0:1]1664; VI-NEXT: s_waitcnt vmcnt(0)1665; VI-NEXT: v_ffbh_u32_e32 v2, v01666; VI-NEXT: v_mov_b32_e32 v0, s01667; VI-NEXT: v_mov_b32_e32 v1, s11668; VI-NEXT: flat_store_byte v[0:1], v21669; VI-NEXT: s_endpgm1670;1671; EG-LABEL: v_ctlz_zero_undef_i8_sel_eq_neg1:1672; EG: ; %bb.0:1673; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]1674; EG-NEXT: TEX 0 @61675; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[]1676; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1677; EG-NEXT: CF_END1678; EG-NEXT: PAD1679; EG-NEXT: Fetch clause starting at 6:1680; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #11681; EG-NEXT: ALU clause starting at 8:1682; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, T0.X,1683; EG-NEXT: ALU clause starting at 9:1684; EG-NEXT: FFBH_UINT T0.W, T0.X,1685; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,1686; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1687; EG-NEXT: AND_INT T0.W, PV.W, literal.x,1688; EG-NEXT: LSHL * T1.W, PS, literal.y,1689; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)1690; EG-NEXT: LSHL T0.X, PV.W, PS,1691; EG-NEXT: LSHL * T0.W, literal.x, PS,1692; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)1693; EG-NEXT: MOV T0.Y, 0.0,1694; EG-NEXT: MOV * T0.Z, 0.0,1695; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1696; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1697;1698; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i8_sel_eq_neg1:1699; GFX9-GISEL: ; %bb.0:1700; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241701; GFX9-GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v01702; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)1703; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s21704; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s31705; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v1, v01706; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v3, vcc1707; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off1708; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 01709; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff1710; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)1711; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v3, 24, v01712; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v3, v31713; GFX9-GISEL-NEXT: v_cmp_eq_u32_sdwa vcc, v0, v1 src0_sel:BYTE_0 src1_sel:DWORD1714; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc1715; GFX9-GISEL-NEXT: global_store_byte v1, v0, s[0:1]1716; GFX9-GISEL-NEXT: s_endpgm1717 %tid = call i32 @llvm.amdgcn.workitem.id.x()1718 %valptr.gep = getelementptr i8, ptr addrspace(1) %valptr, i32 %tid1719 %val = load i8, ptr addrspace(1) %valptr.gep1720 %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 true) nounwind readnone1721 %cmp = icmp eq i8 %val, 01722 %sel = select i1 %cmp, i8 -1, i8 %ctlz1723 store i8 %sel, ptr addrspace(1) %out1724 ret void1725}1726 1727define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1_two_use(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {1728; SI-LABEL: v_ctlz_zero_undef_i32_sel_eq_neg1_two_use:1729; SI: ; %bb.0:1730; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91731; SI-NEXT: s_mov_b32 s7, 0xf0001732; SI-NEXT: s_mov_b32 s10, 01733; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v01734; SI-NEXT: v_mov_b32_e32 v1, 01735; SI-NEXT: s_mov_b32 s11, s71736; SI-NEXT: s_waitcnt lgkmcnt(0)1737; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1738; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr641739; SI-NEXT: s_mov_b32 s6, -11740; SI-NEXT: s_mov_b32 s4, s01741; SI-NEXT: s_mov_b32 s5, s11742; SI-NEXT: s_waitcnt vmcnt(0)1743; SI-NEXT: v_ffbh_u32_e32 v1, v01744; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v01745; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc1746; SI-NEXT: buffer_store_dword v1, off, s[4:7], 01747; SI-NEXT: s_waitcnt vmcnt(0)1748; SI-NEXT: buffer_store_byte v0, off, s[4:7], 01749; SI-NEXT: s_waitcnt vmcnt(0)1750; SI-NEXT: s_endpgm1751;1752; VI-LABEL: v_ctlz_zero_undef_i32_sel_eq_neg1_two_use:1753; VI: ; %bb.0:1754; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241755; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v01756; VI-NEXT: s_waitcnt lgkmcnt(0)1757; VI-NEXT: v_mov_b32_e32 v1, s31758; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01759; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1760; VI-NEXT: flat_load_dword v2, v[0:1]1761; VI-NEXT: v_mov_b32_e32 v0, s01762; VI-NEXT: v_mov_b32_e32 v1, s11763; VI-NEXT: s_waitcnt vmcnt(0)1764; VI-NEXT: v_ffbh_u32_e32 v3, v21765; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v21766; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc1767; VI-NEXT: flat_store_dword v[0:1], v31768; VI-NEXT: s_waitcnt vmcnt(0)1769; VI-NEXT: flat_store_byte v[0:1], v21770; VI-NEXT: s_waitcnt vmcnt(0)1771; VI-NEXT: s_endpgm1772;1773; EG-LABEL: v_ctlz_zero_undef_i32_sel_eq_neg1_two_use:1774; EG: ; %bb.0:1775; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]1776; EG-NEXT: TEX 0 @61777; EG-NEXT: ALU 11, @11, KC0[CB0:0-32], KC1[]1778; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T3.X, 01779; EG-NEXT: MEM_RAT MSKOR T1.XW, T2.X1780; EG-NEXT: CF_END1781; EG-NEXT: Fetch clause starting at 6:1782; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11783; EG-NEXT: ALU clause starting at 8:1784; EG-NEXT: LSHL * T0.W, T0.X, literal.x,1785; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1786; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1787; EG-NEXT: ALU clause starting at 11:1788; EG-NEXT: SETE_INT * T0.W, T0.X, 0.0,1789; EG-NEXT: AND_INT T1.X, PV.W, 1,1790; EG-NEXT: MOV * T1.W, literal.x,1791; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)1792; EG-NEXT: MOV T1.Y, 0.0,1793; EG-NEXT: MOV * T1.Z, 0.0,1794; EG-NEXT: MOV T2.X, literal.x,1795; EG-NEXT: FFBH_UINT * T0.W, T0.X,1796; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)1797; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W,1798; EG-NEXT: LSHR * T3.X, KC0[2].Y, literal.y,1799; EG-NEXT: -1(nan), 2(2.802597e-45)1800;1801; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i32_sel_eq_neg1_two_use:1802; GFX9-GISEL: ; %bb.0:1803; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241804; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v01805; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 01806; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)1807; GFX9-GISEL-NEXT: global_load_dword v0, v0, s[2:3]1808; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)1809; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v2, v01810; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v01811; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc1812; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc1813; GFX9-GISEL-NEXT: global_store_dword v1, v0, s[0:1]1814; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)1815; GFX9-GISEL-NEXT: global_store_byte v[0:1], v2, off1816; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)1817; GFX9-GISEL-NEXT: s_endpgm1818 %tid = call i32 @llvm.amdgcn.workitem.id.x()1819 %in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid1820 %val = load i32, ptr addrspace(1) %in.gep1821 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone1822 %cmp = icmp eq i32 %val, 01823 %sel = select i1 %cmp, i32 -1, i32 %ctlz1824 store volatile i32 %sel, ptr addrspace(1) %out1825 store volatile i1 %cmp, ptr addrspace(1) poison1826 ret void1827}1828 1829; Selected on wrong constant1830define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_0(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {1831; SI-LABEL: v_ctlz_zero_undef_i32_sel_eq_0:1832; SI: ; %bb.0:1833; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91834; SI-NEXT: s_mov_b32 s7, 0xf0001835; SI-NEXT: s_mov_b32 s10, 01836; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v01837; SI-NEXT: v_mov_b32_e32 v1, 01838; SI-NEXT: s_mov_b32 s11, s71839; SI-NEXT: s_waitcnt lgkmcnt(0)1840; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1841; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr641842; SI-NEXT: s_mov_b32 s6, -11843; SI-NEXT: s_mov_b32 s4, s01844; SI-NEXT: s_mov_b32 s5, s11845; SI-NEXT: s_waitcnt vmcnt(0)1846; SI-NEXT: v_ffbh_u32_e32 v1, v01847; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v01848; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc1849; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01850; SI-NEXT: s_endpgm1851;1852; VI-LABEL: v_ctlz_zero_undef_i32_sel_eq_0:1853; VI: ; %bb.0:1854; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241855; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v01856; VI-NEXT: s_waitcnt lgkmcnt(0)1857; VI-NEXT: v_mov_b32_e32 v1, s31858; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01859; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1860; VI-NEXT: flat_load_dword v0, v[0:1]1861; VI-NEXT: s_waitcnt vmcnt(0)1862; VI-NEXT: v_ffbh_u32_e32 v1, v01863; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v01864; VI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc1865; VI-NEXT: v_mov_b32_e32 v0, s01866; VI-NEXT: v_mov_b32_e32 v1, s11867; VI-NEXT: flat_store_dword v[0:1], v21868; VI-NEXT: s_endpgm1869;1870; EG-LABEL: v_ctlz_zero_undef_i32_sel_eq_0:1871; EG: ; %bb.0:1872; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]1873; EG-NEXT: TEX 0 @61874; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[]1875; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11876; EG-NEXT: CF_END1877; EG-NEXT: PAD1878; EG-NEXT: Fetch clause starting at 6:1879; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11880; EG-NEXT: ALU clause starting at 8:1881; EG-NEXT: LSHL * T0.W, T0.X, literal.x,1882; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1883; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1884; EG-NEXT: ALU clause starting at 11:1885; EG-NEXT: FFBH_UINT * T0.W, T0.X,1886; EG-NEXT: CNDE_INT T0.X, T0.X, 0.0, PV.W,1887; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1888; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1889;1890; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i32_sel_eq_0:1891; GFX9-GISEL: ; %bb.0:1892; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241893; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v01894; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)1895; GFX9-GISEL-NEXT: global_load_dword v0, v0, s[2:3]1896; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)1897; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v1, v01898; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v01899; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc1900; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 01901; GFX9-GISEL-NEXT: global_store_dword v1, v0, s[0:1]1902; GFX9-GISEL-NEXT: s_endpgm1903 %tid = call i32 @llvm.amdgcn.workitem.id.x()1904 %in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid1905 %val = load i32, ptr addrspace(1) %in.gep1906 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone1907 %cmp = icmp eq i32 %val, 01908 %sel = select i1 %cmp, i32 0, i32 %ctlz1909 store i32 %sel, ptr addrspace(1) %out1910 ret void1911}1912 1913; Selected on wrong constant1914define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_0(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {1915; SI-LABEL: v_ctlz_zero_undef_i32_sel_ne_0:1916; SI: ; %bb.0:1917; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91918; SI-NEXT: s_mov_b32 s7, 0xf0001919; SI-NEXT: s_mov_b32 s10, 01920; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v01921; SI-NEXT: v_mov_b32_e32 v1, 01922; SI-NEXT: s_mov_b32 s11, s71923; SI-NEXT: s_waitcnt lgkmcnt(0)1924; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1925; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr641926; SI-NEXT: s_mov_b32 s6, -11927; SI-NEXT: s_mov_b32 s4, s01928; SI-NEXT: s_mov_b32 s5, s11929; SI-NEXT: s_waitcnt vmcnt(0)1930; SI-NEXT: v_ffbh_u32_e32 v1, v01931; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v01932; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc1933; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01934; SI-NEXT: s_endpgm1935;1936; VI-LABEL: v_ctlz_zero_undef_i32_sel_ne_0:1937; VI: ; %bb.0:1938; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241939; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v01940; VI-NEXT: s_waitcnt lgkmcnt(0)1941; VI-NEXT: v_mov_b32_e32 v1, s31942; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01943; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1944; VI-NEXT: flat_load_dword v0, v[0:1]1945; VI-NEXT: s_waitcnt vmcnt(0)1946; VI-NEXT: v_ffbh_u32_e32 v1, v01947; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v01948; VI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc1949; VI-NEXT: v_mov_b32_e32 v0, s01950; VI-NEXT: v_mov_b32_e32 v1, s11951; VI-NEXT: flat_store_dword v[0:1], v21952; VI-NEXT: s_endpgm1953;1954; EG-LABEL: v_ctlz_zero_undef_i32_sel_ne_0:1955; EG: ; %bb.0:1956; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]1957; EG-NEXT: TEX 0 @61958; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[]1959; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11960; EG-NEXT: CF_END1961; EG-NEXT: PAD1962; EG-NEXT: Fetch clause starting at 6:1963; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11964; EG-NEXT: ALU clause starting at 8:1965; EG-NEXT: LSHL * T0.W, T0.X, literal.x,1966; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1967; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1968; EG-NEXT: ALU clause starting at 11:1969; EG-NEXT: FFBH_UINT * T0.W, T0.X,1970; EG-NEXT: CNDE_INT T0.X, T0.X, 0.0, PV.W,1971; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1972; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1973;1974; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i32_sel_ne_0:1975; GFX9-GISEL: ; %bb.0:1976; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241977; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v01978; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)1979; GFX9-GISEL-NEXT: global_load_dword v0, v0, s[2:3]1980; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)1981; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v1, v01982; GFX9-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v01983; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc1984; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 01985; GFX9-GISEL-NEXT: global_store_dword v1, v0, s[0:1]1986; GFX9-GISEL-NEXT: s_endpgm1987 %tid = call i32 @llvm.amdgcn.workitem.id.x()1988 %in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid1989 %val = load i32, ptr addrspace(1) %in.gep1990 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone1991 %cmp = icmp ne i32 %val, 01992 %sel = select i1 %cmp, i32 %ctlz, i32 01993 store i32 %sel, ptr addrspace(1) %out1994 ret void1995}1996 1997; Compare on wrong constant1998define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_cmp_non0(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {1999; SI-LABEL: v_ctlz_zero_undef_i32_sel_eq_cmp_non0:2000; SI: ; %bb.0:2001; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92002; SI-NEXT: s_mov_b32 s7, 0xf0002003; SI-NEXT: s_mov_b32 s10, 02004; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v02005; SI-NEXT: v_mov_b32_e32 v1, 02006; SI-NEXT: s_mov_b32 s11, s72007; SI-NEXT: s_waitcnt lgkmcnt(0)2008; SI-NEXT: s_mov_b64 s[8:9], s[2:3]2009; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr642010; SI-NEXT: s_mov_b32 s6, -12011; SI-NEXT: s_mov_b32 s4, s02012; SI-NEXT: s_mov_b32 s5, s12013; SI-NEXT: s_waitcnt vmcnt(0)2014; SI-NEXT: v_ffbh_u32_e32 v1, v02015; SI-NEXT: v_cmp_ne_u32_e32 vcc, 1, v02016; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc2017; SI-NEXT: buffer_store_dword v0, off, s[4:7], 02018; SI-NEXT: s_endpgm2019;2020; VI-LABEL: v_ctlz_zero_undef_i32_sel_eq_cmp_non0:2021; VI: ; %bb.0:2022; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x242023; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v02024; VI-NEXT: s_waitcnt lgkmcnt(0)2025; VI-NEXT: v_mov_b32_e32 v1, s32026; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v02027; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2028; VI-NEXT: flat_load_dword v0, v[0:1]2029; VI-NEXT: s_waitcnt vmcnt(0)2030; VI-NEXT: v_ffbh_u32_e32 v1, v02031; VI-NEXT: v_cmp_ne_u32_e32 vcc, 1, v02032; VI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc2033; VI-NEXT: v_mov_b32_e32 v0, s02034; VI-NEXT: v_mov_b32_e32 v1, s12035; VI-NEXT: flat_store_dword v[0:1], v22036; VI-NEXT: s_endpgm2037;2038; EG-LABEL: v_ctlz_zero_undef_i32_sel_eq_cmp_non0:2039; EG: ; %bb.0:2040; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]2041; EG-NEXT: TEX 0 @62042; EG-NEXT: ALU 4, @11, KC0[CB0:0-32], KC1[]2043; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 12044; EG-NEXT: CF_END2045; EG-NEXT: PAD2046; EG-NEXT: Fetch clause starting at 6:2047; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #12048; EG-NEXT: ALU clause starting at 8:2049; EG-NEXT: LSHL * T0.W, T0.X, literal.x,2050; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2051; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,2052; EG-NEXT: ALU clause starting at 11:2053; EG-NEXT: FFBH_UINT T0.W, T0.X,2054; EG-NEXT: SETE_INT * T1.W, T0.X, 1,2055; EG-NEXT: CNDE_INT T0.X, PS, PV.W, 0.0,2056; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,2057; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2058;2059; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i32_sel_eq_cmp_non0:2060; GFX9-GISEL: ; %bb.0:2061; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x242062; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v02063; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)2064; GFX9-GISEL-NEXT: global_load_dword v0, v0, s[2:3]2065; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)2066; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v1, v02067; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 1, v02068; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc2069; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 02070; GFX9-GISEL-NEXT: global_store_dword v1, v0, s[0:1]2071; GFX9-GISEL-NEXT: s_endpgm2072 %tid = call i32 @llvm.amdgcn.workitem.id.x()2073 %in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid2074 %val = load i32, ptr addrspace(1) %in.gep2075 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone2076 %cmp = icmp eq i32 %val, 12077 %sel = select i1 %cmp, i32 0, i32 %ctlz2078 store i32 %sel, ptr addrspace(1) %out2079 ret void2080}2081 2082; Selected on wrong constant2083define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_cmp_non0(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {2084; SI-LABEL: v_ctlz_zero_undef_i32_sel_ne_cmp_non0:2085; SI: ; %bb.0:2086; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92087; SI-NEXT: s_mov_b32 s7, 0xf0002088; SI-NEXT: s_mov_b32 s10, 02089; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v02090; SI-NEXT: v_mov_b32_e32 v1, 02091; SI-NEXT: s_mov_b32 s11, s72092; SI-NEXT: s_waitcnt lgkmcnt(0)2093; SI-NEXT: s_mov_b64 s[8:9], s[2:3]2094; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr642095; SI-NEXT: s_mov_b32 s6, -12096; SI-NEXT: s_mov_b32 s4, s02097; SI-NEXT: s_mov_b32 s5, s12098; SI-NEXT: s_waitcnt vmcnt(0)2099; SI-NEXT: v_ffbh_u32_e32 v1, v02100; SI-NEXT: v_cmp_ne_u32_e32 vcc, 1, v02101; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc2102; SI-NEXT: buffer_store_dword v0, off, s[4:7], 02103; SI-NEXT: s_endpgm2104;2105; VI-LABEL: v_ctlz_zero_undef_i32_sel_ne_cmp_non0:2106; VI: ; %bb.0:2107; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x242108; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v02109; VI-NEXT: s_waitcnt lgkmcnt(0)2110; VI-NEXT: v_mov_b32_e32 v1, s32111; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v02112; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2113; VI-NEXT: flat_load_dword v0, v[0:1]2114; VI-NEXT: s_waitcnt vmcnt(0)2115; VI-NEXT: v_ffbh_u32_e32 v1, v02116; VI-NEXT: v_cmp_ne_u32_e32 vcc, 1, v02117; VI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc2118; VI-NEXT: v_mov_b32_e32 v0, s02119; VI-NEXT: v_mov_b32_e32 v1, s12120; VI-NEXT: flat_store_dword v[0:1], v22121; VI-NEXT: s_endpgm2122;2123; EG-LABEL: v_ctlz_zero_undef_i32_sel_ne_cmp_non0:2124; EG: ; %bb.0:2125; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]2126; EG-NEXT: TEX 0 @62127; EG-NEXT: ALU 4, @11, KC0[CB0:0-32], KC1[]2128; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 12129; EG-NEXT: CF_END2130; EG-NEXT: PAD2131; EG-NEXT: Fetch clause starting at 6:2132; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #12133; EG-NEXT: ALU clause starting at 8:2134; EG-NEXT: LSHL * T0.W, T0.X, literal.x,2135; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2136; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,2137; EG-NEXT: ALU clause starting at 11:2138; EG-NEXT: FFBH_UINT T0.W, T0.X,2139; EG-NEXT: SETNE_INT * T1.W, T0.X, 1,2140; EG-NEXT: CNDE_INT T0.X, PS, 0.0, PV.W,2141; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,2142; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2143;2144; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i32_sel_ne_cmp_non0:2145; GFX9-GISEL: ; %bb.0:2146; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x242147; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v02148; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)2149; GFX9-GISEL-NEXT: global_load_dword v0, v0, s[2:3]2150; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)2151; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v1, v02152; GFX9-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 1, v02153; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc2154; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 02155; GFX9-GISEL-NEXT: global_store_dword v1, v0, s[0:1]2156; GFX9-GISEL-NEXT: s_endpgm2157 %tid = call i32 @llvm.amdgcn.workitem.id.x()2158 %in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid2159 %val = load i32, ptr addrspace(1) %in.gep2160 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone2161 %cmp = icmp ne i32 %val, 12162 %sel = select i1 %cmp, i32 %ctlz, i32 02163 store i32 %sel, ptr addrspace(1) %out2164 ret void2165}2166 2167define i7 @v_ctlz_zero_undef_i7(i7 %val) {2168; SI-LABEL: v_ctlz_zero_undef_i7:2169; SI: ; %bb.0:2170; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2171; SI-NEXT: v_lshlrev_b32_e32 v0, 25, v02172; SI-NEXT: v_ffbh_u32_e32 v0, v02173; SI-NEXT: s_setpc_b64 s[30:31]2174;2175; VI-LABEL: v_ctlz_zero_undef_i7:2176; VI: ; %bb.0:2177; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2178; VI-NEXT: v_lshlrev_b32_e32 v0, 25, v02179; VI-NEXT: v_ffbh_u32_e32 v0, v02180; VI-NEXT: s_setpc_b64 s[30:31]2181;2182; EG-LABEL: v_ctlz_zero_undef_i7:2183; EG: ; %bb.0:2184; EG-NEXT: CF_END2185; EG-NEXT: PAD2186;2187; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i7:2188; GFX9-GISEL: ; %bb.0:2189; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2190; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 25, v02191; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v0, v02192; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]2193 %ctlz = call i7 @llvm.ctlz.i7(i7 %val, i1 true)2194 ret i7 %ctlz2195}2196 2197define amdgpu_kernel void @s_ctlz_zero_undef_i18(ptr addrspace(1) noalias %out, i18 %val) nounwind {2198; SI-LABEL: s_ctlz_zero_undef_i18:2199; SI: ; %bb.0:2200; SI-NEXT: s_load_dword s2, s[4:5], 0xb2201; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x92202; SI-NEXT: s_mov_b32 s3, 0xf0002203; SI-NEXT: s_waitcnt lgkmcnt(0)2204; SI-NEXT: s_lshl_b32 s2, s2, 142205; SI-NEXT: s_flbit_i32_b32 s4, s22206; SI-NEXT: s_mov_b32 s2, -12207; SI-NEXT: v_mov_b32_e32 v0, s42208; SI-NEXT: s_bfe_u32 s4, s4, 0x200102209; SI-NEXT: buffer_store_short v0, off, s[0:3], 02210; SI-NEXT: s_waitcnt expcnt(0)2211; SI-NEXT: v_mov_b32_e32 v0, s42212; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:22213; SI-NEXT: s_endpgm2214;2215; VI-LABEL: s_ctlz_zero_undef_i18:2216; VI: ; %bb.0:2217; VI-NEXT: s_load_dword s2, s[4:5], 0x2c2218; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x242219; VI-NEXT: s_waitcnt lgkmcnt(0)2220; VI-NEXT: s_lshl_b32 s2, s2, 142221; VI-NEXT: v_mov_b32_e32 v0, s02222; VI-NEXT: s_flbit_i32_b32 s2, s22223; VI-NEXT: v_mov_b32_e32 v1, s12224; VI-NEXT: s_add_u32 s0, s0, 22225; VI-NEXT: v_mov_b32_e32 v2, s22226; VI-NEXT: s_addc_u32 s1, s1, 02227; VI-NEXT: flat_store_short v[0:1], v22228; VI-NEXT: s_bfe_u32 s2, s2, 0x200102229; VI-NEXT: v_mov_b32_e32 v0, s02230; VI-NEXT: v_mov_b32_e32 v1, s12231; VI-NEXT: v_mov_b32_e32 v2, s22232; VI-NEXT: flat_store_byte v[0:1], v22233; VI-NEXT: s_endpgm2234;2235; EG-LABEL: s_ctlz_zero_undef_i18:2236; EG: ; %bb.0:2237; EG-NEXT: ALU 28, @4, KC0[CB0:0-32], KC1[]2238; EG-NEXT: MEM_RAT MSKOR T1.XW, T3.X2239; EG-NEXT: MEM_RAT MSKOR T0.XW, T2.X2240; EG-NEXT: CF_END2241; EG-NEXT: ALU clause starting at 4:2242; EG-NEXT: LSHL * T0.W, KC0[2].Z, literal.x,2243; EG-NEXT: 14(1.961818e-44), 0(0.000000e+00)2244; EG-NEXT: FFBH_UINT T0.W, PV.W,2245; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,2246; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)2247; EG-NEXT: AND_INT T2.W, PV.W, literal.x,2248; EG-NEXT: LSHL * T1.W, PS, literal.y,2249; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)2250; EG-NEXT: LSHL T1.X, PV.W, PS,2251; EG-NEXT: LSHL * T1.W, literal.x, PS,2252; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)2253; EG-NEXT: MOV T1.Y, 0.0,2254; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,2255; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2256; EG-NEXT: AND_INT T3.W, PV.W, literal.x,2257; EG-NEXT: MOV * T4.W, literal.y,2258; EG-NEXT: 3(4.203895e-45), 2(2.802597e-45)2259; EG-NEXT: BFE_UINT T0.W, T0.W, literal.x, PS,2260; EG-NEXT: LSHL * T3.W, PV.W, literal.y,2261; EG-NEXT: 16(2.242078e-44), 3(4.203895e-45)2262; EG-NEXT: LSHL T0.X, PV.W, PS,2263; EG-NEXT: LSHL * T0.W, literal.x, PS,2264; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)2265; EG-NEXT: MOV T0.Y, 0.0,2266; EG-NEXT: MOV T1.Z, 0.0,2267; EG-NEXT: MOV * T0.Z, 0.0,2268; EG-NEXT: LSHR T2.X, T2.W, literal.x,2269; EG-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,2270; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2271;2272; GFX9-GISEL-LABEL: s_ctlz_zero_undef_i18:2273; GFX9-GISEL: ; %bb.0:2274; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c2275; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x242276; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 02277; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)2278; GFX9-GISEL-NEXT: s_lshl_b32 s2, s2, 142279; GFX9-GISEL-NEXT: s_flbit_i32_b32 s2, s22280; GFX9-GISEL-NEXT: s_and_b32 s2, s2, 0x3ffff2281; GFX9-GISEL-NEXT: s_lshr_b32 s3, s2, 162282; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s22283; GFX9-GISEL-NEXT: global_store_short v0, v1, s[0:1]2284; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s32285; GFX9-GISEL-NEXT: global_store_byte v0, v1, s[0:1] offset:22286; GFX9-GISEL-NEXT: s_endpgm2287 %ctlz = call i18 @llvm.ctlz.i18(i18 %val, i1 true) nounwind readnone2288 store i18 %ctlz, ptr addrspace(1) %out, align 42289 ret void2290}2291 2292define i18 @v_ctlz_zero_undef_i18(i18 %val) {2293; SI-LABEL: v_ctlz_zero_undef_i18:2294; SI: ; %bb.0:2295; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2296; SI-NEXT: v_lshlrev_b32_e32 v0, 14, v02297; SI-NEXT: v_ffbh_u32_e32 v0, v02298; SI-NEXT: s_setpc_b64 s[30:31]2299;2300; VI-LABEL: v_ctlz_zero_undef_i18:2301; VI: ; %bb.0:2302; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2303; VI-NEXT: v_lshlrev_b32_e32 v0, 14, v02304; VI-NEXT: v_ffbh_u32_e32 v0, v02305; VI-NEXT: s_setpc_b64 s[30:31]2306;2307; EG-LABEL: v_ctlz_zero_undef_i18:2308; EG: ; %bb.0:2309; EG-NEXT: CF_END2310; EG-NEXT: PAD2311;2312; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i18:2313; GFX9-GISEL: ; %bb.0:2314; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2315; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 14, v02316; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v0, v02317; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]2318 %ctlz = call i18 @llvm.ctlz.i18(i18 %val, i1 true)2319 ret i18 %ctlz2320}2321 2322define <2 x i18> @v_ctlz_zero_undef_v2i18(<2 x i18> %val) {2323; SI-LABEL: v_ctlz_zero_undef_v2i18:2324; SI: ; %bb.0:2325; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2326; SI-NEXT: v_lshlrev_b32_e32 v0, 14, v02327; SI-NEXT: v_lshlrev_b32_e32 v1, 14, v12328; SI-NEXT: v_ffbh_u32_e32 v0, v02329; SI-NEXT: v_ffbh_u32_e32 v1, v12330; SI-NEXT: s_setpc_b64 s[30:31]2331;2332; VI-LABEL: v_ctlz_zero_undef_v2i18:2333; VI: ; %bb.0:2334; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2335; VI-NEXT: v_lshlrev_b32_e32 v0, 14, v02336; VI-NEXT: v_lshlrev_b32_e32 v1, 14, v12337; VI-NEXT: v_ffbh_u32_e32 v0, v02338; VI-NEXT: v_ffbh_u32_e32 v1, v12339; VI-NEXT: s_setpc_b64 s[30:31]2340;2341; EG-LABEL: v_ctlz_zero_undef_v2i18:2342; EG: ; %bb.0:2343; EG-NEXT: CF_END2344; EG-NEXT: PAD2345;2346; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v2i18:2347; GFX9-GISEL: ; %bb.0:2348; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2349; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 14, v02350; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v1, 14, v12351; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v0, v02352; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v1, v12353; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]2354 %ctlz = call <2 x i18> @llvm.ctlz.v2i18(<2 x i18> %val, i1 true)2355 ret <2 x i18> %ctlz2356}2357 2358define <2 x i16> @v_ctlz_zero_undef_v2i16(<2 x i16> %val) {2359; SI-LABEL: v_ctlz_zero_undef_v2i16:2360; SI: ; %bb.0:2361; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2362; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v12363; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v02364; SI-NEXT: v_ffbh_u32_e32 v1, v12365; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v12366; SI-NEXT: v_ffbh_u32_e32 v0, v02367; SI-NEXT: v_or_b32_e32 v0, v0, v22368; SI-NEXT: s_setpc_b64 s[30:31]2369;2370; VI-LABEL: v_ctlz_zero_undef_v2i16:2371; VI: ; %bb.0:2372; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2373; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v02374; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v02375; VI-NEXT: v_ffbh_u32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD2376; VI-NEXT: v_ffbh_u32_e32 v0, v02377; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD2378; VI-NEXT: s_setpc_b64 s[30:31]2379;2380; EG-LABEL: v_ctlz_zero_undef_v2i16:2381; EG: ; %bb.0:2382; EG-NEXT: CF_END2383; EG-NEXT: PAD2384;2385; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v2i16:2386; GFX9-GISEL: ; %bb.0:2387; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2388; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v02389; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v02390; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v0, v02391; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v12392; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v1, v12393; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v02394; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v02395; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]2396 %ctlz = call <2 x i16> @llvm.ctlz.v2i16(<2 x i16> %val, i1 true)2397 ret <2 x i16> %ctlz2398}2399 2400define <3 x i16> @v_ctlz_zero_undef_v3i16(<3 x i16> %val) {2401; SI-LABEL: v_ctlz_zero_undef_v3i16:2402; SI: ; %bb.0:2403; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2404; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v12405; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v02406; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v22407; SI-NEXT: v_ffbh_u32_e32 v1, v12408; SI-NEXT: v_ffbh_u32_e32 v0, v02409; SI-NEXT: v_ffbh_u32_e32 v3, v22410; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v12411; SI-NEXT: v_or_b32_e32 v0, v0, v12412; SI-NEXT: v_or_b32_e32 v2, 0x200000, v32413; SI-NEXT: v_alignbit_b32 v1, v3, v0, 162414; SI-NEXT: s_setpc_b64 s[30:31]2415;2416; VI-LABEL: v_ctlz_zero_undef_v3i16:2417; VI: ; %bb.0:2418; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2419; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v02420; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v02421; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v12422; VI-NEXT: v_ffbh_u32_e32 v2, v22423; VI-NEXT: v_ffbh_u32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD2424; VI-NEXT: v_ffbh_u32_e32 v1, v12425; VI-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD2426; VI-NEXT: s_setpc_b64 s[30:31]2427;2428; EG-LABEL: v_ctlz_zero_undef_v3i16:2429; EG: ; %bb.0:2430; EG-NEXT: CF_END2431; EG-NEXT: PAD2432;2433; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v3i16:2434; GFX9-GISEL: ; %bb.0:2435; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2436; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v02437; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v02438; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v0, v02439; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v2, 16, v22440; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v2, v22441; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v12442; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v02443; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v1, v12444; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v2, 16, v02445; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]2446 %ctlz = call <3 x i16> @llvm.ctlz.v3i16(<3 x i16> %val, i1 true)2447 ret <3 x i16> %ctlz2448}2449 2450define <4 x i16> @v_ctlz_zero_undef_v4i16(<4 x i16> %val) {2451; SI-LABEL: v_ctlz_zero_undef_v4i16:2452; SI: ; %bb.0:2453; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2454; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v32455; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v22456; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v12457; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v02458; SI-NEXT: v_ffbh_u32_e32 v3, v32459; SI-NEXT: v_ffbh_u32_e32 v2, v22460; SI-NEXT: v_ffbh_u32_e32 v1, v12461; SI-NEXT: v_ffbh_u32_e32 v0, v02462; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v32463; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v12464; SI-NEXT: v_or_b32_e32 v2, v2, v32465; SI-NEXT: v_or_b32_e32 v0, v0, v12466; SI-NEXT: v_alignbit_b32 v1, v2, v0, 162467; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v22468; SI-NEXT: s_setpc_b64 s[30:31]2469;2470; VI-LABEL: v_ctlz_zero_undef_v4i16:2471; VI: ; %bb.0:2472; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2473; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v12474; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v12475; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v02476; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v02477; VI-NEXT: v_ffbh_u32_e32 v2, v22478; VI-NEXT: v_ffbh_u32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD2479; VI-NEXT: v_ffbh_u32_e32 v3, v32480; VI-NEXT: v_ffbh_u32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD2481; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD2482; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD2483; VI-NEXT: s_setpc_b64 s[30:31]2484;2485; EG-LABEL: v_ctlz_zero_undef_v4i16:2486; EG: ; %bb.0:2487; EG-NEXT: CF_END2488; EG-NEXT: PAD2489;2490; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v4i16:2491; GFX9-GISEL: ; %bb.0:2492; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2493; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v02494; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v12495; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v02496; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v12497; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v0, v02498; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v2, 16, v22499; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v1, v12500; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v32501; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v2, v22502; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v3, v32503; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v02504; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v12505; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v2, 16, v02506; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, v3, 16, v12507; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]2508 %ctlz = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %val, i1 true)2509 ret <4 x i16> %ctlz2510}2511 2512define <2 x i8> @v_ctlz_zero_undef_v2i8(<2 x i8> %val) {2513; SI-LABEL: v_ctlz_zero_undef_v2i8:2514; SI: ; %bb.0:2515; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2516; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v12517; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v02518; SI-NEXT: v_ffbh_u32_e32 v1, v12519; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v12520; SI-NEXT: v_ffbh_u32_e32 v0, v02521; SI-NEXT: v_or_b32_e32 v0, v0, v22522; SI-NEXT: s_setpc_b64 s[30:31]2523;2524; VI-LABEL: v_ctlz_zero_undef_v2i8:2525; VI: ; %bb.0:2526; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2527; VI-NEXT: v_lshlrev_b32_e32 v1, 24, v12528; VI-NEXT: v_ffbh_u32_e32 v1, v12529; VI-NEXT: v_lshlrev_b32_e32 v0, 24, v02530; VI-NEXT: v_lshlrev_b16_e32 v2, 8, v12531; VI-NEXT: v_ffbh_u32_e32 v0, v02532; VI-NEXT: v_or_b32_e32 v0, v0, v22533; VI-NEXT: v_and_b32_e32 v1, 0xff, v12534; VI-NEXT: s_setpc_b64 s[30:31]2535;2536; EG-LABEL: v_ctlz_zero_undef_v2i8:2537; EG: ; %bb.0:2538; EG-NEXT: CF_END2539; EG-NEXT: PAD2540;2541; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v2i8:2542; GFX9-GISEL: ; %bb.0:2543; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2544; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 24, v02545; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v12546; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v0, v02547; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v1, v12548; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]2549 %ctlz = call <2 x i8> @llvm.ctlz.v2i8(<2 x i8> %val, i1 true)2550 ret <2 x i8> %ctlz2551}2552 2553define <2 x i7> @v_ctlz_zero_undef_v2i7(<2 x i7> %val) {2554; SI-LABEL: v_ctlz_zero_undef_v2i7:2555; SI: ; %bb.0:2556; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2557; SI-NEXT: v_lshlrev_b32_e32 v0, 25, v02558; SI-NEXT: v_lshlrev_b32_e32 v1, 25, v12559; SI-NEXT: v_ffbh_u32_e32 v0, v02560; SI-NEXT: v_ffbh_u32_e32 v1, v12561; SI-NEXT: s_setpc_b64 s[30:31]2562;2563; VI-LABEL: v_ctlz_zero_undef_v2i7:2564; VI: ; %bb.0:2565; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2566; VI-NEXT: v_lshlrev_b32_e32 v0, 25, v02567; VI-NEXT: v_lshlrev_b32_e32 v1, 25, v12568; VI-NEXT: v_ffbh_u32_e32 v0, v02569; VI-NEXT: v_ffbh_u32_e32 v1, v12570; VI-NEXT: s_setpc_b64 s[30:31]2571;2572; EG-LABEL: v_ctlz_zero_undef_v2i7:2573; EG: ; %bb.0:2574; EG-NEXT: CF_END2575; EG-NEXT: PAD2576;2577; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v2i7:2578; GFX9-GISEL: ; %bb.0:2579; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2580; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 25, v02581; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v1, 25, v12582; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v0, v02583; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v1, v12584; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]2585 %ctlz = call <2 x i7> @llvm.ctlz.v2i7(<2 x i7> %val, i1 true)2586 ret <2 x i7> %ctlz2587}2588