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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -enable-var-scope -check-prefixes=SI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=VI %s4; RUN: llc -mtriple=r600 -mcpu=cypress < %s | FileCheck -enable-var-scope -check-prefix=EG %s5 6declare i16 @llvm.ctpop.i16(i16) nounwind readnone7declare <2 x i16> @llvm.ctpop.v2i16(<2 x i16>) nounwind readnone8declare <4 x i16> @llvm.ctpop.v4i16(<4 x i16>) nounwind readnone9declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>) nounwind readnone10declare <16 x i16> @llvm.ctpop.v16i16(<16 x i16>) nounwind readnone11 12declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone13 14define amdgpu_kernel void @s_ctpop_i16(ptr addrspace(1) noalias %out, i16 %val) nounwind {15; SI-LABEL: s_ctpop_i16:16; SI: ; %bb.0:17; SI-NEXT: s_load_dword s6, s[4:5], 0xb18; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x919; SI-NEXT: s_mov_b32 s3, 0xf00020; SI-NEXT: s_mov_b32 s2, -121; SI-NEXT: s_waitcnt lgkmcnt(0)22; SI-NEXT: s_and_b32 s4, s6, 0xffff23; SI-NEXT: s_bcnt1_i32_b32 s4, s424; SI-NEXT: v_mov_b32_e32 v0, s425; SI-NEXT: buffer_store_short v0, off, s[0:3], 026; SI-NEXT: s_endpgm27;28; VI-LABEL: s_ctpop_i16:29; VI: ; %bb.0:30; VI-NEXT: s_load_dword s6, s[4:5], 0x2c31; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2432; VI-NEXT: s_mov_b32 s3, 0xf00033; VI-NEXT: s_mov_b32 s2, -134; VI-NEXT: s_waitcnt lgkmcnt(0)35; VI-NEXT: s_and_b32 s4, s6, 0xffff36; VI-NEXT: s_bcnt1_i32_b32 s4, s437; VI-NEXT: v_mov_b32_e32 v0, s438; VI-NEXT: buffer_store_short v0, off, s[0:3], 039; VI-NEXT: s_endpgm40;41; EG-LABEL: s_ctpop_i16:42; EG: ; %bb.0:43; EG-NEXT: ALU 0, @8, KC0[], KC1[]44; EG-NEXT: TEX 0 @645; EG-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]46; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X47; EG-NEXT: CF_END48; EG-NEXT: PAD49; EG-NEXT: Fetch clause starting at 6:50; EG-NEXT: VTX_READ_16 T0.X, T0.X, 40, #351; EG-NEXT: ALU clause starting at 8:52; EG-NEXT: MOV * T0.X, 0.0,53; EG-NEXT: ALU clause starting at 9:54; EG-NEXT: AND_INT * T0.W, KC0[2].Y, literal.x,55; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)56; EG-NEXT: BCNT_INT T1.W, T0.X,57; EG-NEXT: LSHL * T0.W, PV.W, literal.x,58; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)59; EG-NEXT: LSHL T0.X, PV.W, PS,60; EG-NEXT: LSHL * T0.W, literal.x, PS,61; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)62; EG-NEXT: MOV T0.Y, 0.0,63; EG-NEXT: MOV * T0.Z, 0.0,64; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,65; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)66 %ctpop = call i16 @llvm.ctpop.i16(i16 %val) nounwind readnone67 store i16 %ctpop, ptr addrspace(1) %out, align 468 ret void69}70 71; XXX - Why 0 in register?72define amdgpu_kernel void @v_ctpop_i16(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {73; SI-LABEL: v_ctpop_i16:74; SI: ; %bb.0:75; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x976; SI-NEXT: s_mov_b32 s7, 0xf00077; SI-NEXT: s_mov_b32 s10, 078; SI-NEXT: s_mov_b32 s11, s779; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v080; SI-NEXT: s_waitcnt lgkmcnt(0)81; SI-NEXT: s_mov_b64 s[8:9], s[2:3]82; SI-NEXT: v_mov_b32_e32 v1, 083; SI-NEXT: buffer_load_ushort v0, v[0:1], s[8:11], 0 addr6484; SI-NEXT: s_mov_b32 s6, -185; SI-NEXT: s_mov_b32 s4, s086; SI-NEXT: s_mov_b32 s5, s187; SI-NEXT: s_waitcnt vmcnt(0)88; SI-NEXT: v_bcnt_u32_b32_e64 v0, v0, 089; SI-NEXT: buffer_store_short v0, off, s[4:7], 090; SI-NEXT: s_endpgm91;92; VI-LABEL: v_ctpop_i16:93; VI: ; %bb.0:94; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2495; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v096; VI-NEXT: s_waitcnt lgkmcnt(0)97; VI-NEXT: v_mov_b32_e32 v1, s398; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v099; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc100; VI-NEXT: flat_load_ushort v0, v[0:1]101; VI-NEXT: s_mov_b32 s3, 0xf000102; VI-NEXT: s_mov_b32 s2, -1103; VI-NEXT: s_waitcnt vmcnt(0)104; VI-NEXT: v_bcnt_u32_b32 v0, v0, 0105; VI-NEXT: buffer_store_short v0, off, s[0:3], 0106; VI-NEXT: s_endpgm107;108; EG-LABEL: v_ctpop_i16:109; EG: ; %bb.0:110; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[]111; EG-NEXT: TEX 0 @6112; EG-NEXT: ALU 11, @10, KC0[CB0:0-32], KC1[]113; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X114; EG-NEXT: CF_END115; EG-NEXT: PAD116; EG-NEXT: Fetch clause starting at 6:117; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #1118; EG-NEXT: ALU clause starting at 8:119; EG-NEXT: LSHL * T0.W, T0.X, 1,120; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,121; EG-NEXT: ALU clause starting at 10:122; EG-NEXT: AND_INT * T0.W, KC0[2].Y, literal.x,123; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)124; EG-NEXT: BCNT_INT T1.W, T0.X,125; EG-NEXT: LSHL * T0.W, PV.W, literal.x,126; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)127; EG-NEXT: LSHL T0.X, PV.W, PS,128; EG-NEXT: LSHL * T0.W, literal.x, PS,129; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)130; EG-NEXT: MOV T0.Y, 0.0,131; EG-NEXT: MOV * T0.Z, 0.0,132; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,133; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)134 %tid = call i32 @llvm.amdgcn.workitem.id.x()135 %in.gep = getelementptr i16, ptr addrspace(1) %in, i32 %tid136 %val = load i16, ptr addrspace(1) %in.gep, align 4137 %ctpop = call i16 @llvm.ctpop.i16(i16 %val) nounwind readnone138 store i16 %ctpop, ptr addrspace(1) %out, align 4139 ret void140}141 142define amdgpu_kernel void @v_ctpop_add_chain_i16(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in0, ptr addrspace(1) noalias %in1) nounwind {143; SI-LABEL: v_ctpop_add_chain_i16:144; SI: ; %bb.0:145; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9146; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd147; SI-NEXT: s_mov_b32 s11, 0xf000148; SI-NEXT: s_mov_b32 s14, 0149; SI-NEXT: s_mov_b32 s15, s11150; SI-NEXT: s_waitcnt lgkmcnt(0)151; SI-NEXT: s_mov_b64 s[12:13], s[2:3]152; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0153; SI-NEXT: v_mov_b32_e32 v1, 0154; SI-NEXT: s_mov_b64 s[6:7], s[14:15]155; SI-NEXT: buffer_load_ushort v2, v[0:1], s[12:15], 0 addr64 glc156; SI-NEXT: s_waitcnt vmcnt(0)157; SI-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 glc158; SI-NEXT: s_waitcnt vmcnt(0)159; SI-NEXT: s_mov_b32 s10, -1160; SI-NEXT: s_mov_b32 s8, s0161; SI-NEXT: s_mov_b32 s9, s1162; SI-NEXT: v_bcnt_u32_b32_e64 v0, v0, 0163; SI-NEXT: v_bcnt_u32_b32_e32 v0, v2, v0164; SI-NEXT: buffer_store_short v0, off, s[8:11], 0165; SI-NEXT: s_endpgm166;167; VI-LABEL: v_ctpop_add_chain_i16:168; VI: ; %bb.0:169; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24170; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34171; VI-NEXT: v_lshlrev_b32_e32 v2, 1, v0172; VI-NEXT: s_waitcnt lgkmcnt(0)173; VI-NEXT: v_mov_b32_e32 v1, s3174; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2175; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc176; VI-NEXT: v_mov_b32_e32 v3, s5177; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2178; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc179; VI-NEXT: flat_load_ushort v0, v[0:1] glc180; VI-NEXT: s_waitcnt vmcnt(0)181; VI-NEXT: flat_load_ushort v1, v[2:3] glc182; VI-NEXT: s_waitcnt vmcnt(0)183; VI-NEXT: s_mov_b32 s3, 0xf000184; VI-NEXT: s_mov_b32 s2, -1185; VI-NEXT: v_bcnt_u32_b32 v1, v1, 0186; VI-NEXT: v_bcnt_u32_b32 v0, v0, v1187; VI-NEXT: buffer_store_short v0, off, s[0:3], 0188; VI-NEXT: s_endpgm189;190; EG-LABEL: v_ctpop_add_chain_i16:191; EG: ; %bb.0:192; EG-NEXT: ALU 1, @12, KC0[CB0:0-32], KC1[]193; EG-NEXT: TEX 0 @8194; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]195; EG-NEXT: TEX 0 @10196; EG-NEXT: ALU 16, @15, KC0[CB0:0-32], KC1[]197; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X198; EG-NEXT: CF_END199; EG-NEXT: PAD200; EG-NEXT: Fetch clause starting at 8:201; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #1202; EG-NEXT: Fetch clause starting at 10:203; EG-NEXT: VTX_READ_16 T1.X, T1.X, 0, #1204; EG-NEXT: ALU clause starting at 12:205; EG-NEXT: LSHL * T0.W, T0.X, 1,206; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,207; EG-NEXT: ALU clause starting at 14:208; EG-NEXT: ADD_INT * T1.X, KC0[2].W, T0.W,209; EG-NEXT: ALU clause starting at 15:210; EG-NEXT: AND_INT T0.W, T0.X, literal.x,211; EG-NEXT: AND_INT * T1.W, T1.X, literal.x,212; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)213; EG-NEXT: BCNT_INT T0.Z, PS,214; EG-NEXT: BCNT_INT T0.W, PV.W,215; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,216; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)217; EG-NEXT: ADD_INT T0.W, PV.W, PV.Z,218; EG-NEXT: LSHL * T1.W, PS, literal.x,219; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)220; EG-NEXT: LSHL T0.X, PV.W, PS,221; EG-NEXT: LSHL * T0.W, literal.x, PS,222; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)223; EG-NEXT: MOV T0.Y, 0.0,224; EG-NEXT: MOV * T0.Z, 0.0,225; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,226; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)227 %tid = call i32 @llvm.amdgcn.workitem.id.x()228 %in0.gep = getelementptr i16, ptr addrspace(1) %in0, i32 %tid229 %in1.gep = getelementptr i16, ptr addrspace(1) %in1, i32 %tid230 %val0 = load volatile i16, ptr addrspace(1) %in0.gep, align 4231 %val1 = load volatile i16, ptr addrspace(1) %in1.gep, align 4232 %ctpop0 = call i16 @llvm.ctpop.i16(i16 %val0) nounwind readnone233 %ctpop1 = call i16 @llvm.ctpop.i16(i16 %val1) nounwind readnone234 %add = add i16 %ctpop0, %ctpop1235 store i16 %add, ptr addrspace(1) %out, align 4236 ret void237}238 239define amdgpu_kernel void @v_ctpop_add_sgpr_i16(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, i16 %sval) nounwind {240; SI-LABEL: v_ctpop_add_sgpr_i16:241; SI: ; %bb.0:242; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9243; SI-NEXT: s_load_dword s12, s[4:5], 0xd244; SI-NEXT: s_mov_b32 s7, 0xf000245; SI-NEXT: s_mov_b32 s10, 0246; SI-NEXT: s_mov_b32 s11, s7247; SI-NEXT: s_waitcnt lgkmcnt(0)248; SI-NEXT: s_mov_b64 s[8:9], s[2:3]249; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0250; SI-NEXT: v_mov_b32_e32 v1, 0251; SI-NEXT: buffer_load_ushort v0, v[0:1], s[8:11], 0 addr64252; SI-NEXT: s_mov_b32 s6, -1253; SI-NEXT: s_mov_b32 s4, s0254; SI-NEXT: s_mov_b32 s5, s1255; SI-NEXT: s_waitcnt vmcnt(0)256; SI-NEXT: v_bcnt_u32_b32_e64 v0, v0, s12257; SI-NEXT: buffer_store_short v0, off, s[4:7], 0258; SI-NEXT: s_endpgm259;260; VI-LABEL: v_ctpop_add_sgpr_i16:261; VI: ; %bb.0:262; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24263; VI-NEXT: s_load_dword s4, s[4:5], 0x34264; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v0265; VI-NEXT: s_waitcnt lgkmcnt(0)266; VI-NEXT: v_mov_b32_e32 v1, s3267; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0268; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc269; VI-NEXT: flat_load_ushort v0, v[0:1]270; VI-NEXT: s_mov_b32 s3, 0xf000271; VI-NEXT: s_mov_b32 s2, -1272; VI-NEXT: s_waitcnt vmcnt(0)273; VI-NEXT: v_bcnt_u32_b32 v0, v0, s4274; VI-NEXT: buffer_store_short v0, off, s[0:3], 0275; VI-NEXT: s_endpgm276;277; EG-LABEL: v_ctpop_add_sgpr_i16:278; EG: ; %bb.0:279; EG-NEXT: ALU 1, @12, KC0[CB0:0-32], KC1[]280; EG-NEXT: TEX 0 @8281; EG-NEXT: ALU 0, @14, KC0[], KC1[]282; EG-NEXT: TEX 0 @10283; EG-NEXT: ALU 13, @15, KC0[CB0:0-32], KC1[]284; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X285; EG-NEXT: CF_END286; EG-NEXT: PAD287; EG-NEXT: Fetch clause starting at 8:288; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #1289; EG-NEXT: Fetch clause starting at 10:290; EG-NEXT: VTX_READ_16 T1.X, T1.X, 44, #3291; EG-NEXT: ALU clause starting at 12:292; EG-NEXT: LSHL * T0.W, T0.X, 1,293; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,294; EG-NEXT: ALU clause starting at 14:295; EG-NEXT: MOV * T1.X, 0.0,296; EG-NEXT: ALU clause starting at 15:297; EG-NEXT: BCNT_INT T0.W, T0.X,298; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,299; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)300; EG-NEXT: ADD_INT * T0.W, PV.W, T1.X,301; EG-NEXT: AND_INT T0.W, PV.W, literal.x,302; EG-NEXT: LSHL * T1.W, T1.W, literal.y,303; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)304; EG-NEXT: LSHL T0.X, PV.W, PS,305; EG-NEXT: LSHL * T0.W, literal.x, PS,306; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)307; EG-NEXT: MOV T0.Y, 0.0,308; EG-NEXT: MOV * T0.Z, 0.0,309; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,310; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)311 %tid = call i32 @llvm.amdgcn.workitem.id.x()312 %in.gep = getelementptr i16, ptr addrspace(1) %in, i32 %tid313 %val = load i16, ptr addrspace(1) %in.gep, align 4314 %ctpop = call i16 @llvm.ctpop.i16(i16 %val) nounwind readnone315 %add = add i16 %ctpop, %sval316 store i16 %add, ptr addrspace(1) %out, align 4317 ret void318}319 320define amdgpu_kernel void @v_ctpop_v2i16(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {321; SI-LABEL: v_ctpop_v2i16:322; SI: ; %bb.0:323; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9324; SI-NEXT: s_mov_b32 s7, 0xf000325; SI-NEXT: s_mov_b32 s10, 0326; SI-NEXT: s_mov_b32 s11, s7327; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0328; SI-NEXT: s_waitcnt lgkmcnt(0)329; SI-NEXT: s_mov_b64 s[8:9], s[2:3]330; SI-NEXT: v_mov_b32_e32 v1, 0331; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64332; SI-NEXT: s_mov_b32 s6, -1333; SI-NEXT: s_mov_b32 s4, s0334; SI-NEXT: s_mov_b32 s5, s1335; SI-NEXT: s_waitcnt vmcnt(0)336; SI-NEXT: v_and_b32_e32 v1, 0xffff, v0337; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0338; SI-NEXT: v_bcnt_u32_b32_e64 v0, v0, 0339; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0340; SI-NEXT: v_bcnt_u32_b32_e64 v1, v1, 0341; SI-NEXT: v_or_b32_e32 v0, v1, v0342; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0343; SI-NEXT: s_endpgm344;345; VI-LABEL: v_ctpop_v2i16:346; VI: ; %bb.0:347; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24348; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0349; VI-NEXT: s_waitcnt lgkmcnt(0)350; VI-NEXT: v_mov_b32_e32 v1, s3351; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0352; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc353; VI-NEXT: flat_load_dword v0, v[0:1]354; VI-NEXT: s_mov_b32 s3, 0xf000355; VI-NEXT: s_mov_b32 s2, -1356; VI-NEXT: s_waitcnt vmcnt(0)357; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0358; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0359; VI-NEXT: v_bcnt_u32_b32 v1, v1, 0360; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1361; VI-NEXT: v_bcnt_u32_b32 v0, v0, 0362; VI-NEXT: v_or_b32_e32 v0, v0, v1363; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0364; VI-NEXT: s_endpgm365;366; EG-LABEL: v_ctpop_v2i16:367; EG: ; %bb.0:368; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]369; EG-NEXT: TEX 0 @6370; EG-NEXT: ALU 10, @11, KC0[CB0:0-32], KC1[]371; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T6.X, 1372; EG-NEXT: CF_END373; EG-NEXT: PAD374; EG-NEXT: Fetch clause starting at 6:375; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1376; EG-NEXT: ALU clause starting at 8:377; EG-NEXT: LSHL * T0.W, T0.X, literal.x,378; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)379; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,380; EG-NEXT: ALU clause starting at 11:381; EG-NEXT: LSHR * T0.W, T0.X, literal.x,382; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)383; EG-NEXT: BCNT_INT T0.W, PV.W,384; EG-NEXT: AND_INT * T1.W, T0.X, literal.x,385; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)386; EG-NEXT: BCNT_INT T1.W, PS,387; EG-NEXT: LSHL * T0.W, PV.W, literal.x,388; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)389; EG-NEXT: OR_INT T0.X, PV.W, PS,390; EG-NEXT: LSHR * T6.X, KC0[2].Y, literal.x,391; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)392 %tid = call i32 @llvm.amdgcn.workitem.id.x()393 %in.gep = getelementptr <2 x i16>, ptr addrspace(1) %in, i32 %tid394 %val = load <2 x i16>, ptr addrspace(1) %in.gep, align 8395 %ctpop = call <2 x i16> @llvm.ctpop.v2i16(<2 x i16> %val) nounwind readnone396 store <2 x i16> %ctpop, ptr addrspace(1) %out, align 8397 ret void398}399 400define amdgpu_kernel void @v_ctpop_v4i16(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {401; SI-LABEL: v_ctpop_v4i16:402; SI: ; %bb.0:403; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9404; SI-NEXT: s_mov_b32 s7, 0xf000405; SI-NEXT: s_mov_b32 s10, 0406; SI-NEXT: s_mov_b32 s11, s7407; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0408; SI-NEXT: s_waitcnt lgkmcnt(0)409; SI-NEXT: s_mov_b64 s[8:9], s[2:3]410; SI-NEXT: v_mov_b32_e32 v1, 0411; SI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[8:11], 0 addr64412; SI-NEXT: s_mov_b32 s6, -1413; SI-NEXT: s_mov_b32 s4, s0414; SI-NEXT: s_mov_b32 s5, s1415; SI-NEXT: s_waitcnt vmcnt(0)416; SI-NEXT: v_and_b32_e32 v2, 0xffff, v0417; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0418; SI-NEXT: v_and_b32_e32 v3, 0xffff, v1419; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1420; SI-NEXT: v_bcnt_u32_b32_e64 v1, v1, 0421; SI-NEXT: v_bcnt_u32_b32_e64 v0, v0, 0422; SI-NEXT: v_bcnt_u32_b32_e64 v3, v3, 0423; SI-NEXT: v_bcnt_u32_b32_e64 v2, v2, 0424; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1425; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0426; SI-NEXT: v_or_b32_e32 v1, v3, v1427; SI-NEXT: v_or_b32_e32 v0, v2, v0428; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0429; SI-NEXT: s_endpgm430;431; VI-LABEL: v_ctpop_v4i16:432; VI: ; %bb.0:433; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24434; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0435; VI-NEXT: s_waitcnt lgkmcnt(0)436; VI-NEXT: v_mov_b32_e32 v1, s3437; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0438; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc439; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]440; VI-NEXT: s_mov_b32 s3, 0xf000441; VI-NEXT: s_mov_b32 s2, -1442; VI-NEXT: s_waitcnt vmcnt(0)443; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v1444; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0445; VI-NEXT: v_and_b32_e32 v1, 0xffff, v1446; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0447; VI-NEXT: v_bcnt_u32_b32 v2, v2, 0448; VI-NEXT: v_bcnt_u32_b32 v3, v3, 0449; VI-NEXT: v_bcnt_u32_b32 v1, v1, 0450; VI-NEXT: v_bcnt_u32_b32 v0, v0, 0451; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2452; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3453; VI-NEXT: v_or_b32_e32 v1, v1, v2454; VI-NEXT: v_or_b32_e32 v0, v0, v3455; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0456; VI-NEXT: s_endpgm457;458; EG-LABEL: v_ctpop_v4i16:459; EG: ; %bb.0:460; EG-NEXT: ALU 3, @8, KC0[CB0:0-32], KC1[]461; EG-NEXT: TEX 0 @6462; EG-NEXT: ALU 37, @12, KC0[CB0:0-32], KC1[]463; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XY, T0.X, 1464; EG-NEXT: CF_END465; EG-NEXT: PAD466; EG-NEXT: Fetch clause starting at 6:467; EG-NEXT: VTX_READ_64 T8.XY, T0.X, 0, #1468; EG-NEXT: ALU clause starting at 8:469; EG-NEXT: MOV T0.Y, T4.X,470; EG-NEXT: LSHL * T0.W, T0.X, literal.x, BS:VEC_120/SCL_212471; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)472; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,473; EG-NEXT: ALU clause starting at 12:474; EG-NEXT: AND_INT * T0.W, T8.X, literal.x,475; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)476; EG-NEXT: BCNT_INT T0.W, PV.W,477; EG-NEXT: AND_INT * T1.W, T0.Y, literal.x,478; EG-NEXT: -65536(nan), 0(0.000000e+00)479; EG-NEXT: OR_INT * T0.W, PS, PV.W,480; EG-NEXT: MOV * T4.X, PV.W,481; EG-NEXT: MOV T0.X, PV.X,482; EG-NEXT: LSHR * T0.W, T8.X, literal.x,483; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)484; EG-NEXT: BCNT_INT T0.W, PV.W,485; EG-NEXT: AND_INT * T1.W, PV.X, literal.x,486; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)487; EG-NEXT: LSHL * T0.W, PV.W, literal.x,488; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)489; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,490; EG-NEXT: MOV T4.X, PV.W,491; EG-NEXT: MOV * T0.X, T5.X,492; EG-NEXT: AND_INT * T0.W, T8.Y, literal.x,493; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)494; EG-NEXT: BCNT_INT T0.W, PV.W,495; EG-NEXT: AND_INT * T1.W, T0.X, literal.x,496; EG-NEXT: -65536(nan), 0(0.000000e+00)497; EG-NEXT: OR_INT * T0.W, PS, PV.W,498; EG-NEXT: MOV * T5.X, PV.W,499; EG-NEXT: MOV T0.X, PV.X,500; EG-NEXT: LSHR * T0.W, T8.Y, literal.x,501; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)502; EG-NEXT: BCNT_INT T0.W, PV.W,503; EG-NEXT: AND_INT * T1.W, PV.X, literal.x,504; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)505; EG-NEXT: LSHL * T0.W, PV.W, literal.x,506; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)507; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,508; EG-NEXT: OR_INT * T8.Y, T1.W, PV.W,509; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)510; EG-NEXT: MOV T5.X, PV.Y,511; EG-NEXT: MOV * T8.X, T4.X,512 %tid = call i32 @llvm.amdgcn.workitem.id.x()513 %in.gep = getelementptr <4 x i16>, ptr addrspace(1) %in, i32 %tid514 %val = load <4 x i16>, ptr addrspace(1) %in.gep, align 16515 %ctpop = call <4 x i16> @llvm.ctpop.v4i16(<4 x i16> %val) nounwind readnone516 store <4 x i16> %ctpop, ptr addrspace(1) %out, align 16517 ret void518}519 520define amdgpu_kernel void @v_ctpop_v8i16(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {521; SI-LABEL: v_ctpop_v8i16:522; SI: ; %bb.0:523; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9524; SI-NEXT: s_mov_b32 s3, 0xf000525; SI-NEXT: s_mov_b32 s10, 0526; SI-NEXT: s_mov_b32 s11, s3527; SI-NEXT: v_lshlrev_b32_e32 v0, 4, v0528; SI-NEXT: s_waitcnt lgkmcnt(0)529; SI-NEXT: s_mov_b64 s[8:9], s[6:7]530; SI-NEXT: v_mov_b32_e32 v1, 0531; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64532; SI-NEXT: s_mov_b32 s2, -1533; SI-NEXT: s_mov_b32 s0, s4534; SI-NEXT: s_mov_b32 s1, s5535; SI-NEXT: s_waitcnt vmcnt(0)536; SI-NEXT: v_and_b32_e32 v4, 0xffff, v0537; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0538; SI-NEXT: v_and_b32_e32 v5, 0xffff, v1539; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1540; SI-NEXT: v_and_b32_e32 v6, 0xffff, v2541; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2542; SI-NEXT: v_and_b32_e32 v7, 0xffff, v3543; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3544; SI-NEXT: v_bcnt_u32_b32_e64 v3, v3, 0545; SI-NEXT: v_bcnt_u32_b32_e64 v2, v2, 0546; SI-NEXT: v_bcnt_u32_b32_e64 v1, v1, 0547; SI-NEXT: v_bcnt_u32_b32_e64 v0, v0, 0548; SI-NEXT: v_bcnt_u32_b32_e64 v7, v7, 0549; SI-NEXT: v_bcnt_u32_b32_e64 v6, v6, 0550; SI-NEXT: v_bcnt_u32_b32_e64 v5, v5, 0551; SI-NEXT: v_bcnt_u32_b32_e64 v4, v4, 0552; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3553; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2554; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1555; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0556; SI-NEXT: v_or_b32_e32 v3, v7, v3557; SI-NEXT: v_or_b32_e32 v2, v6, v2558; SI-NEXT: v_or_b32_e32 v1, v5, v1559; SI-NEXT: v_or_b32_e32 v0, v4, v0560; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0561; SI-NEXT: s_endpgm562;563; VI-LABEL: v_ctpop_v8i16:564; VI: ; %bb.0:565; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24566; VI-NEXT: v_lshlrev_b32_e32 v0, 4, v0567; VI-NEXT: s_waitcnt lgkmcnt(0)568; VI-NEXT: v_mov_b32_e32 v1, s3569; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0570; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc571; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]572; VI-NEXT: s_mov_b32 s3, 0xf000573; VI-NEXT: s_mov_b32 s2, -1574; VI-NEXT: s_waitcnt vmcnt(0)575; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v3576; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v2577; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v1578; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v0579; VI-NEXT: v_and_b32_e32 v3, 0xffff, v3580; VI-NEXT: v_and_b32_e32 v2, 0xffff, v2581; VI-NEXT: v_and_b32_e32 v1, 0xffff, v1582; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0583; VI-NEXT: v_bcnt_u32_b32 v4, v4, 0584; VI-NEXT: v_bcnt_u32_b32 v5, v5, 0585; VI-NEXT: v_bcnt_u32_b32 v6, v6, 0586; VI-NEXT: v_bcnt_u32_b32 v7, v7, 0587; VI-NEXT: v_bcnt_u32_b32 v3, v3, 0588; VI-NEXT: v_bcnt_u32_b32 v2, v2, 0589; VI-NEXT: v_bcnt_u32_b32 v1, v1, 0590; VI-NEXT: v_bcnt_u32_b32 v0, v0, 0591; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4592; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5593; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6594; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7595; VI-NEXT: v_or_b32_e32 v3, v3, v4596; VI-NEXT: v_or_b32_e32 v2, v2, v5597; VI-NEXT: v_or_b32_e32 v1, v1, v6598; VI-NEXT: v_or_b32_e32 v0, v0, v7599; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0600; VI-NEXT: s_endpgm601;602; EG-LABEL: v_ctpop_v8i16:603; EG: ; %bb.0:604; EG-NEXT: ALU 3, @8, KC0[CB0:0-32], KC1[]605; EG-NEXT: TEX 0 @6606; EG-NEXT: ALU 73, @12, KC0[CB0:0-32], KC1[]607; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T12.X, 1608; EG-NEXT: CF_END609; EG-NEXT: PAD610; EG-NEXT: Fetch clause starting at 6:611; EG-NEXT: VTX_READ_128 T12.XYZW, T0.X, 0, #1612; EG-NEXT: ALU clause starting at 8:613; EG-NEXT: MOV T0.Y, T4.X,614; EG-NEXT: LSHL * T0.W, T0.X, literal.x, BS:VEC_120/SCL_212615; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)616; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,617; EG-NEXT: ALU clause starting at 12:618; EG-NEXT: LSHR * T0.W, T12.X, literal.x,619; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)620; EG-NEXT: BCNT_INT * T0.W, PV.W,621; EG-NEXT: LSHL T0.W, PV.W, literal.x,622; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,623; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41)624; EG-NEXT: OR_INT * T0.W, PS, PV.W,625; EG-NEXT: MOV * T4.X, PV.W,626; EG-NEXT: MOV T0.X, PV.X,627; EG-NEXT: AND_INT * T0.W, T12.X, literal.x,628; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)629; EG-NEXT: BCNT_INT T0.W, PV.W,630; EG-NEXT: AND_INT * T1.W, PV.X, literal.x,631; EG-NEXT: -65536(nan), 0(0.000000e+00)632; EG-NEXT: OR_INT * T0.W, PS, PV.W,633; EG-NEXT: MOV T4.X, PV.W,634; EG-NEXT: MOV * T0.X, T5.X,635; EG-NEXT: LSHR * T0.W, T12.Y, literal.x,636; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)637; EG-NEXT: BCNT_INT T0.W, PV.W,638; EG-NEXT: AND_INT * T1.W, T0.X, literal.x,639; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)640; EG-NEXT: LSHL * T0.W, PV.W, literal.x,641; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)642; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,643; EG-NEXT: MOV * T5.X, PV.W,644; EG-NEXT: MOV T0.X, PV.X,645; EG-NEXT: AND_INT * T0.W, T12.Y, literal.x,646; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)647; EG-NEXT: BCNT_INT T0.W, PV.W,648; EG-NEXT: AND_INT * T1.W, PV.X, literal.x,649; EG-NEXT: -65536(nan), 0(0.000000e+00)650; EG-NEXT: OR_INT * T0.Y, PS, PV.W,651; EG-NEXT: MOV T5.X, PV.Y,652; EG-NEXT: MOV * T0.X, T8.X,653; EG-NEXT: LSHR * T0.W, T12.Z, literal.x,654; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)655; EG-NEXT: BCNT_INT T0.W, PV.W,656; EG-NEXT: AND_INT * T1.W, T0.X, literal.x,657; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)658; EG-NEXT: LSHL * T0.W, PV.W, literal.x,659; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)660; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,661; EG-NEXT: MOV * T8.X, PV.W,662; EG-NEXT: MOV T0.X, PV.X,663; EG-NEXT: AND_INT * T0.W, T12.Z, literal.x,664; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)665; EG-NEXT: BCNT_INT T0.W, PV.W,666; EG-NEXT: AND_INT * T1.W, PV.X, literal.x,667; EG-NEXT: -65536(nan), 0(0.000000e+00)668; EG-NEXT: OR_INT * T0.W, PS, PV.W,669; EG-NEXT: MOV T8.X, PV.W,670; EG-NEXT: MOV * T0.X, T9.X,671; EG-NEXT: LSHR * T0.W, T12.W, literal.x,672; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)673; EG-NEXT: BCNT_INT T0.W, PV.W,674; EG-NEXT: AND_INT * T1.W, T0.X, literal.x,675; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)676; EG-NEXT: LSHL * T0.W, PV.W, literal.x,677; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)678; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,679; EG-NEXT: MOV * T9.X, PV.W,680; EG-NEXT: MOV T0.X, PV.X,681; EG-NEXT: AND_INT * T0.W, T12.W, literal.x,682; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)683; EG-NEXT: BCNT_INT T0.W, PV.W,684; EG-NEXT: AND_INT * T1.W, PV.X, literal.x,685; EG-NEXT: -65536(nan), 0(0.000000e+00)686; EG-NEXT: LSHR T12.X, KC0[2].Y, literal.x,687; EG-NEXT: OR_INT * T0.W, PS, PV.W,688; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)689; EG-NEXT: MOV T9.X, PV.W,690; EG-NEXT: MOV * T0.X, T4.X,691; EG-NEXT: MOV * T0.Z, T8.X,692 %tid = call i32 @llvm.amdgcn.workitem.id.x()693 %in.gep = getelementptr <8 x i16>, ptr addrspace(1) %in, i32 %tid694 %val = load <8 x i16>, ptr addrspace(1) %in.gep, align 32695 %ctpop = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %val) nounwind readnone696 store <8 x i16> %ctpop, ptr addrspace(1) %out, align 32697 ret void698}699 700define amdgpu_kernel void @v_ctpop_v16i16(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {701; SI-LABEL: v_ctpop_v16i16:702; SI: ; %bb.0:703; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9704; SI-NEXT: s_mov_b32 s3, 0xf000705; SI-NEXT: s_mov_b32 s10, 0706; SI-NEXT: s_mov_b32 s11, s3707; SI-NEXT: v_lshlrev_b32_e32 v4, 5, v0708; SI-NEXT: s_waitcnt lgkmcnt(0)709; SI-NEXT: s_mov_b64 s[8:9], s[6:7]710; SI-NEXT: v_mov_b32_e32 v5, 0711; SI-NEXT: buffer_load_dwordx4 v[0:3], v[4:5], s[8:11], 0 addr64 offset:16712; SI-NEXT: buffer_load_dwordx4 v[4:7], v[4:5], s[8:11], 0 addr64713; SI-NEXT: s_mov_b32 s2, -1714; SI-NEXT: s_mov_b32 s0, s4715; SI-NEXT: s_mov_b32 s1, s5716; SI-NEXT: s_waitcnt vmcnt(1)717; SI-NEXT: v_and_b32_e32 v8, 0xffff, v0718; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0719; SI-NEXT: v_and_b32_e32 v9, 0xffff, v1720; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1721; SI-NEXT: v_and_b32_e32 v10, 0xffff, v2722; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2723; SI-NEXT: v_and_b32_e32 v11, 0xffff, v3724; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3725; SI-NEXT: s_waitcnt vmcnt(0)726; SI-NEXT: v_and_b32_e32 v12, 0xffff, v4727; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4728; SI-NEXT: v_and_b32_e32 v13, 0xffff, v5729; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5730; SI-NEXT: v_and_b32_e32 v14, 0xffff, v6731; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6732; SI-NEXT: v_and_b32_e32 v15, 0xffff, v7733; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7734; SI-NEXT: v_bcnt_u32_b32_e64 v7, v7, 0735; SI-NEXT: v_bcnt_u32_b32_e64 v6, v6, 0736; SI-NEXT: v_bcnt_u32_b32_e64 v5, v5, 0737; SI-NEXT: v_bcnt_u32_b32_e64 v4, v4, 0738; SI-NEXT: v_bcnt_u32_b32_e64 v3, v3, 0739; SI-NEXT: v_bcnt_u32_b32_e64 v2, v2, 0740; SI-NEXT: v_bcnt_u32_b32_e64 v1, v1, 0741; SI-NEXT: v_bcnt_u32_b32_e64 v0, v0, 0742; SI-NEXT: v_bcnt_u32_b32_e64 v15, v15, 0743; SI-NEXT: v_bcnt_u32_b32_e64 v14, v14, 0744; SI-NEXT: v_bcnt_u32_b32_e64 v13, v13, 0745; SI-NEXT: v_bcnt_u32_b32_e64 v12, v12, 0746; SI-NEXT: v_bcnt_u32_b32_e64 v11, v11, 0747; SI-NEXT: v_bcnt_u32_b32_e64 v10, v10, 0748; SI-NEXT: v_bcnt_u32_b32_e64 v9, v9, 0749; SI-NEXT: v_bcnt_u32_b32_e64 v8, v8, 0750; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7751; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6752; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5753; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4754; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v3755; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v2756; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v1757; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v0758; SI-NEXT: v_or_b32_e32 v3, v15, v7759; SI-NEXT: v_or_b32_e32 v2, v14, v6760; SI-NEXT: v_or_b32_e32 v1, v13, v5761; SI-NEXT: v_or_b32_e32 v0, v12, v4762; SI-NEXT: v_or_b32_e32 v7, v11, v16763; SI-NEXT: v_or_b32_e32 v6, v10, v17764; SI-NEXT: v_or_b32_e32 v5, v9, v18765; SI-NEXT: v_or_b32_e32 v4, v8, v19766; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16767; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0768; SI-NEXT: s_endpgm769;770; VI-LABEL: v_ctpop_v16i16:771; VI: ; %bb.0:772; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24773; VI-NEXT: v_lshlrev_b32_e32 v0, 5, v0774; VI-NEXT: s_waitcnt lgkmcnt(0)775; VI-NEXT: v_mov_b32_e32 v1, s3776; VI-NEXT: v_add_u32_e32 v4, vcc, s2, v0777; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc778; VI-NEXT: flat_load_dwordx4 v[0:3], v[4:5]779; VI-NEXT: v_add_u32_e32 v4, vcc, 16, v4780; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc781; VI-NEXT: flat_load_dwordx4 v[4:7], v[4:5]782; VI-NEXT: s_mov_b32 s3, 0xf000783; VI-NEXT: s_mov_b32 s2, -1784; VI-NEXT: s_waitcnt vmcnt(1)785; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v3786; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v2787; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v1788; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v0789; VI-NEXT: v_and_b32_e32 v3, 0xffff, v3790; VI-NEXT: v_and_b32_e32 v2, 0xffff, v2791; VI-NEXT: v_and_b32_e32 v1, 0xffff, v1792; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0793; VI-NEXT: s_waitcnt vmcnt(0)794; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v7795; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v6796; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v5797; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v4798; VI-NEXT: v_bcnt_u32_b32 v8, v8, 0799; VI-NEXT: v_bcnt_u32_b32 v9, v9, 0800; VI-NEXT: v_bcnt_u32_b32 v10, v10, 0801; VI-NEXT: v_bcnt_u32_b32 v11, v11, 0802; VI-NEXT: v_and_b32_e32 v7, 0xffff, v7803; VI-NEXT: v_and_b32_e32 v6, 0xffff, v6804; VI-NEXT: v_and_b32_e32 v5, 0xffff, v5805; VI-NEXT: v_and_b32_e32 v4, 0xffff, v4806; VI-NEXT: v_bcnt_u32_b32 v3, v3, 0807; VI-NEXT: v_bcnt_u32_b32 v2, v2, 0808; VI-NEXT: v_bcnt_u32_b32 v1, v1, 0809; VI-NEXT: v_bcnt_u32_b32 v0, v0, 0810; VI-NEXT: v_bcnt_u32_b32 v12, v12, 0811; VI-NEXT: v_bcnt_u32_b32 v13, v13, 0812; VI-NEXT: v_bcnt_u32_b32 v14, v14, 0813; VI-NEXT: v_bcnt_u32_b32 v15, v15, 0814; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8815; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9816; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10817; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11818; VI-NEXT: v_bcnt_u32_b32 v7, v7, 0819; VI-NEXT: v_bcnt_u32_b32 v6, v6, 0820; VI-NEXT: v_bcnt_u32_b32 v5, v5, 0821; VI-NEXT: v_bcnt_u32_b32 v4, v4, 0822; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12823; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13824; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14825; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15826; VI-NEXT: v_or_b32_e32 v3, v3, v8827; VI-NEXT: v_or_b32_e32 v2, v2, v9828; VI-NEXT: v_or_b32_e32 v1, v1, v10829; VI-NEXT: v_or_b32_e32 v0, v0, v11830; VI-NEXT: v_or_b32_e32 v7, v7, v12831; VI-NEXT: v_or_b32_e32 v6, v6, v13832; VI-NEXT: v_or_b32_e32 v5, v5, v14833; VI-NEXT: v_or_b32_e32 v4, v4, v15834; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0835; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16836; VI-NEXT: s_endpgm837;838; EG-LABEL: v_ctpop_v16i16:839; EG: ; %bb.0:840; EG-NEXT: ALU 3, @12, KC0[CB0:0-32], KC1[]841; EG-NEXT: TEX 1 @8842; EG-NEXT: ALU 114, @16, KC0[], KC1[]843; EG-NEXT: ALU 34, @131, KC0[CB0:0-32], KC1[]844; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T22.X, 0845; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T20.XYZW, T21.X, 1846; EG-NEXT: CF_END847; EG-NEXT: PAD848; EG-NEXT: Fetch clause starting at 8:849; EG-NEXT: VTX_READ_128 T20.XYZW, T0.X, 16, #1850; EG-NEXT: VTX_READ_128 T21.XYZW, T0.X, 0, #1851; EG-NEXT: ALU clause starting at 12:852; EG-NEXT: MOV T0.Y, T4.X,853; EG-NEXT: LSHL * T0.W, T0.X, literal.x, BS:VEC_120/SCL_212854; EG-NEXT: 5(7.006492e-45), 0(0.000000e+00)855; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,856; EG-NEXT: ALU clause starting at 16:857; EG-NEXT: LSHR * T0.W, T20.X, literal.x,858; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)859; EG-NEXT: BCNT_INT * T0.W, PV.W,860; EG-NEXT: LSHL T0.W, PV.W, literal.x,861; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,862; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41)863; EG-NEXT: OR_INT * T0.W, PS, PV.W,864; EG-NEXT: MOV * T4.X, PV.W,865; EG-NEXT: MOV T0.X, PV.X,866; EG-NEXT: AND_INT * T0.W, T20.X, literal.x,867; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)868; EG-NEXT: BCNT_INT T0.W, PV.W,869; EG-NEXT: AND_INT * T1.W, PV.X, literal.x,870; EG-NEXT: -65536(nan), 0(0.000000e+00)871; EG-NEXT: OR_INT * T0.W, PS, PV.W,872; EG-NEXT: MOV T4.X, PV.W,873; EG-NEXT: MOV * T0.X, T5.X,874; EG-NEXT: LSHR * T0.W, T20.Y, literal.x,875; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)876; EG-NEXT: BCNT_INT T0.W, PV.W,877; EG-NEXT: AND_INT * T1.W, T0.X, literal.x,878; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)879; EG-NEXT: LSHL * T0.W, PV.W, literal.x,880; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)881; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,882; EG-NEXT: MOV * T5.X, PV.W,883; EG-NEXT: MOV T0.X, PV.X,884; EG-NEXT: AND_INT * T0.W, T20.Y, literal.x,885; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)886; EG-NEXT: BCNT_INT T0.W, PV.W,887; EG-NEXT: AND_INT * T1.W, PV.X, literal.x,888; EG-NEXT: -65536(nan), 0(0.000000e+00)889; EG-NEXT: OR_INT * T0.Y, PS, PV.W,890; EG-NEXT: MOV T5.X, PV.Y,891; EG-NEXT: MOV * T0.X, T8.X,892; EG-NEXT: LSHR * T0.W, T20.Z, literal.x,893; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)894; EG-NEXT: BCNT_INT T0.W, PV.W,895; EG-NEXT: AND_INT * T1.W, T0.X, literal.x,896; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)897; EG-NEXT: LSHL * T0.W, PV.W, literal.x,898; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)899; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,900; EG-NEXT: MOV * T8.X, PV.W,901; EG-NEXT: MOV T0.X, PV.X,902; EG-NEXT: AND_INT * T0.W, T20.Z, literal.x,903; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)904; EG-NEXT: BCNT_INT T0.W, PV.W,905; EG-NEXT: AND_INT * T1.W, PV.X, literal.x,906; EG-NEXT: -65536(nan), 0(0.000000e+00)907; EG-NEXT: OR_INT * T0.W, PS, PV.W,908; EG-NEXT: MOV T8.X, PV.W,909; EG-NEXT: MOV * T0.X, T9.X,910; EG-NEXT: LSHR * T0.W, T20.W, literal.x,911; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)912; EG-NEXT: BCNT_INT T0.W, PV.W,913; EG-NEXT: AND_INT * T1.W, T0.X, literal.x,914; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)915; EG-NEXT: LSHL * T0.W, PV.W, literal.x,916; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)917; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,918; EG-NEXT: MOV * T9.X, PV.W,919; EG-NEXT: MOV T0.X, PV.X,920; EG-NEXT: AND_INT * T0.W, T20.W, literal.x,921; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)922; EG-NEXT: BCNT_INT T0.W, PV.W,923; EG-NEXT: AND_INT * T1.W, PV.X, literal.x,924; EG-NEXT: -65536(nan), 0(0.000000e+00)925; EG-NEXT: OR_INT * T0.W, PS, PV.W,926; EG-NEXT: MOV T9.X, PV.W,927; EG-NEXT: MOV * T0.X, T12.X,928; EG-NEXT: LSHR * T1.W, T21.X, literal.x,929; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)930; EG-NEXT: BCNT_INT T1.W, PV.W,931; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,932; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)933; EG-NEXT: LSHL * T1.W, PV.W, literal.x,934; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)935; EG-NEXT: OR_INT * T1.W, T2.W, PV.W,936; EG-NEXT: MOV * T12.X, PV.W,937; EG-NEXT: MOV T0.X, PV.X,938; EG-NEXT: AND_INT * T1.W, T21.X, literal.x,939; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)940; EG-NEXT: BCNT_INT T1.W, PV.W,941; EG-NEXT: AND_INT * T2.W, PV.X, literal.x,942; EG-NEXT: -65536(nan), 0(0.000000e+00)943; EG-NEXT: OR_INT * T1.W, PS, PV.W,944; EG-NEXT: MOV T12.X, PV.W,945; EG-NEXT: MOV * T0.X, T13.X,946; EG-NEXT: LSHR * T1.W, T21.Y, literal.x,947; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)948; EG-NEXT: BCNT_INT T1.W, PV.W,949; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,950; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)951; EG-NEXT: LSHL * T1.W, PV.W, literal.x,952; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)953; EG-NEXT: OR_INT * T1.W, T2.W, PV.W,954; EG-NEXT: MOV * T13.X, PV.W,955; EG-NEXT: MOV T0.X, PV.X,956; EG-NEXT: AND_INT * T1.W, T21.Y, literal.x,957; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)958; EG-NEXT: BCNT_INT T1.W, PV.W,959; EG-NEXT: AND_INT * T2.W, PV.X, literal.x,960; EG-NEXT: -65536(nan), 0(0.000000e+00)961; EG-NEXT: OR_INT * T20.Y, PS, PV.W,962; EG-NEXT: MOV T13.X, PV.Y,963; EG-NEXT: MOV * T0.X, T16.X,964; EG-NEXT: LSHR * T1.W, T21.Z, literal.x,965; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)966; EG-NEXT: BCNT_INT T1.W, PV.W,967; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,968; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)969; EG-NEXT: LSHL * T1.W, PV.W, literal.x,970; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)971; EG-NEXT: OR_INT * T1.W, T2.W, PV.W,972; EG-NEXT: ALU clause starting at 131:973; EG-NEXT: MOV * T16.X, T1.W,974; EG-NEXT: MOV T0.X, PV.X,975; EG-NEXT: AND_INT * T1.W, T21.Z, literal.x,976; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)977; EG-NEXT: BCNT_INT T1.W, PV.W,978; EG-NEXT: AND_INT * T2.W, PV.X, literal.x,979; EG-NEXT: -65536(nan), 0(0.000000e+00)980; EG-NEXT: OR_INT * T1.W, PS, PV.W,981; EG-NEXT: MOV T16.X, PV.W,982; EG-NEXT: MOV * T0.X, T17.X,983; EG-NEXT: LSHR * T1.W, T21.W, literal.x,984; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)985; EG-NEXT: BCNT_INT T1.W, PV.W,986; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,987; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)988; EG-NEXT: LSHL * T1.W, PV.W, literal.x,989; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)990; EG-NEXT: OR_INT * T1.W, T2.W, PV.W,991; EG-NEXT: MOV * T17.X, PV.W,992; EG-NEXT: MOV T0.X, PV.X,993; EG-NEXT: AND_INT T1.W, T21.W, literal.x,994; EG-NEXT: LSHR * T21.X, KC0[2].Y, literal.y,995; EG-NEXT: 65535(9.183409e-41), 2(2.802597e-45)996; EG-NEXT: AND_INT T0.Z, PV.X, literal.x,997; EG-NEXT: BCNT_INT T1.W, PV.W,998; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.y,999; EG-NEXT: -65536(nan), 16(2.242078e-44)1000; EG-NEXT: LSHR T22.X, PS, literal.x,1001; EG-NEXT: OR_INT * T20.W, PV.Z, PV.W,1002; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1003; EG-NEXT: MOV T17.X, PV.W,1004; EG-NEXT: MOV * T0.X, T4.X,1005; EG-NEXT: MOV * T0.Z, T8.X,1006; EG-NEXT: MOV T20.X, T12.X,1007; EG-NEXT: MOV * T20.Z, T16.X, BS:VEC_120/SCL_2121008 %tid = call i32 @llvm.amdgcn.workitem.id.x()1009 %in.gep = getelementptr <16 x i16>, ptr addrspace(1) %in, i32 %tid1010 %val = load <16 x i16>, ptr addrspace(1) %in.gep, align 321011 %ctpop = call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %val) nounwind readnone1012 store <16 x i16> %ctpop, ptr addrspace(1) %out, align 321013 ret void1014}1015 1016define amdgpu_kernel void @v_ctpop_i16_add_inline_constant(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {1017; SI-LABEL: v_ctpop_i16_add_inline_constant:1018; SI: ; %bb.0:1019; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91020; SI-NEXT: s_mov_b32 s7, 0xf0001021; SI-NEXT: s_mov_b32 s10, 01022; SI-NEXT: s_mov_b32 s11, s71023; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v01024; SI-NEXT: s_waitcnt lgkmcnt(0)1025; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1026; SI-NEXT: v_mov_b32_e32 v1, 01027; SI-NEXT: buffer_load_ushort v0, v[0:1], s[8:11], 0 addr641028; SI-NEXT: s_mov_b32 s6, -11029; SI-NEXT: s_mov_b32 s4, s01030; SI-NEXT: s_mov_b32 s5, s11031; SI-NEXT: s_waitcnt vmcnt(0)1032; SI-NEXT: v_bcnt_u32_b32_e64 v0, v0, 41033; SI-NEXT: buffer_store_short v0, off, s[4:7], 01034; SI-NEXT: s_endpgm1035;1036; VI-LABEL: v_ctpop_i16_add_inline_constant:1037; VI: ; %bb.0:1038; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241039; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v01040; VI-NEXT: s_waitcnt lgkmcnt(0)1041; VI-NEXT: v_mov_b32_e32 v1, s31042; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01043; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1044; VI-NEXT: flat_load_ushort v0, v[0:1]1045; VI-NEXT: s_mov_b32 s3, 0xf0001046; VI-NEXT: s_mov_b32 s2, -11047; VI-NEXT: s_waitcnt vmcnt(0)1048; VI-NEXT: v_bcnt_u32_b32 v0, v0, 41049; VI-NEXT: buffer_store_short v0, off, s[0:3], 01050; VI-NEXT: s_endpgm1051;1052; EG-LABEL: v_ctpop_i16_add_inline_constant:1053; EG: ; %bb.0:1054; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[]1055; EG-NEXT: TEX 0 @61056; EG-NEXT: ALU 12, @10, KC0[CB0:0-32], KC1[]1057; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1058; EG-NEXT: CF_END1059; EG-NEXT: PAD1060; EG-NEXT: Fetch clause starting at 6:1061; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #11062; EG-NEXT: ALU clause starting at 8:1063; EG-NEXT: LSHL * T0.W, T0.X, 1,1064; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1065; EG-NEXT: ALU clause starting at 10:1066; EG-NEXT: BCNT_INT T0.W, T0.X,1067; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,1068; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1069; EG-NEXT: ADD_INT T0.W, PV.W, literal.x,1070; EG-NEXT: LSHL * T1.W, PS, literal.y,1071; EG-NEXT: 4(5.605194e-45), 3(4.203895e-45)1072; EG-NEXT: LSHL T0.X, PV.W, PS,1073; EG-NEXT: LSHL * T0.W, literal.x, PS,1074; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1075; EG-NEXT: MOV T0.Y, 0.0,1076; EG-NEXT: MOV * T0.Z, 0.0,1077; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1078; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1079 %tid = call i32 @llvm.amdgcn.workitem.id.x()1080 %in.gep = getelementptr i16, ptr addrspace(1) %in, i32 %tid1081 %val = load i16, ptr addrspace(1) %in.gep, align 41082 %ctpop = call i16 @llvm.ctpop.i16(i16 %val) nounwind readnone1083 %add = add i16 %ctpop, 41084 store i16 %add, ptr addrspace(1) %out, align 41085 ret void1086}1087 1088define amdgpu_kernel void @v_ctpop_i16_add_inline_constant_inv(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {1089; SI-LABEL: v_ctpop_i16_add_inline_constant_inv:1090; SI: ; %bb.0:1091; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91092; SI-NEXT: s_mov_b32 s7, 0xf0001093; SI-NEXT: s_mov_b32 s10, 01094; SI-NEXT: s_mov_b32 s11, s71095; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v01096; SI-NEXT: s_waitcnt lgkmcnt(0)1097; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1098; SI-NEXT: v_mov_b32_e32 v1, 01099; SI-NEXT: buffer_load_ushort v0, v[0:1], s[8:11], 0 addr641100; SI-NEXT: s_mov_b32 s6, -11101; SI-NEXT: s_mov_b32 s4, s01102; SI-NEXT: s_mov_b32 s5, s11103; SI-NEXT: s_waitcnt vmcnt(0)1104; SI-NEXT: v_bcnt_u32_b32_e64 v0, v0, 41105; SI-NEXT: buffer_store_short v0, off, s[4:7], 01106; SI-NEXT: s_endpgm1107;1108; VI-LABEL: v_ctpop_i16_add_inline_constant_inv:1109; VI: ; %bb.0:1110; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241111; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v01112; VI-NEXT: s_waitcnt lgkmcnt(0)1113; VI-NEXT: v_mov_b32_e32 v1, s31114; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01115; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1116; VI-NEXT: flat_load_ushort v0, v[0:1]1117; VI-NEXT: s_mov_b32 s3, 0xf0001118; VI-NEXT: s_mov_b32 s2, -11119; VI-NEXT: s_waitcnt vmcnt(0)1120; VI-NEXT: v_bcnt_u32_b32 v0, v0, 41121; VI-NEXT: buffer_store_short v0, off, s[0:3], 01122; VI-NEXT: s_endpgm1123;1124; EG-LABEL: v_ctpop_i16_add_inline_constant_inv:1125; EG: ; %bb.0:1126; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[]1127; EG-NEXT: TEX 0 @61128; EG-NEXT: ALU 12, @10, KC0[CB0:0-32], KC1[]1129; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1130; EG-NEXT: CF_END1131; EG-NEXT: PAD1132; EG-NEXT: Fetch clause starting at 6:1133; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #11134; EG-NEXT: ALU clause starting at 8:1135; EG-NEXT: LSHL * T0.W, T0.X, 1,1136; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1137; EG-NEXT: ALU clause starting at 10:1138; EG-NEXT: BCNT_INT T0.W, T0.X,1139; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,1140; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1141; EG-NEXT: ADD_INT T0.W, PV.W, literal.x,1142; EG-NEXT: LSHL * T1.W, PS, literal.y,1143; EG-NEXT: 4(5.605194e-45), 3(4.203895e-45)1144; EG-NEXT: LSHL T0.X, PV.W, PS,1145; EG-NEXT: LSHL * T0.W, literal.x, PS,1146; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1147; EG-NEXT: MOV T0.Y, 0.0,1148; EG-NEXT: MOV * T0.Z, 0.0,1149; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1150; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1151 %tid = call i32 @llvm.amdgcn.workitem.id.x()1152 %in.gep = getelementptr i16, ptr addrspace(1) %in, i32 %tid1153 %val = load i16, ptr addrspace(1) %in.gep, align 41154 %ctpop = call i16 @llvm.ctpop.i16(i16 %val) nounwind readnone1155 %add = add i16 4, %ctpop1156 store i16 %add, ptr addrspace(1) %out, align 41157 ret void1158}1159 1160define amdgpu_kernel void @v_ctpop_i16_add_literal(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {1161; SI-LABEL: v_ctpop_i16_add_literal:1162; SI: ; %bb.0:1163; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91164; SI-NEXT: s_mov_b32 s7, 0xf0001165; SI-NEXT: s_mov_b32 s10, 01166; SI-NEXT: s_mov_b32 s11, s71167; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v01168; SI-NEXT: s_waitcnt lgkmcnt(0)1169; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1170; SI-NEXT: v_mov_b32_e32 v1, 01171; SI-NEXT: buffer_load_ushort v0, v[0:1], s[8:11], 0 addr641172; SI-NEXT: s_mov_b32 s4, s01173; SI-NEXT: s_movk_i32 s0, 0x3e71174; SI-NEXT: s_mov_b32 s6, -11175; SI-NEXT: s_mov_b32 s5, s11176; SI-NEXT: s_waitcnt vmcnt(0)1177; SI-NEXT: v_bcnt_u32_b32_e64 v0, v0, s01178; SI-NEXT: buffer_store_short v0, off, s[4:7], 01179; SI-NEXT: s_endpgm1180;1181; VI-LABEL: v_ctpop_i16_add_literal:1182; VI: ; %bb.0:1183; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241184; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v01185; VI-NEXT: s_movk_i32 s4, 0x3e71186; VI-NEXT: s_waitcnt lgkmcnt(0)1187; VI-NEXT: v_mov_b32_e32 v1, s31188; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01189; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1190; VI-NEXT: flat_load_ushort v0, v[0:1]1191; VI-NEXT: s_mov_b32 s3, 0xf0001192; VI-NEXT: s_mov_b32 s2, -11193; VI-NEXT: s_waitcnt vmcnt(0)1194; VI-NEXT: v_bcnt_u32_b32 v0, v0, s41195; VI-NEXT: buffer_store_short v0, off, s[0:3], 01196; VI-NEXT: s_endpgm1197;1198; EG-LABEL: v_ctpop_i16_add_literal:1199; EG: ; %bb.0:1200; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[]1201; EG-NEXT: TEX 0 @61202; EG-NEXT: ALU 12, @10, KC0[CB0:0-32], KC1[]1203; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1204; EG-NEXT: CF_END1205; EG-NEXT: PAD1206; EG-NEXT: Fetch clause starting at 6:1207; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #11208; EG-NEXT: ALU clause starting at 8:1209; EG-NEXT: LSHL * T0.W, T0.X, 1,1210; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1211; EG-NEXT: ALU clause starting at 10:1212; EG-NEXT: BCNT_INT T0.W, T0.X,1213; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,1214; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1215; EG-NEXT: ADD_INT T0.W, PV.W, literal.x,1216; EG-NEXT: LSHL * T1.W, PS, literal.y,1217; EG-NEXT: 999(1.399897e-42), 3(4.203895e-45)1218; EG-NEXT: LSHL T0.X, PV.W, PS,1219; EG-NEXT: LSHL * T0.W, literal.x, PS,1220; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1221; EG-NEXT: MOV T0.Y, 0.0,1222; EG-NEXT: MOV * T0.Z, 0.0,1223; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1224; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1225 %tid = call i32 @llvm.amdgcn.workitem.id.x()1226 %in.gep = getelementptr i16, ptr addrspace(1) %in, i32 %tid1227 %val = load i16, ptr addrspace(1) %in.gep, align 41228 %ctpop = call i16 @llvm.ctpop.i16(i16 %val) nounwind readnone1229 %add = add i16 %ctpop, 9991230 store i16 %add, ptr addrspace(1) %out, align 41231 ret void1232}1233 1234define amdgpu_kernel void @v_ctpop_i16_add_var(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, i16 %const) nounwind {1235; SI-LABEL: v_ctpop_i16_add_var:1236; SI: ; %bb.0:1237; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91238; SI-NEXT: s_load_dword s12, s[4:5], 0xd1239; SI-NEXT: s_mov_b32 s7, 0xf0001240; SI-NEXT: s_mov_b32 s10, 01241; SI-NEXT: s_mov_b32 s11, s71242; SI-NEXT: s_waitcnt lgkmcnt(0)1243; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1244; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v01245; SI-NEXT: v_mov_b32_e32 v1, 01246; SI-NEXT: buffer_load_ushort v0, v[0:1], s[8:11], 0 addr641247; SI-NEXT: s_mov_b32 s6, -11248; SI-NEXT: s_mov_b32 s4, s01249; SI-NEXT: s_mov_b32 s5, s11250; SI-NEXT: s_waitcnt vmcnt(0)1251; SI-NEXT: v_bcnt_u32_b32_e64 v0, v0, s121252; SI-NEXT: buffer_store_short v0, off, s[4:7], 01253; SI-NEXT: s_endpgm1254;1255; VI-LABEL: v_ctpop_i16_add_var:1256; VI: ; %bb.0:1257; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241258; VI-NEXT: s_load_dword s4, s[4:5], 0x341259; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v01260; VI-NEXT: s_waitcnt lgkmcnt(0)1261; VI-NEXT: v_mov_b32_e32 v1, s31262; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01263; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1264; VI-NEXT: flat_load_ushort v0, v[0:1]1265; VI-NEXT: s_mov_b32 s3, 0xf0001266; VI-NEXT: s_mov_b32 s2, -11267; VI-NEXT: s_waitcnt vmcnt(0)1268; VI-NEXT: v_bcnt_u32_b32 v0, v0, s41269; VI-NEXT: buffer_store_short v0, off, s[0:3], 01270; VI-NEXT: s_endpgm1271;1272; EG-LABEL: v_ctpop_i16_add_var:1273; EG: ; %bb.0:1274; EG-NEXT: ALU 1, @12, KC0[CB0:0-32], KC1[]1275; EG-NEXT: TEX 0 @81276; EG-NEXT: ALU 0, @14, KC0[], KC1[]1277; EG-NEXT: TEX 0 @101278; EG-NEXT: ALU 13, @15, KC0[CB0:0-32], KC1[]1279; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1280; EG-NEXT: CF_END1281; EG-NEXT: PAD1282; EG-NEXT: Fetch clause starting at 8:1283; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #11284; EG-NEXT: Fetch clause starting at 10:1285; EG-NEXT: VTX_READ_16 T1.X, T1.X, 44, #31286; EG-NEXT: ALU clause starting at 12:1287; EG-NEXT: LSHL * T0.W, T0.X, 1,1288; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1289; EG-NEXT: ALU clause starting at 14:1290; EG-NEXT: MOV * T1.X, 0.0,1291; EG-NEXT: ALU clause starting at 15:1292; EG-NEXT: BCNT_INT T0.W, T0.X,1293; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,1294; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1295; EG-NEXT: ADD_INT * T0.W, PV.W, T1.X,1296; EG-NEXT: AND_INT T0.W, PV.W, literal.x,1297; EG-NEXT: LSHL * T1.W, T1.W, literal.y,1298; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)1299; EG-NEXT: LSHL T0.X, PV.W, PS,1300; EG-NEXT: LSHL * T0.W, literal.x, PS,1301; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1302; EG-NEXT: MOV T0.Y, 0.0,1303; EG-NEXT: MOV * T0.Z, 0.0,1304; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1305; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1306 %tid = call i32 @llvm.amdgcn.workitem.id.x()1307 %in.gep = getelementptr i16, ptr addrspace(1) %in, i32 %tid1308 %val = load i16, ptr addrspace(1) %in.gep, align 41309 %ctpop = call i16 @llvm.ctpop.i16(i16 %val) nounwind readnone1310 %add = add i16 %ctpop, %const1311 store i16 %add, ptr addrspace(1) %out, align 41312 ret void1313}1314 1315define amdgpu_kernel void @v_ctpop_i16_add_var_inv(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, i16 %const) nounwind {1316; SI-LABEL: v_ctpop_i16_add_var_inv:1317; SI: ; %bb.0:1318; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91319; SI-NEXT: s_load_dword s12, s[4:5], 0xd1320; SI-NEXT: s_mov_b32 s7, 0xf0001321; SI-NEXT: s_mov_b32 s10, 01322; SI-NEXT: s_mov_b32 s11, s71323; SI-NEXT: s_waitcnt lgkmcnt(0)1324; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1325; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v01326; SI-NEXT: v_mov_b32_e32 v1, 01327; SI-NEXT: buffer_load_ushort v0, v[0:1], s[8:11], 0 addr641328; SI-NEXT: s_mov_b32 s6, -11329; SI-NEXT: s_mov_b32 s4, s01330; SI-NEXT: s_mov_b32 s5, s11331; SI-NEXT: s_waitcnt vmcnt(0)1332; SI-NEXT: v_bcnt_u32_b32_e64 v0, v0, s121333; SI-NEXT: buffer_store_short v0, off, s[4:7], 01334; SI-NEXT: s_endpgm1335;1336; VI-LABEL: v_ctpop_i16_add_var_inv:1337; VI: ; %bb.0:1338; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241339; VI-NEXT: s_load_dword s4, s[4:5], 0x341340; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v01341; VI-NEXT: s_waitcnt lgkmcnt(0)1342; VI-NEXT: v_mov_b32_e32 v1, s31343; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01344; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1345; VI-NEXT: flat_load_ushort v0, v[0:1]1346; VI-NEXT: s_mov_b32 s3, 0xf0001347; VI-NEXT: s_mov_b32 s2, -11348; VI-NEXT: s_waitcnt vmcnt(0)1349; VI-NEXT: v_bcnt_u32_b32 v0, v0, s41350; VI-NEXT: buffer_store_short v0, off, s[0:3], 01351; VI-NEXT: s_endpgm1352;1353; EG-LABEL: v_ctpop_i16_add_var_inv:1354; EG: ; %bb.0:1355; EG-NEXT: ALU 1, @12, KC0[CB0:0-32], KC1[]1356; EG-NEXT: TEX 0 @81357; EG-NEXT: ALU 0, @14, KC0[], KC1[]1358; EG-NEXT: TEX 0 @101359; EG-NEXT: ALU 13, @15, KC0[CB0:0-32], KC1[]1360; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1361; EG-NEXT: CF_END1362; EG-NEXT: PAD1363; EG-NEXT: Fetch clause starting at 8:1364; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #11365; EG-NEXT: Fetch clause starting at 10:1366; EG-NEXT: VTX_READ_16 T1.X, T1.X, 44, #31367; EG-NEXT: ALU clause starting at 12:1368; EG-NEXT: LSHL * T0.W, T0.X, 1,1369; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1370; EG-NEXT: ALU clause starting at 14:1371; EG-NEXT: MOV * T1.X, 0.0,1372; EG-NEXT: ALU clause starting at 15:1373; EG-NEXT: BCNT_INT T0.W, T0.X,1374; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,1375; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1376; EG-NEXT: ADD_INT * T0.W, T1.X, PV.W,1377; EG-NEXT: AND_INT T0.W, PV.W, literal.x,1378; EG-NEXT: LSHL * T1.W, T1.W, literal.y,1379; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)1380; EG-NEXT: LSHL T0.X, PV.W, PS,1381; EG-NEXT: LSHL * T0.W, literal.x, PS,1382; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1383; EG-NEXT: MOV T0.Y, 0.0,1384; EG-NEXT: MOV * T0.Z, 0.0,1385; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1386; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1387 %tid = call i32 @llvm.amdgcn.workitem.id.x()1388 %in.gep = getelementptr i16, ptr addrspace(1) %in, i32 %tid1389 %val = load i16, ptr addrspace(1) %in.gep, align 41390 %ctpop = call i16 @llvm.ctpop.i16(i16 %val) nounwind readnone1391 %add = add i16 %const, %ctpop1392 store i16 %add, ptr addrspace(1) %out, align 41393 ret void1394}1395 1396define amdgpu_kernel void @v_ctpop_i16_add_vvar_inv(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, ptr addrspace(1) noalias %constptr) nounwind {1397; SI-LABEL: v_ctpop_i16_add_vvar_inv:1398; SI: ; %bb.0:1399; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91400; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd1401; SI-NEXT: s_mov_b32 s11, 0xf0001402; SI-NEXT: s_mov_b32 s14, 01403; SI-NEXT: s_mov_b32 s15, s111404; SI-NEXT: s_waitcnt lgkmcnt(0)1405; SI-NEXT: s_mov_b64 s[12:13], s[2:3]1406; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v01407; SI-NEXT: v_mov_b32_e32 v1, 01408; SI-NEXT: s_mov_b64 s[6:7], s[14:15]1409; SI-NEXT: buffer_load_ushort v2, v[0:1], s[12:15], 0 addr641410; SI-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr641411; SI-NEXT: s_mov_b32 s10, -11412; SI-NEXT: s_mov_b32 s8, s01413; SI-NEXT: s_mov_b32 s9, s11414; SI-NEXT: s_waitcnt vmcnt(0)1415; SI-NEXT: v_bcnt_u32_b32_e32 v0, v2, v01416; SI-NEXT: buffer_store_short v0, off, s[8:11], 01417; SI-NEXT: s_endpgm1418;1419; VI-LABEL: v_ctpop_i16_add_vvar_inv:1420; VI: ; %bb.0:1421; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241422; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341423; VI-NEXT: v_lshlrev_b32_e32 v2, 1, v01424; VI-NEXT: s_waitcnt lgkmcnt(0)1425; VI-NEXT: v_mov_b32_e32 v1, s31426; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v21427; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1428; VI-NEXT: flat_load_ushort v3, v[0:1]1429; VI-NEXT: v_mov_b32_e32 v1, s51430; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v21431; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1432; VI-NEXT: flat_load_ushort v0, v[0:1]1433; VI-NEXT: s_mov_b32 s3, 0xf0001434; VI-NEXT: s_mov_b32 s2, -11435; VI-NEXT: s_waitcnt vmcnt(0)1436; VI-NEXT: v_bcnt_u32_b32 v0, v3, v01437; VI-NEXT: buffer_store_short v0, off, s[0:3], 01438; VI-NEXT: s_endpgm1439;1440; EG-LABEL: v_ctpop_i16_add_vvar_inv:1441; EG: ; %bb.0:1442; EG-NEXT: ALU 1, @12, KC0[CB0:0-32], KC1[]1443; EG-NEXT: TEX 0 @81444; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]1445; EG-NEXT: TEX 0 @101446; EG-NEXT: ALU 13, @15, KC0[CB0:0-32], KC1[]1447; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1448; EG-NEXT: CF_END1449; EG-NEXT: PAD1450; EG-NEXT: Fetch clause starting at 8:1451; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #11452; EG-NEXT: Fetch clause starting at 10:1453; EG-NEXT: VTX_READ_16 T1.X, T1.X, 0, #11454; EG-NEXT: ALU clause starting at 12:1455; EG-NEXT: LSHL * T0.W, T0.X, 1,1456; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1457; EG-NEXT: ALU clause starting at 14:1458; EG-NEXT: ADD_INT * T1.X, KC0[2].W, T0.W,1459; EG-NEXT: ALU clause starting at 15:1460; EG-NEXT: BCNT_INT T0.W, T0.X,1461; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,1462; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1463; EG-NEXT: ADD_INT * T0.W, T1.X, PV.W,1464; EG-NEXT: AND_INT T0.W, PV.W, literal.x,1465; EG-NEXT: LSHL * T1.W, T1.W, literal.y,1466; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)1467; EG-NEXT: LSHL T0.X, PV.W, PS,1468; EG-NEXT: LSHL * T0.W, literal.x, PS,1469; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1470; EG-NEXT: MOV T0.Y, 0.0,1471; EG-NEXT: MOV * T0.Z, 0.0,1472; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1473; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1474 %tid = call i32 @llvm.amdgcn.workitem.id.x()1475 %in.gep = getelementptr i16, ptr addrspace(1) %in, i32 %tid1476 %val = load i16, ptr addrspace(1) %in.gep, align 41477 %ctpop = call i16 @llvm.ctpop.i16(i16 %val) nounwind readnone1478 %gep = getelementptr i16, ptr addrspace(1) %constptr, i32 %tid1479 %const = load i16, ptr addrspace(1) %gep, align 41480 %add = add i16 %const, %ctpop1481 store i16 %add, ptr addrspace(1) %out, align 41482 ret void1483}1484 1485; FIXME: We currently disallow SALU instructions in all branches,1486; but there are some cases when the should be allowed.1487define amdgpu_kernel void @ctpop_i16_in_br(ptr addrspace(1) %out, ptr addrspace(1) %in, i16 %ctpop_arg, i16 %cond) {1488; SI-LABEL: ctpop_i16_in_br:1489; SI: ; %bb.0: ; %entry1490; SI-NEXT: s_load_dword s6, s[4:5], 0xd1491; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91492; SI-NEXT: s_waitcnt lgkmcnt(0)1493; SI-NEXT: s_lshr_b32 s4, s6, 161494; SI-NEXT: s_cbranch_scc0 .LBB14_41495; SI-NEXT: ; %bb.1: ; %else1496; SI-NEXT: s_mov_b32 s11, 0xf0001497; SI-NEXT: s_mov_b32 s10, -11498; SI-NEXT: s_mov_b32 s8, s21499; SI-NEXT: s_mov_b32 s9, s31500; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 offset:21501; SI-NEXT: s_cbranch_execnz .LBB14_31502; SI-NEXT: .LBB14_2: ; %if1503; SI-NEXT: s_and_b32 s2, s6, 0xffff1504; SI-NEXT: s_bcnt1_i32_b32 s2, s21505; SI-NEXT: s_waitcnt vmcnt(0)1506; SI-NEXT: v_mov_b32_e32 v0, s21507; SI-NEXT: .LBB14_3: ; %endif1508; SI-NEXT: s_mov_b32 s3, 0xf0001509; SI-NEXT: s_mov_b32 s2, -11510; SI-NEXT: s_waitcnt vmcnt(0)1511; SI-NEXT: buffer_store_short v0, off, s[0:3], 01512; SI-NEXT: s_endpgm1513; SI-NEXT: .LBB14_4:1514; SI-NEXT: ; implicit-def: $vgpr01515; SI-NEXT: s_branch .LBB14_21516;1517; VI-LABEL: ctpop_i16_in_br:1518; VI: ; %bb.0: ; %entry1519; VI-NEXT: s_load_dword s6, s[4:5], 0x341520; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241521; VI-NEXT: s_waitcnt lgkmcnt(0)1522; VI-NEXT: s_lshr_b32 s4, s6, 161523; VI-NEXT: s_cbranch_scc0 .LBB14_41524; VI-NEXT: ; %bb.1: ; %else1525; VI-NEXT: s_mov_b32 s11, 0xf0001526; VI-NEXT: s_mov_b32 s10, -11527; VI-NEXT: s_mov_b32 s8, s21528; VI-NEXT: s_mov_b32 s9, s31529; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 offset:21530; VI-NEXT: s_cbranch_execnz .LBB14_31531; VI-NEXT: .LBB14_2: ; %if1532; VI-NEXT: s_and_b32 s2, s6, 0xffff1533; VI-NEXT: s_bcnt1_i32_b32 s2, s21534; VI-NEXT: s_waitcnt vmcnt(0)1535; VI-NEXT: v_mov_b32_e32 v0, s21536; VI-NEXT: .LBB14_3: ; %endif1537; VI-NEXT: s_mov_b32 s3, 0xf0001538; VI-NEXT: s_mov_b32 s2, -11539; VI-NEXT: s_waitcnt vmcnt(0)1540; VI-NEXT: buffer_store_short v0, off, s[0:3], 01541; VI-NEXT: s_endpgm1542; VI-NEXT: .LBB14_4:1543; VI-NEXT: ; implicit-def: $vgpr01544; VI-NEXT: s_branch .LBB14_21545;1546; EG-LABEL: ctpop_i16_in_br:1547; EG: ; %bb.0: ; %entry1548; EG-NEXT: ALU 0, @20, KC0[], KC1[]1549; EG-NEXT: TEX 0 @141550; EG-NEXT: ALU_PUSH_BEFORE 3, @21, KC0[], KC1[]1551; EG-NEXT: JUMP @7 POP:11552; EG-NEXT: ALU 0, @25, KC0[CB0:0-32], KC1[]1553; EG-NEXT: TEX 0 @161554; EG-NEXT: ALU_POP_AFTER 1, @26, KC0[], KC1[]1555; EG-NEXT: ALU_PUSH_BEFORE 2, @28, KC0[CB0:0-32], KC1[]1556; EG-NEXT: JUMP @11 POP:11557; EG-NEXT: TEX 0 @181558; EG-NEXT: ALU_POP_AFTER 0, @31, KC0[], KC1[]1559; EG-NEXT: ALU 11, @32, KC0[], KC1[]1560; EG-NEXT: MEM_RAT MSKOR T1.XW, T0.X1561; EG-NEXT: CF_END1562; EG-NEXT: Fetch clause starting at 14:1563; EG-NEXT: VTX_READ_16 T1.X, T0.X, 46, #31564; EG-NEXT: Fetch clause starting at 16:1565; EG-NEXT: VTX_READ_16 T1.X, T1.X, 2, #11566; EG-NEXT: Fetch clause starting at 18:1567; EG-NEXT: VTX_READ_16 T0.X, T0.X, 44, #31568; EG-NEXT: ALU clause starting at 20:1569; EG-NEXT: MOV * T0.X, 0.0,1570; EG-NEXT: ALU clause starting at 21:1571; EG-NEXT: MOV T1.W, literal.x,1572; EG-NEXT: SETNE_INT * T0.W, T1.X, 0.0,1573; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)1574; EG-NEXT: PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PS, 0.0,1575; EG-NEXT: ALU clause starting at 25:1576; EG-NEXT: MOV * T1.X, KC0[2].Z,1577; EG-NEXT: ALU clause starting at 26:1578; EG-NEXT: MOV * T1.W, literal.x,1579; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)1580; EG-NEXT: ALU clause starting at 28:1581; EG-NEXT: MOV T0.W, KC0[2].Y,1582; EG-NEXT: SETE_INT * T1.W, T1.W, 0.0,1583; EG-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PS, 0.0,1584; EG-NEXT: ALU clause starting at 31:1585; EG-NEXT: BCNT_INT * T1.X, T0.X,1586; EG-NEXT: ALU clause starting at 32:1587; EG-NEXT: LSHL * T1.W, T0.W, literal.x,1588; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1589; EG-NEXT: AND_INT T1.W, PV.W, literal.x,1590; EG-NEXT: AND_INT * T2.W, T1.X, literal.y,1591; EG-NEXT: 24(3.363116e-44), 65535(9.183409e-41)1592; EG-NEXT: LSHL T1.X, PS, PV.W,1593; EG-NEXT: LSHL * T1.W, literal.x, PV.W,1594; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1595; EG-NEXT: MOV T1.Y, 0.0,1596; EG-NEXT: MOV * T1.Z, 0.0,1597; EG-NEXT: LSHR * T0.X, T0.W, literal.x,1598; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1599entry:1600 %tmp0 = icmp eq i16 %cond, 01601 br i1 %tmp0, label %if, label %else1602 1603if:1604 %tmp2 = call i16 @llvm.ctpop.i16(i16 %ctpop_arg)1605 br label %endif1606 1607else:1608 %tmp3 = getelementptr i16, ptr addrspace(1) %in, i16 11609 %tmp4 = load i16, ptr addrspace(1) %tmp31610 br label %endif1611 1612endif:1613 %tmp5 = phi i16 [%tmp2, %if], [%tmp4, %else]1614 store i16 %tmp5, ptr addrspace(1) %out1615 ret void1616}1617