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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=amdgcn | FileCheck %s -enable-var-scope --check-prefix=SI3; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck %s -enable-var-scope --check-prefix=VI4; RUN: llc < %s -mtriple=r600 -mcpu=cypress | FileCheck %s -enable-var-scope --check-prefix=EG5; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 | FileCheck %s -enable-var-scope --check-prefix=GFX106; RUN: llc < %s -global-isel -mtriple=amdgcn -mcpu=gfx1010 | FileCheck %s -enable-var-scope --check-prefix=GFX10-GISEL7 8declare i7 @llvm.cttz.i7(i7, i1) nounwind readnone9declare i8 @llvm.cttz.i8(i8, i1) nounwind readnone10declare i16 @llvm.cttz.i16(i16, i1) nounwind readnone11 12declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone13declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1) nounwind readnone14declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1) nounwind readnone15 16declare i64 @llvm.cttz.i64(i64, i1) nounwind readnone17declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1) nounwind readnone18declare <4 x i64> @llvm.cttz.v4i64(<4 x i64>, i1) nounwind readnone19 20declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone21 22define amdgpu_kernel void @s_cttz_i32(ptr addrspace(1) noalias %out, i32 %val) nounwind {23; SI-LABEL: s_cttz_i32:24; SI: ; %bb.0:25; SI-NEXT: s_load_dword s2, s[4:5], 0xb26; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x927; SI-NEXT: s_mov_b32 s3, 0xf00028; SI-NEXT: s_waitcnt lgkmcnt(0)29; SI-NEXT: s_ff1_i32_b32 s2, s230; SI-NEXT: s_min_u32 s4, s2, 3231; SI-NEXT: s_mov_b32 s2, -132; SI-NEXT: v_mov_b32_e32 v0, s433; SI-NEXT: buffer_store_dword v0, off, s[0:3], 034; SI-NEXT: s_endpgm35;36; VI-LABEL: s_cttz_i32:37; VI: ; %bb.0:38; VI-NEXT: s_load_dword s6, s[4:5], 0x2c39; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2440; VI-NEXT: s_mov_b32 s3, 0xf00041; VI-NEXT: s_mov_b32 s2, -142; VI-NEXT: s_waitcnt lgkmcnt(0)43; VI-NEXT: s_ff1_i32_b32 s4, s644; VI-NEXT: s_min_u32 s4, s4, 3245; VI-NEXT: v_mov_b32_e32 v0, s446; VI-NEXT: buffer_store_dword v0, off, s[0:3], 047; VI-NEXT: s_endpgm48;49; EG-LABEL: s_cttz_i32:50; EG: ; %bb.0:51; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]52; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 153; EG-NEXT: CF_END54; EG-NEXT: PAD55; EG-NEXT: ALU clause starting at 4:56; EG-NEXT: FFBL_INT * T0.W, KC0[2].Z,57; EG-NEXT: CNDE_INT T0.X, KC0[2].Z, literal.x, PV.W,58; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,59; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45)60;61; GFX10-LABEL: s_cttz_i32:62; GFX10: ; %bb.0:63; GFX10-NEXT: s_clause 0x164; GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c65; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2466; GFX10-NEXT: v_mov_b32_e32 v0, 067; GFX10-NEXT: s_waitcnt lgkmcnt(0)68; GFX10-NEXT: s_ff1_i32_b32 s2, s269; GFX10-NEXT: s_min_u32 s2, s2, 3270; GFX10-NEXT: v_mov_b32_e32 v1, s271; GFX10-NEXT: global_store_dword v0, v1, s[0:1]72; GFX10-NEXT: s_endpgm73;74; GFX10-GISEL-LABEL: s_cttz_i32:75; GFX10-GISEL: ; %bb.0:76; GFX10-GISEL-NEXT: s_clause 0x177; GFX10-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c78; GFX10-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2479; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 080; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)81; GFX10-GISEL-NEXT: s_ff1_i32_b32 s2, s282; GFX10-GISEL-NEXT: s_min_u32 s2, s2, 3283; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s284; GFX10-GISEL-NEXT: global_store_dword v1, v0, s[0:1]85; GFX10-GISEL-NEXT: s_endpgm86 %cttz = call i32 @llvm.cttz.i32(i32 %val, i1 false) nounwind readnone87 store i32 %cttz, ptr addrspace(1) %out, align 488 ret void89}90 91define amdgpu_kernel void @v_cttz_i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {92; SI-LABEL: v_cttz_i32:93; SI: ; %bb.0:94; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x995; SI-NEXT: s_mov_b32 s7, 0xf00096; SI-NEXT: s_mov_b32 s10, 097; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v098; SI-NEXT: v_mov_b32_e32 v1, 099; SI-NEXT: s_mov_b32 s11, s7100; SI-NEXT: s_waitcnt lgkmcnt(0)101; SI-NEXT: s_mov_b64 s[8:9], s[2:3]102; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64103; SI-NEXT: s_mov_b32 s6, -1104; SI-NEXT: s_mov_b32 s4, s0105; SI-NEXT: s_mov_b32 s5, s1106; SI-NEXT: s_waitcnt vmcnt(0)107; SI-NEXT: v_ffbl_b32_e32 v0, v0108; SI-NEXT: v_min_u32_e32 v0, 32, v0109; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0110; SI-NEXT: s_endpgm111;112; VI-LABEL: v_cttz_i32:113; VI: ; %bb.0:114; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24115; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0116; VI-NEXT: s_waitcnt lgkmcnt(0)117; VI-NEXT: v_mov_b32_e32 v1, s3118; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0119; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc120; VI-NEXT: flat_load_dword v0, v[0:1]121; VI-NEXT: s_mov_b32 s3, 0xf000122; VI-NEXT: s_mov_b32 s2, -1123; VI-NEXT: s_waitcnt vmcnt(0)124; VI-NEXT: v_ffbl_b32_e32 v0, v0125; VI-NEXT: v_min_u32_e32 v0, 32, v0126; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0127; VI-NEXT: s_endpgm128;129; EG-LABEL: v_cttz_i32:130; EG: ; %bb.0:131; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]132; EG-NEXT: TEX 0 @6133; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[]134; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1135; EG-NEXT: CF_END136; EG-NEXT: PAD137; EG-NEXT: Fetch clause starting at 6:138; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1139; EG-NEXT: ALU clause starting at 8:140; EG-NEXT: LSHL * T0.W, T0.X, literal.x,141; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)142; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,143; EG-NEXT: ALU clause starting at 11:144; EG-NEXT: FFBL_INT * T0.W, T0.X,145; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W,146; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,147; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45)148;149; GFX10-LABEL: v_cttz_i32:150; GFX10: ; %bb.0:151; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24152; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0153; GFX10-NEXT: v_mov_b32_e32 v1, 0154; GFX10-NEXT: s_waitcnt lgkmcnt(0)155; GFX10-NEXT: global_load_dword v0, v0, s[2:3]156; GFX10-NEXT: s_waitcnt vmcnt(0)157; GFX10-NEXT: v_ffbl_b32_e32 v0, v0158; GFX10-NEXT: v_min_u32_e32 v0, 32, v0159; GFX10-NEXT: global_store_dword v1, v0, s[0:1]160; GFX10-NEXT: s_endpgm161;162; GFX10-GISEL-LABEL: v_cttz_i32:163; GFX10-GISEL: ; %bb.0:164; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24165; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0166; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0167; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)168; GFX10-GISEL-NEXT: global_load_dword v0, v0, s[2:3]169; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)170; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v0, v0171; GFX10-GISEL-NEXT: v_min_u32_e32 v0, 32, v0172; GFX10-GISEL-NEXT: global_store_dword v1, v0, s[0:1]173; GFX10-GISEL-NEXT: s_endpgm174 %tid = call i32 @llvm.amdgcn.workitem.id.x()175 %in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid176 %val = load i32, ptr addrspace(1) %in.gep, align 4177 %cttz = call i32 @llvm.cttz.i32(i32 %val, i1 false) nounwind readnone178 store i32 %cttz, ptr addrspace(1) %out, align 4179 ret void180}181 182define amdgpu_kernel void @v_cttz_v2i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {183; SI-LABEL: v_cttz_v2i32:184; SI: ; %bb.0:185; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9186; SI-NEXT: s_mov_b32 s7, 0xf000187; SI-NEXT: s_mov_b32 s10, 0188; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0189; SI-NEXT: v_mov_b32_e32 v1, 0190; SI-NEXT: s_mov_b32 s11, s7191; SI-NEXT: s_waitcnt lgkmcnt(0)192; SI-NEXT: s_mov_b64 s[8:9], s[2:3]193; SI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[8:11], 0 addr64194; SI-NEXT: s_mov_b32 s6, -1195; SI-NEXT: s_mov_b32 s4, s0196; SI-NEXT: s_mov_b32 s5, s1197; SI-NEXT: s_waitcnt vmcnt(0)198; SI-NEXT: v_ffbl_b32_e32 v1, v1199; SI-NEXT: v_ffbl_b32_e32 v0, v0200; SI-NEXT: v_min_u32_e32 v1, 32, v1201; SI-NEXT: v_min_u32_e32 v0, 32, v0202; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0203; SI-NEXT: s_endpgm204;205; VI-LABEL: v_cttz_v2i32:206; VI: ; %bb.0:207; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24208; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0209; VI-NEXT: s_waitcnt lgkmcnt(0)210; VI-NEXT: v_mov_b32_e32 v1, s3211; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0212; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc213; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]214; VI-NEXT: s_mov_b32 s3, 0xf000215; VI-NEXT: s_mov_b32 s2, -1216; VI-NEXT: s_waitcnt vmcnt(0)217; VI-NEXT: v_ffbl_b32_e32 v1, v1218; VI-NEXT: v_ffbl_b32_e32 v0, v0219; VI-NEXT: v_min_u32_e32 v1, 32, v1220; VI-NEXT: v_min_u32_e32 v0, 32, v0221; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0222; VI-NEXT: s_endpgm223;224; EG-LABEL: v_cttz_v2i32:225; EG: ; %bb.0:226; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]227; EG-NEXT: TEX 0 @6228; EG-NEXT: ALU 6, @11, KC0[CB0:0-32], KC1[]229; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1230; EG-NEXT: CF_END231; EG-NEXT: PAD232; EG-NEXT: Fetch clause starting at 6:233; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1234; EG-NEXT: ALU clause starting at 8:235; EG-NEXT: LSHL * T0.W, T0.X, literal.x,236; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)237; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,238; EG-NEXT: ALU clause starting at 11:239; EG-NEXT: FFBL_INT * T0.W, T0.Y,240; EG-NEXT: CNDE_INT T0.Y, T0.Y, literal.x, PV.W,241; EG-NEXT: FFBL_INT * T0.W, T0.X,242; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)243; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W,244; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,245; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45)246;247; GFX10-LABEL: v_cttz_v2i32:248; GFX10: ; %bb.0:249; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24250; GFX10-NEXT: v_lshlrev_b32_e32 v0, 3, v0251; GFX10-NEXT: v_mov_b32_e32 v2, 0252; GFX10-NEXT: s_waitcnt lgkmcnt(0)253; GFX10-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3]254; GFX10-NEXT: s_waitcnt vmcnt(0)255; GFX10-NEXT: v_ffbl_b32_e32 v1, v1256; GFX10-NEXT: v_ffbl_b32_e32 v0, v0257; GFX10-NEXT: v_min_u32_e32 v1, 32, v1258; GFX10-NEXT: v_min_u32_e32 v0, 32, v0259; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]260; GFX10-NEXT: s_endpgm261;262; GFX10-GISEL-LABEL: v_cttz_v2i32:263; GFX10-GISEL: ; %bb.0:264; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24265; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v0, 3, v0266; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0267; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)268; GFX10-GISEL-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3]269; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)270; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v0, v0271; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v1, v1272; GFX10-GISEL-NEXT: v_min_u32_e32 v0, 32, v0273; GFX10-GISEL-NEXT: v_min_u32_e32 v1, 32, v1274; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]275; GFX10-GISEL-NEXT: s_endpgm276 %tid = call i32 @llvm.amdgcn.workitem.id.x()277 %in.gep = getelementptr <2 x i32>, ptr addrspace(1) %valptr, i32 %tid278 %val = load <2 x i32>, ptr addrspace(1) %in.gep, align 8279 %cttz = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %val, i1 false) nounwind readnone280 store <2 x i32> %cttz, ptr addrspace(1) %out, align 8281 ret void282}283 284define amdgpu_kernel void @v_cttz_v4i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {285; SI-LABEL: v_cttz_v4i32:286; SI: ; %bb.0:287; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9288; SI-NEXT: s_mov_b32 s7, 0xf000289; SI-NEXT: s_mov_b32 s10, 0290; SI-NEXT: v_lshlrev_b32_e32 v0, 4, v0291; SI-NEXT: v_mov_b32_e32 v1, 0292; SI-NEXT: s_mov_b32 s11, s7293; SI-NEXT: s_waitcnt lgkmcnt(0)294; SI-NEXT: s_mov_b64 s[8:9], s[2:3]295; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64296; SI-NEXT: s_mov_b32 s6, -1297; SI-NEXT: s_mov_b32 s4, s0298; SI-NEXT: s_mov_b32 s5, s1299; SI-NEXT: s_waitcnt vmcnt(0)300; SI-NEXT: v_ffbl_b32_e32 v3, v3301; SI-NEXT: v_ffbl_b32_e32 v2, v2302; SI-NEXT: v_ffbl_b32_e32 v1, v1303; SI-NEXT: v_ffbl_b32_e32 v0, v0304; SI-NEXT: v_min_u32_e32 v3, 32, v3305; SI-NEXT: v_min_u32_e32 v2, 32, v2306; SI-NEXT: v_min_u32_e32 v1, 32, v1307; SI-NEXT: v_min_u32_e32 v0, 32, v0308; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0309; SI-NEXT: s_endpgm310;311; VI-LABEL: v_cttz_v4i32:312; VI: ; %bb.0:313; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24314; VI-NEXT: v_lshlrev_b32_e32 v0, 4, v0315; VI-NEXT: s_waitcnt lgkmcnt(0)316; VI-NEXT: v_mov_b32_e32 v1, s3317; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0318; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc319; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]320; VI-NEXT: s_mov_b32 s3, 0xf000321; VI-NEXT: s_mov_b32 s2, -1322; VI-NEXT: s_waitcnt vmcnt(0)323; VI-NEXT: v_ffbl_b32_e32 v3, v3324; VI-NEXT: v_ffbl_b32_e32 v2, v2325; VI-NEXT: v_ffbl_b32_e32 v1, v1326; VI-NEXT: v_ffbl_b32_e32 v0, v0327; VI-NEXT: v_min_u32_e32 v3, 32, v3328; VI-NEXT: v_min_u32_e32 v2, 32, v2329; VI-NEXT: v_min_u32_e32 v1, 32, v1330; VI-NEXT: v_min_u32_e32 v0, 32, v0331; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0332; VI-NEXT: s_endpgm333;334; EG-LABEL: v_cttz_v4i32:335; EG: ; %bb.0:336; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]337; EG-NEXT: TEX 0 @6338; EG-NEXT: ALU 12, @11, KC0[CB0:0-32], KC1[]339; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1340; EG-NEXT: CF_END341; EG-NEXT: PAD342; EG-NEXT: Fetch clause starting at 6:343; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1344; EG-NEXT: ALU clause starting at 8:345; EG-NEXT: LSHL * T0.W, T0.X, literal.x,346; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)347; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,348; EG-NEXT: ALU clause starting at 11:349; EG-NEXT: FFBL_INT * T1.W, T0.W,350; EG-NEXT: FFBL_INT T2.W, T0.Z,351; EG-NEXT: CNDE_INT * T0.W, T0.W, literal.x, PV.W, BS:VEC_021/SCL_122352; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)353; EG-NEXT: CNDE_INT T0.Z, T0.Z, literal.x, PV.W,354; EG-NEXT: FFBL_INT * T1.W, T0.Y,355; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)356; EG-NEXT: CNDE_INT T0.Y, T0.Y, literal.x, PV.W,357; EG-NEXT: FFBL_INT * T1.W, T0.X,358; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)359; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W,360; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,361; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45)362;363; GFX10-LABEL: v_cttz_v4i32:364; GFX10: ; %bb.0:365; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24366; GFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0367; GFX10-NEXT: v_mov_b32_e32 v4, 0368; GFX10-NEXT: s_waitcnt lgkmcnt(0)369; GFX10-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3]370; GFX10-NEXT: s_waitcnt vmcnt(0)371; GFX10-NEXT: v_ffbl_b32_e32 v3, v3372; GFX10-NEXT: v_ffbl_b32_e32 v2, v2373; GFX10-NEXT: v_ffbl_b32_e32 v1, v1374; GFX10-NEXT: v_ffbl_b32_e32 v0, v0375; GFX10-NEXT: v_min_u32_e32 v3, 32, v3376; GFX10-NEXT: v_min_u32_e32 v2, 32, v2377; GFX10-NEXT: v_min_u32_e32 v1, 32, v1378; GFX10-NEXT: v_min_u32_e32 v0, 32, v0379; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]380; GFX10-NEXT: s_endpgm381;382; GFX10-GISEL-LABEL: v_cttz_v4i32:383; GFX10-GISEL: ; %bb.0:384; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24385; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v0, 4, v0386; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0387; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)388; GFX10-GISEL-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3]389; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)390; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v0, v0391; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v1, v1392; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v2, v2393; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v3, v3394; GFX10-GISEL-NEXT: v_min_u32_e32 v0, 32, v0395; GFX10-GISEL-NEXT: v_min_u32_e32 v1, 32, v1396; GFX10-GISEL-NEXT: v_min_u32_e32 v2, 32, v2397; GFX10-GISEL-NEXT: v_min_u32_e32 v3, 32, v3398; GFX10-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]399; GFX10-GISEL-NEXT: s_endpgm400 %tid = call i32 @llvm.amdgcn.workitem.id.x()401 %in.gep = getelementptr <4 x i32>, ptr addrspace(1) %valptr, i32 %tid402 %val = load <4 x i32>, ptr addrspace(1) %in.gep, align 16403 %cttz = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %val, i1 false) nounwind readnone404 store <4 x i32> %cttz, ptr addrspace(1) %out, align 16405 ret void406}407 408define amdgpu_kernel void @v_cttz_i8(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {409; SI-LABEL: v_cttz_i8:410; SI: ; %bb.0:411; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9412; SI-NEXT: s_mov_b32 s7, 0xf000413; SI-NEXT: s_mov_b32 s6, -1414; SI-NEXT: s_mov_b32 s10, s6415; SI-NEXT: s_mov_b32 s11, s7416; SI-NEXT: s_waitcnt lgkmcnt(0)417; SI-NEXT: s_mov_b32 s8, s2418; SI-NEXT: s_mov_b32 s9, s3419; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0420; SI-NEXT: s_mov_b32 s4, s0421; SI-NEXT: s_mov_b32 s5, s1422; SI-NEXT: s_waitcnt vmcnt(0)423; SI-NEXT: v_or_b32_e32 v0, 0x100, v0424; SI-NEXT: v_ffbl_b32_e32 v0, v0425; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0426; SI-NEXT: s_endpgm427;428; VI-LABEL: v_cttz_i8:429; VI: ; %bb.0:430; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24431; VI-NEXT: s_mov_b32 s7, 0xf000432; VI-NEXT: s_mov_b32 s6, -1433; VI-NEXT: s_mov_b32 s10, s6434; VI-NEXT: s_mov_b32 s11, s7435; VI-NEXT: s_waitcnt lgkmcnt(0)436; VI-NEXT: s_mov_b32 s8, s2437; VI-NEXT: s_mov_b32 s9, s3438; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0439; VI-NEXT: s_mov_b32 s4, s0440; VI-NEXT: s_mov_b32 s5, s1441; VI-NEXT: s_waitcnt vmcnt(0)442; VI-NEXT: v_or_b32_e32 v0, 0x100, v0443; VI-NEXT: v_ffbl_b32_e32 v0, v0444; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0445; VI-NEXT: s_endpgm446;447; EG-LABEL: v_cttz_i8:448; EG: ; %bb.0:449; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]450; EG-NEXT: TEX 0 @6451; EG-NEXT: ALU 14, @9, KC0[CB0:0-32], KC1[]452; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X453; EG-NEXT: CF_END454; EG-NEXT: PAD455; EG-NEXT: Fetch clause starting at 6:456; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1457; EG-NEXT: ALU clause starting at 8:458; EG-NEXT: MOV * T0.X, KC0[2].Z,459; EG-NEXT: ALU clause starting at 9:460; EG-NEXT: OR_INT * T0.W, T0.X, literal.x,461; EG-NEXT: 256(3.587324e-43), 0(0.000000e+00)462; EG-NEXT: FFBL_INT T0.W, PV.W,463; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,464; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)465; EG-NEXT: AND_INT T0.W, PV.W, literal.x,466; EG-NEXT: LSHL * T1.W, PS, literal.y,467; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)468; EG-NEXT: LSHL T0.X, PV.W, PS,469; EG-NEXT: LSHL * T0.W, literal.x, PS,470; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)471; EG-NEXT: MOV T0.Y, 0.0,472; EG-NEXT: MOV * T0.Z, 0.0,473; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,474; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)475;476; GFX10-LABEL: v_cttz_i8:477; GFX10: ; %bb.0:478; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24479; GFX10-NEXT: v_mov_b32_e32 v0, 0480; GFX10-NEXT: s_waitcnt lgkmcnt(0)481; GFX10-NEXT: global_load_ubyte v1, v0, s[2:3]482; GFX10-NEXT: s_waitcnt vmcnt(0)483; GFX10-NEXT: v_or_b32_e32 v1, 0x100, v1484; GFX10-NEXT: v_ffbl_b32_e32 v1, v1485; GFX10-NEXT: global_store_byte v0, v1, s[0:1]486; GFX10-NEXT: s_endpgm487;488; GFX10-GISEL-LABEL: v_cttz_i8:489; GFX10-GISEL: ; %bb.0:490; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24491; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, 0492; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)493; GFX10-GISEL-NEXT: global_load_ubyte v1, v0, s[2:3]494; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)495; GFX10-GISEL-NEXT: v_or_b32_e32 v1, 0x100, v1496; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v1, v1497; GFX10-GISEL-NEXT: global_store_byte v0, v1, s[0:1]498; GFX10-GISEL-NEXT: s_endpgm499 %val = load i8, ptr addrspace(1) %valptr500 %cttz = call i8 @llvm.cttz.i8(i8 %val, i1 false) nounwind readnone501 store i8 %cttz, ptr addrspace(1) %out502 ret void503}504 505define amdgpu_kernel void @s_cttz_i64(ptr addrspace(1) noalias %out, [8 x i32], i64 %val) nounwind {506; SI-LABEL: s_cttz_i64:507; SI: ; %bb.0:508; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x13509; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9510; SI-NEXT: s_mov_b32 s3, 0xf000511; SI-NEXT: s_mov_b32 s2, -1512; SI-NEXT: s_waitcnt lgkmcnt(0)513; SI-NEXT: s_ff1_i32_b64 s4, s[6:7]514; SI-NEXT: s_min_u32 s4, s4, 64515; SI-NEXT: v_mov_b32_e32 v1, 0516; SI-NEXT: v_mov_b32_e32 v0, s4517; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0518; SI-NEXT: s_endpgm519;520; VI-LABEL: s_cttz_i64:521; VI: ; %bb.0:522; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x4c523; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24524; VI-NEXT: s_mov_b32 s3, 0xf000525; VI-NEXT: s_mov_b32 s2, -1526; VI-NEXT: v_mov_b32_e32 v1, 0527; VI-NEXT: s_waitcnt lgkmcnt(0)528; VI-NEXT: s_ff1_i32_b64 s4, s[6:7]529; VI-NEXT: s_min_u32 s4, s4, 64530; VI-NEXT: v_mov_b32_e32 v0, s4531; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0532; VI-NEXT: s_endpgm533;534; EG-LABEL: s_cttz_i64:535; EG: ; %bb.0:536; EG-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]537; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1538; EG-NEXT: CF_END539; EG-NEXT: PAD540; EG-NEXT: ALU clause starting at 4:541; EG-NEXT: FFBL_INT * T0.W, KC0[5].X,542; EG-NEXT: CNDE_INT * T0.W, KC0[5].X, literal.x, PV.W,543; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)544; EG-NEXT: FFBL_INT T1.W, KC0[4].W,545; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,546; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)547; EG-NEXT: CNDE_INT T0.X, KC0[4].W, PS, PV.W,548; EG-NEXT: MOV T0.Y, 0.0,549; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,550; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)551;552; GFX10-LABEL: s_cttz_i64:553; GFX10: ; %bb.0:554; GFX10-NEXT: s_clause 0x1555; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x4c556; GFX10-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24557; GFX10-NEXT: v_mov_b32_e32 v1, 0558; GFX10-NEXT: s_waitcnt lgkmcnt(0)559; GFX10-NEXT: s_ff1_i32_b64 s0, s[0:1]560; GFX10-NEXT: s_min_u32 s0, s0, 64561; GFX10-NEXT: v_mov_b32_e32 v0, s0562; GFX10-NEXT: global_store_dwordx2 v1, v[0:1], s[2:3]563; GFX10-NEXT: s_endpgm564;565; GFX10-GISEL-LABEL: s_cttz_i64:566; GFX10-GISEL: ; %bb.0:567; GFX10-GISEL-NEXT: s_clause 0x1568; GFX10-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x4c569; GFX10-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24570; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0571; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)572; GFX10-GISEL-NEXT: s_ff1_i32_b64 s0, s[0:1]573; GFX10-GISEL-NEXT: s_mov_b32 s1, 0574; GFX10-GISEL-NEXT: s_min_u32 s0, s0, 64575; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0576; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1577; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]578; GFX10-GISEL-NEXT: s_endpgm579 %cttz = call i64 @llvm.cttz.i64(i64 %val, i1 false)580 store i64 %cttz, ptr addrspace(1) %out581 ret void582}583 584define amdgpu_kernel void @s_cttz_i64_trunc(ptr addrspace(1) noalias %out, i64 %val) nounwind {585; SI-LABEL: s_cttz_i64_trunc:586; SI: ; %bb.0:587; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9588; SI-NEXT: s_mov_b32 s7, 0xf000589; SI-NEXT: s_waitcnt lgkmcnt(0)590; SI-NEXT: s_ff1_i32_b64 s2, s[2:3]591; SI-NEXT: s_min_u32 s2, s2, 64592; SI-NEXT: s_mov_b32 s6, -1593; SI-NEXT: s_mov_b32 s4, s0594; SI-NEXT: s_mov_b32 s5, s1595; SI-NEXT: v_mov_b32_e32 v0, s2596; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0597; SI-NEXT: s_endpgm598;599; VI-LABEL: s_cttz_i64_trunc:600; VI: ; %bb.0:601; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24602; VI-NEXT: s_mov_b32 s7, 0xf000603; VI-NEXT: s_mov_b32 s6, -1604; VI-NEXT: s_waitcnt lgkmcnt(0)605; VI-NEXT: s_mov_b32 s4, s0606; VI-NEXT: s_ff1_i32_b64 s0, s[2:3]607; VI-NEXT: s_min_u32 s0, s0, 64608; VI-NEXT: s_mov_b32 s5, s1609; VI-NEXT: v_mov_b32_e32 v0, s0610; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0611; VI-NEXT: s_endpgm612;613; EG-LABEL: s_cttz_i64_trunc:614; EG: ; %bb.0:615; EG-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[]616; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1617; EG-NEXT: CF_END618; EG-NEXT: PAD619; EG-NEXT: ALU clause starting at 4:620; EG-NEXT: FFBL_INT * T0.W, KC0[3].X,621; EG-NEXT: CNDE_INT * T0.W, KC0[3].X, literal.x, PV.W,622; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)623; EG-NEXT: FFBL_INT T1.W, KC0[2].W,624; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,625; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)626; EG-NEXT: CNDE_INT T0.X, KC0[2].W, PS, PV.W,627; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,628; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)629;630; GFX10-LABEL: s_cttz_i64_trunc:631; GFX10: ; %bb.0:632; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24633; GFX10-NEXT: v_mov_b32_e32 v0, 0634; GFX10-NEXT: s_waitcnt lgkmcnt(0)635; GFX10-NEXT: s_ff1_i32_b64 s2, s[2:3]636; GFX10-NEXT: s_min_u32 s2, s2, 64637; GFX10-NEXT: v_mov_b32_e32 v1, s2638; GFX10-NEXT: global_store_dword v0, v1, s[0:1]639; GFX10-NEXT: s_endpgm640;641; GFX10-GISEL-LABEL: s_cttz_i64_trunc:642; GFX10-GISEL: ; %bb.0:643; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24644; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0645; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)646; GFX10-GISEL-NEXT: s_ff1_i32_b64 s2, s[2:3]647; GFX10-GISEL-NEXT: s_min_u32 s2, s2, 64648; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2649; GFX10-GISEL-NEXT: global_store_dword v1, v0, s[0:1]650; GFX10-GISEL-NEXT: s_endpgm651 %cttz = call i64 @llvm.cttz.i64(i64 %val, i1 false)652 %trunc = trunc i64 %cttz to i32653 store i32 %trunc, ptr addrspace(1) %out654 ret void655}656 657define amdgpu_kernel void @v_cttz_i64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {658; SI-LABEL: v_cttz_i64:659; SI: ; %bb.0:660; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9661; SI-NEXT: s_mov_b32 s7, 0xf000662; SI-NEXT: s_mov_b32 s6, 0663; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0664; SI-NEXT: v_mov_b32_e32 v1, 0665; SI-NEXT: s_waitcnt lgkmcnt(0)666; SI-NEXT: s_mov_b64 s[4:5], s[2:3]667; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64668; SI-NEXT: s_mov_b64 s[2:3], s[6:7]669; SI-NEXT: s_waitcnt vmcnt(0)670; SI-NEXT: v_ffbl_b32_e32 v3, v3671; SI-NEXT: v_min_u32_e32 v3, 0xffffffdf, v3672; SI-NEXT: v_add_i32_e32 v3, vcc, 32, v3673; SI-NEXT: v_ffbl_b32_e32 v2, v2674; SI-NEXT: v_min3_u32 v2, v2, v3, 64675; SI-NEXT: v_mov_b32_e32 v3, v1676; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64677; SI-NEXT: s_endpgm678;679; VI-LABEL: v_cttz_i64:680; VI: ; %bb.0:681; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24682; VI-NEXT: v_lshlrev_b32_e32 v3, 3, v0683; VI-NEXT: v_mov_b32_e32 v2, 0684; VI-NEXT: s_waitcnt lgkmcnt(0)685; VI-NEXT: v_mov_b32_e32 v1, s3686; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v3687; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc688; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]689; VI-NEXT: v_mov_b32_e32 v4, s1690; VI-NEXT: v_add_u32_e32 v3, vcc, s0, v3691; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc692; VI-NEXT: s_waitcnt vmcnt(0)693; VI-NEXT: v_ffbl_b32_e32 v1, v1694; VI-NEXT: v_add_u32_e64 v1, s[0:1], v1, 32 clamp695; VI-NEXT: v_ffbl_b32_e32 v0, v0696; VI-NEXT: v_min3_u32 v1, v0, v1, 64697; VI-NEXT: flat_store_dwordx2 v[3:4], v[1:2]698; VI-NEXT: s_endpgm699;700; EG-LABEL: v_cttz_i64:701; EG: ; %bb.0:702; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]703; EG-NEXT: TEX 0 @6704; EG-NEXT: ALU 10, @11, KC0[CB0:0-32], KC1[]705; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1706; EG-NEXT: CF_END707; EG-NEXT: PAD708; EG-NEXT: Fetch clause starting at 6:709; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1710; EG-NEXT: ALU clause starting at 8:711; EG-NEXT: LSHL * T0.W, T0.X, literal.x,712; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)713; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,714; EG-NEXT: ALU clause starting at 11:715; EG-NEXT: FFBL_INT * T1.W, T0.Y,716; EG-NEXT: CNDE_INT * T1.W, T0.Y, literal.x, PV.W,717; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)718; EG-NEXT: FFBL_INT T2.W, T0.X,719; EG-NEXT: ADD_INT * T1.W, PV.W, literal.x,720; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)721; EG-NEXT: CNDE_INT T0.X, T0.X, PS, PV.W,722; EG-NEXT: MOV T0.Y, 0.0,723; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,724; EG-NEXT: LSHR * T1.X, PV.W, literal.x,725; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)726;727; GFX10-LABEL: v_cttz_i64:728; GFX10: ; %bb.0:729; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24730; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v0731; GFX10-NEXT: s_waitcnt lgkmcnt(0)732; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3]733; GFX10-NEXT: s_waitcnt vmcnt(0)734; GFX10-NEXT: v_ffbl_b32_e32 v1, v1735; GFX10-NEXT: v_ffbl_b32_e32 v0, v0736; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, 32 clamp737; GFX10-NEXT: v_min3_u32 v0, v0, v1, 64738; GFX10-NEXT: v_mov_b32_e32 v1, 0739; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]740; GFX10-NEXT: s_endpgm741;742; GFX10-GISEL-LABEL: v_cttz_i64:743; GFX10-GISEL: ; %bb.0:744; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24745; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v2, 3, v0746; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)747; GFX10-GISEL-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3]748; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)749; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v1, v1750; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v0, v0751; GFX10-GISEL-NEXT: v_add_nc_u32_e64 v1, v1, 32 clamp752; GFX10-GISEL-NEXT: v_min_u32_e32 v0, v0, v1753; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0754; GFX10-GISEL-NEXT: v_min_u32_e32 v0, 64, v0755; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]756; GFX10-GISEL-NEXT: s_endpgm757 %tid = call i32 @llvm.amdgcn.workitem.id.x()758 %in.gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid759 %out.gep = getelementptr i64, ptr addrspace(1) %out, i32 %tid760 %val = load i64, ptr addrspace(1) %in.gep761 %cttz = call i64 @llvm.cttz.i64(i64 %val, i1 false)762 store i64 %cttz, ptr addrspace(1) %out.gep763 ret void764}765 766define amdgpu_kernel void @v_cttz_i64_trunc(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {767; SI-LABEL: v_cttz_i64_trunc:768; SI: ; %bb.0:769; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9770; SI-NEXT: s_mov_b32 s7, 0xf000771; SI-NEXT: s_mov_b32 s6, 0772; SI-NEXT: v_lshlrev_b32_e32 v1, 3, v0773; SI-NEXT: v_mov_b32_e32 v2, 0774; SI-NEXT: s_waitcnt lgkmcnt(0)775; SI-NEXT: s_mov_b64 s[4:5], s[2:3]776; SI-NEXT: buffer_load_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr64777; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v0778; SI-NEXT: s_mov_b64 s[2:3], s[6:7]779; SI-NEXT: s_waitcnt vmcnt(0)780; SI-NEXT: v_ffbl_b32_e32 v0, v4781; SI-NEXT: v_min_u32_e32 v0, 0xffffffdf, v0782; SI-NEXT: v_add_i32_e32 v0, vcc, 32, v0783; SI-NEXT: v_ffbl_b32_e32 v3, v3784; SI-NEXT: v_min3_u32 v0, v3, v0, 64785; SI-NEXT: buffer_store_dword v0, v[1:2], s[0:3], 0 addr64786; SI-NEXT: s_endpgm787;788; VI-LABEL: v_cttz_i64_trunc:789; VI: ; %bb.0:790; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24791; VI-NEXT: v_lshlrev_b32_e32 v1, 3, v0792; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0793; VI-NEXT: s_waitcnt lgkmcnt(0)794; VI-NEXT: v_mov_b32_e32 v2, s3795; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v1796; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc797; VI-NEXT: flat_load_dwordx2 v[1:2], v[1:2]798; VI-NEXT: v_add_u32_e32 v3, vcc, s0, v0799; VI-NEXT: v_mov_b32_e32 v4, s1800; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc801; VI-NEXT: s_waitcnt vmcnt(0)802; VI-NEXT: v_ffbl_b32_e32 v0, v2803; VI-NEXT: v_add_u32_e64 v0, s[0:1], v0, 32 clamp804; VI-NEXT: v_ffbl_b32_e32 v1, v1805; VI-NEXT: v_min3_u32 v0, v1, v0, 64806; VI-NEXT: flat_store_dword v[3:4], v0807; VI-NEXT: s_endpgm808;809; EG-LABEL: v_cttz_i64_trunc:810; EG: ; %bb.0:811; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]812; EG-NEXT: TEX 0 @6813; EG-NEXT: ALU 10, @11, KC0[CB0:0-32], KC1[]814; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1815; EG-NEXT: CF_END816; EG-NEXT: PAD817; EG-NEXT: Fetch clause starting at 6:818; EG-NEXT: VTX_READ_64 T1.XY, T1.X, 0, #1819; EG-NEXT: ALU clause starting at 8:820; EG-NEXT: LSHL * T0.W, T0.X, literal.x,821; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)822; EG-NEXT: ADD_INT * T1.X, KC0[2].Z, PV.W,823; EG-NEXT: ALU clause starting at 11:824; EG-NEXT: FFBL_INT * T0.W, T1.Y,825; EG-NEXT: CNDE_INT * T0.W, T1.Y, literal.x, PV.W,826; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)827; EG-NEXT: LSHL T0.Z, T0.X, literal.x,828; EG-NEXT: FFBL_INT T1.W, T1.X, BS:VEC_120/SCL_212829; EG-NEXT: ADD_INT * T0.W, PV.W, literal.y,830; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)831; EG-NEXT: CNDE_INT T0.X, T1.X, PS, PV.W,832; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, PV.Z,833; EG-NEXT: LSHR * T1.X, PV.W, literal.x,834; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)835;836; GFX10-LABEL: v_cttz_i64_trunc:837; GFX10: ; %bb.0:838; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24839; GFX10-NEXT: v_lshlrev_b32_e32 v1, 3, v0840; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0841; GFX10-NEXT: s_waitcnt lgkmcnt(0)842; GFX10-NEXT: global_load_dwordx2 v[1:2], v1, s[2:3]843; GFX10-NEXT: s_waitcnt vmcnt(0)844; GFX10-NEXT: v_ffbl_b32_e32 v2, v2845; GFX10-NEXT: v_ffbl_b32_e32 v1, v1846; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, 32 clamp847; GFX10-NEXT: v_min3_u32 v1, v1, v2, 64848; GFX10-NEXT: global_store_dword v0, v1, s[0:1]849; GFX10-NEXT: s_endpgm850;851; GFX10-GISEL-LABEL: v_cttz_i64_trunc:852; GFX10-GISEL: ; %bb.0:853; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24854; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v1, 3, v0855; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0856; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)857; GFX10-GISEL-NEXT: global_load_dwordx2 v[1:2], v1, s[2:3]858; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)859; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v2, v2860; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v1, v1861; GFX10-GISEL-NEXT: v_add_nc_u32_e64 v2, v2, 32 clamp862; GFX10-GISEL-NEXT: v_min_u32_e32 v1, v1, v2863; GFX10-GISEL-NEXT: v_min_u32_e32 v1, 64, v1864; GFX10-GISEL-NEXT: global_store_dword v0, v1, s[0:1]865; GFX10-GISEL-NEXT: s_endpgm866 %tid = call i32 @llvm.amdgcn.workitem.id.x()867 %in.gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid868 %out.gep = getelementptr i32, ptr addrspace(1) %out, i32 %tid869 %val = load i64, ptr addrspace(1) %in.gep870 %cttz = call i64 @llvm.cttz.i64(i64 %val, i1 false)871 %trunc = trunc i64 %cttz to i32872 store i32 %trunc, ptr addrspace(1) %out.gep873 ret void874}875 876define amdgpu_kernel void @v_cttz_i32_sel_eq_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {877; SI-LABEL: v_cttz_i32_sel_eq_neg1:878; SI: ; %bb.0:879; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9880; SI-NEXT: s_mov_b32 s7, 0xf000881; SI-NEXT: s_mov_b32 s10, 0882; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0883; SI-NEXT: v_mov_b32_e32 v1, 0884; SI-NEXT: s_mov_b32 s11, s7885; SI-NEXT: s_waitcnt lgkmcnt(0)886; SI-NEXT: s_mov_b64 s[8:9], s[2:3]887; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64888; SI-NEXT: s_mov_b32 s6, -1889; SI-NEXT: s_mov_b32 s4, s0890; SI-NEXT: s_mov_b32 s5, s1891; SI-NEXT: s_waitcnt vmcnt(0)892; SI-NEXT: v_ffbl_b32_e32 v0, v0893; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0894; SI-NEXT: s_endpgm895;896; VI-LABEL: v_cttz_i32_sel_eq_neg1:897; VI: ; %bb.0:898; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24899; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0900; VI-NEXT: s_waitcnt lgkmcnt(0)901; VI-NEXT: v_mov_b32_e32 v1, s3902; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0903; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc904; VI-NEXT: flat_load_dword v0, v[0:1]905; VI-NEXT: s_mov_b32 s3, 0xf000906; VI-NEXT: s_mov_b32 s2, -1907; VI-NEXT: s_waitcnt vmcnt(0)908; VI-NEXT: v_ffbl_b32_e32 v0, v0909; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0910; VI-NEXT: s_endpgm911;912; EG-LABEL: v_cttz_i32_sel_eq_neg1:913; EG: ; %bb.0:914; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]915; EG-NEXT: TEX 0 @6916; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]917; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1918; EG-NEXT: CF_END919; EG-NEXT: PAD920; EG-NEXT: Fetch clause starting at 6:921; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1922; EG-NEXT: ALU clause starting at 8:923; EG-NEXT: LSHL * T0.W, T0.X, literal.x,924; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)925; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,926; EG-NEXT: ALU clause starting at 11:927; EG-NEXT: FFBL_INT * T0.W, T0.X,928; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W,929; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)930; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W,931; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,932; EG-NEXT: -1(nan), 2(2.802597e-45)933;934; GFX10-LABEL: v_cttz_i32_sel_eq_neg1:935; GFX10: ; %bb.0:936; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24937; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0938; GFX10-NEXT: v_mov_b32_e32 v1, 0939; GFX10-NEXT: s_waitcnt lgkmcnt(0)940; GFX10-NEXT: global_load_dword v0, v0, s[2:3]941; GFX10-NEXT: s_waitcnt vmcnt(0)942; GFX10-NEXT: v_ffbl_b32_e32 v0, v0943; GFX10-NEXT: global_store_dword v1, v0, s[0:1]944; GFX10-NEXT: s_endpgm945;946; GFX10-GISEL-LABEL: v_cttz_i32_sel_eq_neg1:947; GFX10-GISEL: ; %bb.0:948; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24949; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0950; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)951; GFX10-GISEL-NEXT: global_load_dword v0, v0, s[2:3]952; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)953; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v1, v0954; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0955; GFX10-GISEL-NEXT: v_min_u32_e32 v1, 32, v1956; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, -1, vcc_lo957; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0958; GFX10-GISEL-NEXT: global_store_dword v1, v0, s[0:1]959; GFX10-GISEL-NEXT: s_endpgm960 %tid = call i32 @llvm.amdgcn.workitem.id.x()961 %in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid962 %val = load i32, ptr addrspace(1) %in.gep963 %cttz = call i32 @llvm.cttz.i32(i32 %val, i1 false) nounwind readnone964 %cmp = icmp eq i32 %val, 0965 %sel = select i1 %cmp, i32 -1, i32 %cttz966 store i32 %sel, ptr addrspace(1) %out967 ret void968}969 970define amdgpu_kernel void @v_cttz_i32_sel_ne_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {971; SI-LABEL: v_cttz_i32_sel_ne_neg1:972; SI: ; %bb.0:973; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9974; SI-NEXT: s_mov_b32 s7, 0xf000975; SI-NEXT: s_mov_b32 s10, 0976; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0977; SI-NEXT: v_mov_b32_e32 v1, 0978; SI-NEXT: s_mov_b32 s11, s7979; SI-NEXT: s_waitcnt lgkmcnt(0)980; SI-NEXT: s_mov_b64 s[8:9], s[2:3]981; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64982; SI-NEXT: s_mov_b32 s6, -1983; SI-NEXT: s_mov_b32 s4, s0984; SI-NEXT: s_mov_b32 s5, s1985; SI-NEXT: s_waitcnt vmcnt(0)986; SI-NEXT: v_ffbl_b32_e32 v0, v0987; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0988; SI-NEXT: s_endpgm989;990; VI-LABEL: v_cttz_i32_sel_ne_neg1:991; VI: ; %bb.0:992; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24993; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0994; VI-NEXT: s_waitcnt lgkmcnt(0)995; VI-NEXT: v_mov_b32_e32 v1, s3996; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0997; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc998; VI-NEXT: flat_load_dword v0, v[0:1]999; VI-NEXT: s_mov_b32 s3, 0xf0001000; VI-NEXT: s_mov_b32 s2, -11001; VI-NEXT: s_waitcnt vmcnt(0)1002; VI-NEXT: v_ffbl_b32_e32 v0, v01003; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01004; VI-NEXT: s_endpgm1005;1006; EG-LABEL: v_cttz_i32_sel_ne_neg1:1007; EG: ; %bb.0:1008; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]1009; EG-NEXT: TEX 0 @61010; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]1011; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11012; EG-NEXT: CF_END1013; EG-NEXT: PAD1014; EG-NEXT: Fetch clause starting at 6:1015; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11016; EG-NEXT: ALU clause starting at 8:1017; EG-NEXT: LSHL * T0.W, T0.X, literal.x,1018; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1019; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1020; EG-NEXT: ALU clause starting at 11:1021; EG-NEXT: FFBL_INT * T0.W, T0.X,1022; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W,1023; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1024; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W,1025; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,1026; EG-NEXT: -1(nan), 2(2.802597e-45)1027;1028; GFX10-LABEL: v_cttz_i32_sel_ne_neg1:1029; GFX10: ; %bb.0:1030; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241031; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v01032; GFX10-NEXT: v_mov_b32_e32 v1, 01033; GFX10-NEXT: s_waitcnt lgkmcnt(0)1034; GFX10-NEXT: global_load_dword v0, v0, s[2:3]1035; GFX10-NEXT: s_waitcnt vmcnt(0)1036; GFX10-NEXT: v_ffbl_b32_e32 v0, v01037; GFX10-NEXT: global_store_dword v1, v0, s[0:1]1038; GFX10-NEXT: s_endpgm1039;1040; GFX10-GISEL-LABEL: v_cttz_i32_sel_ne_neg1:1041; GFX10-GISEL: ; %bb.0:1042; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241043; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v01044; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)1045; GFX10-GISEL-NEXT: global_load_dword v0, v0, s[2:3]1046; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)1047; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v1, v01048; GFX10-GISEL-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v01049; GFX10-GISEL-NEXT: v_min_u32_e32 v1, 32, v11050; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, -1, v1, vcc_lo1051; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 01052; GFX10-GISEL-NEXT: global_store_dword v1, v0, s[0:1]1053; GFX10-GISEL-NEXT: s_endpgm1054 %tid = call i32 @llvm.amdgcn.workitem.id.x()1055 %in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid1056 %val = load i32, ptr addrspace(1) %in.gep1057 %cttz = call i32 @llvm.cttz.i32(i32 %val, i1 false) nounwind readnone1058 %cmp = icmp ne i32 %val, 01059 %sel = select i1 %cmp, i32 %cttz, i32 -11060 store i32 %sel, ptr addrspace(1) %out1061 ret void1062}1063 1064; TODO: Should be able to eliminate select here as well.1065define amdgpu_kernel void @v_cttz_i32_sel_eq_bitwidth(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {1066; SI-LABEL: v_cttz_i32_sel_eq_bitwidth:1067; SI: ; %bb.0:1068; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91069; SI-NEXT: s_mov_b32 s7, 0xf0001070; SI-NEXT: s_mov_b32 s10, 01071; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v01072; SI-NEXT: v_mov_b32_e32 v1, 01073; SI-NEXT: s_mov_b32 s11, s71074; SI-NEXT: s_waitcnt lgkmcnt(0)1075; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1076; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr641077; SI-NEXT: s_mov_b32 s6, -11078; SI-NEXT: s_mov_b32 s4, s01079; SI-NEXT: s_mov_b32 s5, s11080; SI-NEXT: s_waitcnt vmcnt(0)1081; SI-NEXT: v_ffbl_b32_e32 v0, v01082; SI-NEXT: v_min_u32_e32 v0, 32, v01083; SI-NEXT: v_cmp_ne_u32_e32 vcc, 32, v01084; SI-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc1085; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01086; SI-NEXT: s_endpgm1087;1088; VI-LABEL: v_cttz_i32_sel_eq_bitwidth:1089; VI: ; %bb.0:1090; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241091; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v01092; VI-NEXT: s_waitcnt lgkmcnt(0)1093; VI-NEXT: v_mov_b32_e32 v1, s31094; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01095; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1096; VI-NEXT: flat_load_dword v0, v[0:1]1097; VI-NEXT: s_mov_b32 s3, 0xf0001098; VI-NEXT: s_mov_b32 s2, -11099; VI-NEXT: s_waitcnt vmcnt(0)1100; VI-NEXT: v_ffbl_b32_e32 v0, v01101; VI-NEXT: v_min_u32_e32 v0, 32, v01102; VI-NEXT: v_cmp_ne_u32_e32 vcc, 32, v01103; VI-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc1104; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01105; VI-NEXT: s_endpgm1106;1107; EG-LABEL: v_cttz_i32_sel_eq_bitwidth:1108; EG: ; %bb.0:1109; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]1110; EG-NEXT: TEX 0 @61111; EG-NEXT: ALU 7, @11, KC0[CB0:0-32], KC1[]1112; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11113; EG-NEXT: CF_END1114; EG-NEXT: PAD1115; EG-NEXT: Fetch clause starting at 6:1116; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11117; EG-NEXT: ALU clause starting at 8:1118; EG-NEXT: LSHL * T0.W, T0.X, literal.x,1119; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1120; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1121; EG-NEXT: ALU clause starting at 11:1122; EG-NEXT: FFBL_INT * T0.W, T0.X,1123; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W,1124; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1125; EG-NEXT: SETE_INT * T1.W, PV.W, literal.x,1126; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1127; EG-NEXT: CNDE_INT T0.X, PV.W, T0.W, literal.x,1128; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,1129; EG-NEXT: -1(nan), 2(2.802597e-45)1130;1131; GFX10-LABEL: v_cttz_i32_sel_eq_bitwidth:1132; GFX10: ; %bb.0:1133; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241134; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v01135; GFX10-NEXT: v_mov_b32_e32 v1, 01136; GFX10-NEXT: s_waitcnt lgkmcnt(0)1137; GFX10-NEXT: global_load_dword v0, v0, s[2:3]1138; GFX10-NEXT: s_waitcnt vmcnt(0)1139; GFX10-NEXT: v_ffbl_b32_e32 v0, v01140; GFX10-NEXT: v_min_u32_e32 v0, 32, v01141; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 32, v01142; GFX10-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc_lo1143; GFX10-NEXT: global_store_dword v1, v0, s[0:1]1144; GFX10-NEXT: s_endpgm1145;1146; GFX10-GISEL-LABEL: v_cttz_i32_sel_eq_bitwidth:1147; GFX10-GISEL: ; %bb.0:1148; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241149; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v01150; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 01151; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)1152; GFX10-GISEL-NEXT: global_load_dword v0, v0, s[2:3]1153; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)1154; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v0, v01155; GFX10-GISEL-NEXT: v_min_u32_e32 v0, 32, v01156; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 32, v01157; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc_lo1158; GFX10-GISEL-NEXT: global_store_dword v1, v0, s[0:1]1159; GFX10-GISEL-NEXT: s_endpgm1160 %tid = call i32 @llvm.amdgcn.workitem.id.x()1161 %in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid1162 %val = load i32, ptr addrspace(1) %in.gep1163 %cttz = call i32 @llvm.cttz.i32(i32 %val, i1 false) nounwind readnone1164 %cmp = icmp eq i32 %cttz, 321165 %sel = select i1 %cmp, i32 -1, i32 %cttz1166 store i32 %sel, ptr addrspace(1) %out1167 ret void1168}1169 1170define amdgpu_kernel void @v_cttz_i32_sel_ne_bitwidth(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {1171; SI-LABEL: v_cttz_i32_sel_ne_bitwidth:1172; SI: ; %bb.0:1173; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91174; SI-NEXT: s_mov_b32 s7, 0xf0001175; SI-NEXT: s_mov_b32 s10, 01176; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v01177; SI-NEXT: v_mov_b32_e32 v1, 01178; SI-NEXT: s_mov_b32 s11, s71179; SI-NEXT: s_waitcnt lgkmcnt(0)1180; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1181; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr641182; SI-NEXT: s_mov_b32 s6, -11183; SI-NEXT: s_mov_b32 s4, s01184; SI-NEXT: s_mov_b32 s5, s11185; SI-NEXT: s_waitcnt vmcnt(0)1186; SI-NEXT: v_ffbl_b32_e32 v0, v01187; SI-NEXT: v_min_u32_e32 v0, 32, v01188; SI-NEXT: v_cmp_ne_u32_e32 vcc, 32, v01189; SI-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc1190; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01191; SI-NEXT: s_endpgm1192;1193; VI-LABEL: v_cttz_i32_sel_ne_bitwidth:1194; VI: ; %bb.0:1195; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241196; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v01197; VI-NEXT: s_waitcnt lgkmcnt(0)1198; VI-NEXT: v_mov_b32_e32 v1, s31199; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01200; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1201; VI-NEXT: flat_load_dword v0, v[0:1]1202; VI-NEXT: s_mov_b32 s3, 0xf0001203; VI-NEXT: s_mov_b32 s2, -11204; VI-NEXT: s_waitcnt vmcnt(0)1205; VI-NEXT: v_ffbl_b32_e32 v0, v01206; VI-NEXT: v_min_u32_e32 v0, 32, v01207; VI-NEXT: v_cmp_ne_u32_e32 vcc, 32, v01208; VI-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc1209; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01210; VI-NEXT: s_endpgm1211;1212; EG-LABEL: v_cttz_i32_sel_ne_bitwidth:1213; EG: ; %bb.0:1214; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]1215; EG-NEXT: TEX 0 @61216; EG-NEXT: ALU 7, @11, KC0[CB0:0-32], KC1[]1217; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11218; EG-NEXT: CF_END1219; EG-NEXT: PAD1220; EG-NEXT: Fetch clause starting at 6:1221; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11222; EG-NEXT: ALU clause starting at 8:1223; EG-NEXT: LSHL * T0.W, T0.X, literal.x,1224; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1225; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1226; EG-NEXT: ALU clause starting at 11:1227; EG-NEXT: FFBL_INT * T0.W, T0.X,1228; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W,1229; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1230; EG-NEXT: SETNE_INT * T1.W, PV.W, literal.x,1231; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1232; EG-NEXT: CNDE_INT T0.X, PV.W, literal.x, T0.W,1233; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,1234; EG-NEXT: -1(nan), 2(2.802597e-45)1235;1236; GFX10-LABEL: v_cttz_i32_sel_ne_bitwidth:1237; GFX10: ; %bb.0:1238; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241239; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v01240; GFX10-NEXT: v_mov_b32_e32 v1, 01241; GFX10-NEXT: s_waitcnt lgkmcnt(0)1242; GFX10-NEXT: global_load_dword v0, v0, s[2:3]1243; GFX10-NEXT: s_waitcnt vmcnt(0)1244; GFX10-NEXT: v_ffbl_b32_e32 v0, v01245; GFX10-NEXT: v_min_u32_e32 v0, 32, v01246; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 32, v01247; GFX10-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc_lo1248; GFX10-NEXT: global_store_dword v1, v0, s[0:1]1249; GFX10-NEXT: s_endpgm1250;1251; GFX10-GISEL-LABEL: v_cttz_i32_sel_ne_bitwidth:1252; GFX10-GISEL: ; %bb.0:1253; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241254; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v01255; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 01256; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)1257; GFX10-GISEL-NEXT: global_load_dword v0, v0, s[2:3]1258; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)1259; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v0, v01260; GFX10-GISEL-NEXT: v_min_u32_e32 v0, 32, v01261; GFX10-GISEL-NEXT: v_cmp_ne_u32_e32 vcc_lo, 32, v01262; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc_lo1263; GFX10-GISEL-NEXT: global_store_dword v1, v0, s[0:1]1264; GFX10-GISEL-NEXT: s_endpgm1265 %tid = call i32 @llvm.amdgcn.workitem.id.x()1266 %in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid1267 %val = load i32, ptr addrspace(1) %in.gep1268 %cttz = call i32 @llvm.cttz.i32(i32 %val, i1 false) nounwind readnone1269 %cmp = icmp ne i32 %cttz, 321270 %sel = select i1 %cmp, i32 %cttz, i32 -11271 store i32 %sel, ptr addrspace(1) %out1272 ret void1273}1274 1275 define amdgpu_kernel void @v_cttz_i8_sel_eq_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {1276; SI-LABEL: v_cttz_i8_sel_eq_neg1:1277; SI: ; %bb.0:1278; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91279; SI-NEXT: s_mov_b32 s7, 0xf0001280; SI-NEXT: v_mov_b32_e32 v1, 01281; SI-NEXT: s_mov_b32 s10, 01282; SI-NEXT: s_mov_b32 s11, s71283; SI-NEXT: s_waitcnt lgkmcnt(0)1284; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1285; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[8:11], 0 addr641286; SI-NEXT: s_mov_b32 s6, -11287; SI-NEXT: s_mov_b32 s4, s01288; SI-NEXT: s_mov_b32 s5, s11289; SI-NEXT: s_waitcnt vmcnt(0)1290; SI-NEXT: v_ffbl_b32_e32 v0, v01291; SI-NEXT: buffer_store_byte v0, off, s[4:7], 01292; SI-NEXT: s_endpgm1293;1294; VI-LABEL: v_cttz_i8_sel_eq_neg1:1295; VI: ; %bb.0:1296; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241297; VI-NEXT: s_waitcnt lgkmcnt(0)1298; VI-NEXT: v_mov_b32_e32 v1, s31299; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01300; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1301; VI-NEXT: flat_load_ubyte v0, v[0:1]1302; VI-NEXT: s_mov_b32 s3, 0xf0001303; VI-NEXT: s_mov_b32 s2, -11304; VI-NEXT: s_waitcnt vmcnt(0)1305; VI-NEXT: v_ffbl_b32_e32 v0, v01306; VI-NEXT: buffer_store_byte v0, off, s[0:3], 01307; VI-NEXT: s_endpgm1308;1309; EG-LABEL: v_cttz_i8_sel_eq_neg1:1310; EG: ; %bb.0:1311; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]1312; EG-NEXT: TEX 0 @61313; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[]1314; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1315; EG-NEXT: CF_END1316; EG-NEXT: PAD1317; EG-NEXT: Fetch clause starting at 6:1318; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #11319; EG-NEXT: ALU clause starting at 8:1320; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, T0.X,1321; EG-NEXT: ALU clause starting at 9:1322; EG-NEXT: FFBL_INT T0.W, T0.X,1323; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,1324; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1325; EG-NEXT: AND_INT T0.W, PV.W, literal.x,1326; EG-NEXT: LSHL * T1.W, PS, literal.y,1327; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)1328; EG-NEXT: LSHL T0.X, PV.W, PS,1329; EG-NEXT: LSHL * T0.W, literal.x, PS,1330; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)1331; EG-NEXT: MOV T0.Y, 0.0,1332; EG-NEXT: MOV * T0.Z, 0.0,1333; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1334; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1335;1336; GFX10-LABEL: v_cttz_i8_sel_eq_neg1:1337; GFX10: ; %bb.0:1338; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241339; GFX10-NEXT: v_mov_b32_e32 v1, 01340; GFX10-NEXT: s_waitcnt lgkmcnt(0)1341; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3]1342; GFX10-NEXT: s_waitcnt vmcnt(0)1343; GFX10-NEXT: v_ffbl_b32_e32 v0, v01344; GFX10-NEXT: global_store_byte v1, v0, s[0:1]1345; GFX10-NEXT: s_endpgm1346;1347; GFX10-GISEL-LABEL: v_cttz_i8_sel_eq_neg1:1348; GFX10-GISEL: ; %bb.0:1349; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241350; GFX10-GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v01351; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)1352; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s21353; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s31354; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v1, v01355; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v2, v3, vcc_lo1356; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 01357; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off1358; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)1359; GFX10-GISEL-NEXT: v_or_b32_e32 v1, 0x100, v01360; GFX10-GISEL-NEXT: v_cmp_eq_u32_sdwa s2, v0, v2 src0_sel:BYTE_0 src1_sel:DWORD1361; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v1, v11362; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0xffff, s21363; GFX10-GISEL-NEXT: global_store_byte v2, v0, s[0:1]1364; GFX10-GISEL-NEXT: s_endpgm1365 %tid = call i32 @llvm.amdgcn.workitem.id.x()1366 %valptr.gep = getelementptr i8, ptr addrspace(1) %valptr, i32 %tid1367 %val = load i8, ptr addrspace(1) %valptr.gep1368 %cttz = call i8 @llvm.cttz.i8(i8 %val, i1 false) nounwind readnone1369 %cmp = icmp eq i8 %val, 01370 %sel = select i1 %cmp, i8 -1, i8 %cttz1371 store i8 %sel, ptr addrspace(1) %out1372 ret void1373}1374 1375 define amdgpu_kernel void @v_cttz_i16_sel_eq_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {1376; SI-LABEL: v_cttz_i16_sel_eq_neg1:1377; SI: ; %bb.0:1378; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91379; SI-NEXT: s_mov_b32 s7, 0xf0001380; SI-NEXT: s_mov_b32 s6, -11381; SI-NEXT: s_mov_b32 s10, s61382; SI-NEXT: s_mov_b32 s11, s71383; SI-NEXT: s_waitcnt lgkmcnt(0)1384; SI-NEXT: s_mov_b32 s8, s21385; SI-NEXT: s_mov_b32 s9, s31386; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 01387; SI-NEXT: s_mov_b32 s4, s01388; SI-NEXT: s_mov_b32 s5, s11389; SI-NEXT: s_waitcnt vmcnt(0)1390; SI-NEXT: v_ffbl_b32_e32 v0, v01391; SI-NEXT: buffer_store_short v0, off, s[4:7], 01392; SI-NEXT: s_endpgm1393;1394; VI-LABEL: v_cttz_i16_sel_eq_neg1:1395; VI: ; %bb.0:1396; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241397; VI-NEXT: s_mov_b32 s7, 0xf0001398; VI-NEXT: s_mov_b32 s6, -11399; VI-NEXT: s_mov_b32 s10, s61400; VI-NEXT: s_mov_b32 s11, s71401; VI-NEXT: s_waitcnt lgkmcnt(0)1402; VI-NEXT: s_mov_b32 s8, s21403; VI-NEXT: s_mov_b32 s9, s31404; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 01405; VI-NEXT: s_mov_b32 s4, s01406; VI-NEXT: s_mov_b32 s5, s11407; VI-NEXT: s_waitcnt vmcnt(0)1408; VI-NEXT: v_ffbl_b32_e32 v0, v01409; VI-NEXT: buffer_store_short v0, off, s[4:7], 01410; VI-NEXT: s_endpgm1411;1412; EG-LABEL: v_cttz_i16_sel_eq_neg1:1413; EG: ; %bb.0:1414; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]1415; EG-NEXT: TEX 0 @61416; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[]1417; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1418; EG-NEXT: CF_END1419; EG-NEXT: PAD1420; EG-NEXT: Fetch clause starting at 6:1421; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #11422; EG-NEXT: ALU clause starting at 8:1423; EG-NEXT: MOV * T0.X, KC0[2].Z,1424; EG-NEXT: ALU clause starting at 9:1425; EG-NEXT: FFBL_INT T0.W, T0.X,1426; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,1427; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1428; EG-NEXT: AND_INT T0.W, PV.W, literal.x,1429; EG-NEXT: LSHL * T1.W, PS, literal.y,1430; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)1431; EG-NEXT: LSHL T0.X, PV.W, PS,1432; EG-NEXT: LSHL * T0.W, literal.x, PS,1433; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1434; EG-NEXT: MOV T0.Y, 0.0,1435; EG-NEXT: MOV * T0.Z, 0.0,1436; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1437; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1438;1439; GFX10-LABEL: v_cttz_i16_sel_eq_neg1:1440; GFX10: ; %bb.0:1441; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241442; GFX10-NEXT: v_mov_b32_e32 v0, 01443; GFX10-NEXT: s_waitcnt lgkmcnt(0)1444; GFX10-NEXT: global_load_ushort v1, v0, s[2:3]1445; GFX10-NEXT: s_waitcnt vmcnt(0)1446; GFX10-NEXT: v_ffbl_b32_e32 v1, v11447; GFX10-NEXT: global_store_short v0, v1, s[0:1]1448; GFX10-NEXT: s_endpgm1449;1450; GFX10-GISEL-LABEL: v_cttz_i16_sel_eq_neg1:1451; GFX10-GISEL: ; %bb.0:1452; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241453; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, 01454; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)1455; GFX10-GISEL-NEXT: global_load_ushort v1, v0, s[2:3]1456; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)1457; GFX10-GISEL-NEXT: v_or_b32_e32 v2, 0x10000, v11458; GFX10-GISEL-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11459; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v2, v21460; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v2, 0xffff, vcc_lo1461; GFX10-GISEL-NEXT: global_store_short v0, v1, s[0:1]1462; GFX10-GISEL-NEXT: s_endpgm1463 %val = load i16, ptr addrspace(1) %valptr1464 %cttz = call i16 @llvm.cttz.i16(i16 %val, i1 false) nounwind readnone1465 %cmp = icmp eq i16 %val, 01466 %sel = select i1 %cmp, i16 -1, i16 %cttz1467 store i16 %sel, ptr addrspace(1) %out1468 ret void1469}1470 1471; FIXME: Need to handle non-uniform case for function below (load without gep).1472define amdgpu_kernel void @v_cttz_i7_sel_eq_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {1473; SI-LABEL: v_cttz_i7_sel_eq_neg1:1474; SI: ; %bb.0:1475; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91476; SI-NEXT: s_mov_b32 s7, 0xf0001477; SI-NEXT: v_mov_b32_e32 v1, 01478; SI-NEXT: s_mov_b32 s10, 01479; SI-NEXT: s_mov_b32 s11, s71480; SI-NEXT: s_waitcnt lgkmcnt(0)1481; SI-NEXT: s_mov_b64 s[8:9], s[2:3]1482; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[8:11], 0 addr641483; SI-NEXT: s_mov_b32 s6, -11484; SI-NEXT: s_mov_b32 s4, s01485; SI-NEXT: s_mov_b32 s5, s11486; SI-NEXT: s_waitcnt vmcnt(0)1487; SI-NEXT: v_ffbl_b32_e32 v0, v01488; SI-NEXT: v_and_b32_e32 v0, 0x7f, v01489; SI-NEXT: buffer_store_byte v0, off, s[4:7], 01490; SI-NEXT: s_endpgm1491;1492; VI-LABEL: v_cttz_i7_sel_eq_neg1:1493; VI: ; %bb.0:1494; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241495; VI-NEXT: s_waitcnt lgkmcnt(0)1496; VI-NEXT: v_mov_b32_e32 v1, s31497; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v01498; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1499; VI-NEXT: flat_load_ubyte v0, v[0:1]1500; VI-NEXT: s_mov_b32 s3, 0xf0001501; VI-NEXT: s_mov_b32 s2, -11502; VI-NEXT: s_waitcnt vmcnt(0)1503; VI-NEXT: v_ffbl_b32_e32 v0, v01504; VI-NEXT: v_and_b32_e32 v0, 0x7f, v01505; VI-NEXT: buffer_store_byte v0, off, s[0:3], 01506; VI-NEXT: s_endpgm1507;1508; EG-LABEL: v_cttz_i7_sel_eq_neg1:1509; EG: ; %bb.0:1510; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]1511; EG-NEXT: TEX 0 @61512; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[]1513; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1514; EG-NEXT: CF_END1515; EG-NEXT: PAD1516; EG-NEXT: Fetch clause starting at 6:1517; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #11518; EG-NEXT: ALU clause starting at 8:1519; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, T0.X,1520; EG-NEXT: ALU clause starting at 9:1521; EG-NEXT: FFBL_INT T0.W, T0.X,1522; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,1523; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1524; EG-NEXT: AND_INT T0.W, PV.W, literal.x,1525; EG-NEXT: LSHL * T1.W, PS, literal.y,1526; EG-NEXT: 127(1.779649e-43), 3(4.203895e-45)1527; EG-NEXT: LSHL T0.X, PV.W, PS,1528; EG-NEXT: LSHL * T0.W, literal.x, PS,1529; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)1530; EG-NEXT: MOV T0.Y, 0.0,1531; EG-NEXT: MOV * T0.Z, 0.0,1532; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1533; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1534;1535; GFX10-LABEL: v_cttz_i7_sel_eq_neg1:1536; GFX10: ; %bb.0:1537; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241538; GFX10-NEXT: v_mov_b32_e32 v1, 01539; GFX10-NEXT: s_waitcnt lgkmcnt(0)1540; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3]1541; GFX10-NEXT: s_waitcnt vmcnt(0)1542; GFX10-NEXT: v_ffbl_b32_e32 v0, v01543; GFX10-NEXT: v_and_b32_e32 v0, 0x7f, v01544; GFX10-NEXT: global_store_byte v1, v0, s[0:1]1545; GFX10-NEXT: s_endpgm1546;1547; GFX10-GISEL-LABEL: v_cttz_i7_sel_eq_neg1:1548; GFX10-GISEL: ; %bb.0:1549; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241550; GFX10-GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v01551; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)1552; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s21553; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s31554; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v1, v01555; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v2, v3, vcc_lo1556; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off1557; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)1558; GFX10-GISEL-NEXT: v_or_b32_e32 v1, 0x80, v01559; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0x7f, v01560; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v1, v11561; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v01562; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0x7f, vcc_lo1563; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 01564; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0x7f, v01565; GFX10-GISEL-NEXT: global_store_byte v1, v0, s[0:1]1566; GFX10-GISEL-NEXT: s_endpgm1567 %tid = call i32 @llvm.amdgcn.workitem.id.x()1568 %valptr.gep = getelementptr i7, ptr addrspace(1) %valptr, i32 %tid1569 %val = load i7, ptr addrspace(1) %valptr.gep1570 %cttz = call i7 @llvm.cttz.i7(i7 %val, i1 false) nounwind readnone1571 %cmp = icmp eq i7 %val, 01572 %sel = select i1 %cmp, i7 -1, i7 %cttz1573 store i7 %sel, ptr addrspace(1) %out1574 ret void1575}1576