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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefixes=SI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s4; RUN: llc -mtriple=r600 -mcpu=cypress < %s | FileCheck -check-prefixes=EG %s5; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9-GISEL %s6 7declare i7 @llvm.cttz.i7(i7, i1) nounwind readnone8declare i8 @llvm.cttz.i8(i8, i1) nounwind readnone9declare i16 @llvm.cttz.i16(i16, i1) nounwind readnone10declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone11declare i64 @llvm.cttz.i64(i64, i1) nounwind readnone12declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1) nounwind readnone13declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1) nounwind readnone14declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone15 16define amdgpu_kernel void @s_cttz_zero_undef_i32(ptr addrspace(1) noalias %out, i32 %val) nounwind {17; SI-LABEL: s_cttz_zero_undef_i32:18; SI: ; %bb.0:19; SI-NEXT: s_load_dword s2, s[4:5], 0xb20; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x921; SI-NEXT: s_mov_b32 s3, 0xf00022; SI-NEXT: s_waitcnt lgkmcnt(0)23; SI-NEXT: s_ff1_i32_b32 s4, s224; SI-NEXT: s_mov_b32 s2, -125; SI-NEXT: v_mov_b32_e32 v0, s426; SI-NEXT: buffer_store_dword v0, off, s[0:3], 027; SI-NEXT: s_endpgm28;29; VI-LABEL: s_cttz_zero_undef_i32:30; VI: ; %bb.0:31; VI-NEXT: s_load_dword s2, s[4:5], 0x2c32; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2433; VI-NEXT: s_waitcnt lgkmcnt(0)34; VI-NEXT: s_ff1_i32_b32 s2, s235; VI-NEXT: v_mov_b32_e32 v0, s036; VI-NEXT: v_mov_b32_e32 v1, s137; VI-NEXT: v_mov_b32_e32 v2, s238; VI-NEXT: flat_store_dword v[0:1], v239; VI-NEXT: s_endpgm40;41; EG-LABEL: s_cttz_zero_undef_i32:42; EG: ; %bb.0:43; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]44; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 145; EG-NEXT: CF_END46; EG-NEXT: PAD47; EG-NEXT: ALU clause starting at 4:48; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,49; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)50; EG-NEXT: FFBL_INT * T1.X, KC0[2].Z,51;52; GFX9-GISEL-LABEL: s_cttz_zero_undef_i32:53; GFX9-GISEL: ; %bb.0:54; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c55; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2456; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 057; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)58; GFX9-GISEL-NEXT: s_ff1_i32_b32 s2, s259; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s260; GFX9-GISEL-NEXT: global_store_dword v1, v0, s[0:1]61; GFX9-GISEL-NEXT: s_endpgm62 %cttz = call i32 @llvm.cttz.i32(i32 %val, i1 true) nounwind readnone63 store i32 %cttz, ptr addrspace(1) %out, align 464 ret void65}66 67define amdgpu_kernel void @v_cttz_zero_undef_i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {68; SI-LABEL: v_cttz_zero_undef_i32:69; SI: ; %bb.0:70; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x971; SI-NEXT: s_mov_b32 s7, 0xf00072; SI-NEXT: s_mov_b32 s10, 073; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v074; SI-NEXT: v_mov_b32_e32 v1, 075; SI-NEXT: s_mov_b32 s11, s776; SI-NEXT: s_waitcnt lgkmcnt(0)77; SI-NEXT: s_mov_b64 s[8:9], s[2:3]78; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr6479; SI-NEXT: s_mov_b32 s6, -180; SI-NEXT: s_mov_b32 s4, s081; SI-NEXT: s_mov_b32 s5, s182; SI-NEXT: s_waitcnt vmcnt(0)83; SI-NEXT: v_ffbl_b32_e32 v0, v084; SI-NEXT: buffer_store_dword v0, off, s[4:7], 085; SI-NEXT: s_endpgm86;87; VI-LABEL: v_cttz_zero_undef_i32:88; VI: ; %bb.0:89; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2490; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v091; VI-NEXT: s_waitcnt lgkmcnt(0)92; VI-NEXT: v_mov_b32_e32 v1, s393; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v094; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc95; VI-NEXT: flat_load_dword v0, v[0:1]96; VI-NEXT: s_waitcnt vmcnt(0)97; VI-NEXT: v_ffbl_b32_e32 v2, v098; VI-NEXT: v_mov_b32_e32 v0, s099; VI-NEXT: v_mov_b32_e32 v1, s1100; VI-NEXT: flat_store_dword v[0:1], v2101; VI-NEXT: s_endpgm102;103; EG-LABEL: v_cttz_zero_undef_i32:104; EG: ; %bb.0:105; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]106; EG-NEXT: TEX 0 @6107; EG-NEXT: ALU 2, @11, KC0[CB0:0-32], KC1[]108; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1109; EG-NEXT: CF_END110; EG-NEXT: PAD111; EG-NEXT: Fetch clause starting at 6:112; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1113; EG-NEXT: ALU clause starting at 8:114; EG-NEXT: LSHL * T0.W, T0.X, literal.x,115; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)116; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,117; EG-NEXT: ALU clause starting at 11:118; EG-NEXT: FFBL_INT T0.X, T0.X,119; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,120; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)121;122; GFX9-GISEL-LABEL: v_cttz_zero_undef_i32:123; GFX9-GISEL: ; %bb.0:124; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24125; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0126; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0127; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)128; GFX9-GISEL-NEXT: global_load_dword v0, v0, s[2:3]129; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)130; GFX9-GISEL-NEXT: v_ffbl_b32_e32 v0, v0131; GFX9-GISEL-NEXT: global_store_dword v1, v0, s[0:1]132; GFX9-GISEL-NEXT: s_endpgm133 %tid = call i32 @llvm.amdgcn.workitem.id.x()134 %in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid135 %val = load i32, ptr addrspace(1) %in.gep, align 4136 %cttz = call i32 @llvm.cttz.i32(i32 %val, i1 true) nounwind readnone137 store i32 %cttz, ptr addrspace(1) %out, align 4138 ret void139}140 141define amdgpu_kernel void @v_cttz_zero_undef_v2i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {142; SI-LABEL: v_cttz_zero_undef_v2i32:143; SI: ; %bb.0:144; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9145; SI-NEXT: s_mov_b32 s7, 0xf000146; SI-NEXT: s_mov_b32 s10, 0147; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0148; SI-NEXT: v_mov_b32_e32 v1, 0149; SI-NEXT: s_mov_b32 s11, s7150; SI-NEXT: s_waitcnt lgkmcnt(0)151; SI-NEXT: s_mov_b64 s[8:9], s[2:3]152; SI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[8:11], 0 addr64153; SI-NEXT: s_mov_b32 s6, -1154; SI-NEXT: s_mov_b32 s4, s0155; SI-NEXT: s_mov_b32 s5, s1156; SI-NEXT: s_waitcnt vmcnt(0)157; SI-NEXT: v_ffbl_b32_e32 v1, v1158; SI-NEXT: v_ffbl_b32_e32 v0, v0159; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0160; SI-NEXT: s_endpgm161;162; VI-LABEL: v_cttz_zero_undef_v2i32:163; VI: ; %bb.0:164; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24165; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0166; VI-NEXT: s_waitcnt lgkmcnt(0)167; VI-NEXT: v_mov_b32_e32 v1, s3168; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0169; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc170; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]171; VI-NEXT: v_mov_b32_e32 v3, s1172; VI-NEXT: v_mov_b32_e32 v2, s0173; VI-NEXT: s_waitcnt vmcnt(0)174; VI-NEXT: v_ffbl_b32_e32 v1, v1175; VI-NEXT: v_ffbl_b32_e32 v0, v0176; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]177; VI-NEXT: s_endpgm178;179; EG-LABEL: v_cttz_zero_undef_v2i32:180; EG: ; %bb.0:181; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]182; EG-NEXT: TEX 0 @6183; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[]184; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1185; EG-NEXT: CF_END186; EG-NEXT: PAD187; EG-NEXT: Fetch clause starting at 6:188; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1189; EG-NEXT: ALU clause starting at 8:190; EG-NEXT: LSHL * T0.W, T0.X, literal.x,191; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)192; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,193; EG-NEXT: ALU clause starting at 11:194; EG-NEXT: FFBL_INT * T0.Y, T0.Y,195; EG-NEXT: FFBL_INT T0.X, T0.X,196; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,197; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)198;199; GFX9-GISEL-LABEL: v_cttz_zero_undef_v2i32:200; GFX9-GISEL: ; %bb.0:201; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24202; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 3, v0203; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0204; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)205; GFX9-GISEL-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3]206; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)207; GFX9-GISEL-NEXT: v_ffbl_b32_e32 v0, v0208; GFX9-GISEL-NEXT: v_ffbl_b32_e32 v1, v1209; GFX9-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]210; GFX9-GISEL-NEXT: s_endpgm211 %tid = call i32 @llvm.amdgcn.workitem.id.x()212 %in.gep = getelementptr <2 x i32>, ptr addrspace(1) %valptr, i32 %tid213 %val = load <2 x i32>, ptr addrspace(1) %in.gep, align 8214 %cttz = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %val, i1 true) nounwind readnone215 store <2 x i32> %cttz, ptr addrspace(1) %out, align 8216 ret void217}218 219define amdgpu_kernel void @v_cttz_zero_undef_v4i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {220; SI-LABEL: v_cttz_zero_undef_v4i32:221; SI: ; %bb.0:222; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9223; SI-NEXT: s_mov_b32 s7, 0xf000224; SI-NEXT: s_mov_b32 s10, 0225; SI-NEXT: v_lshlrev_b32_e32 v0, 4, v0226; SI-NEXT: v_mov_b32_e32 v1, 0227; SI-NEXT: s_mov_b32 s11, s7228; SI-NEXT: s_waitcnt lgkmcnt(0)229; SI-NEXT: s_mov_b64 s[8:9], s[2:3]230; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64231; SI-NEXT: s_mov_b32 s6, -1232; SI-NEXT: s_mov_b32 s4, s0233; SI-NEXT: s_mov_b32 s5, s1234; SI-NEXT: s_waitcnt vmcnt(0)235; SI-NEXT: v_ffbl_b32_e32 v3, v3236; SI-NEXT: v_ffbl_b32_e32 v2, v2237; SI-NEXT: v_ffbl_b32_e32 v1, v1238; SI-NEXT: v_ffbl_b32_e32 v0, v0239; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0240; SI-NEXT: s_endpgm241;242; VI-LABEL: v_cttz_zero_undef_v4i32:243; VI: ; %bb.0:244; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24245; VI-NEXT: v_lshlrev_b32_e32 v0, 4, v0246; VI-NEXT: s_waitcnt lgkmcnt(0)247; VI-NEXT: v_mov_b32_e32 v1, s3248; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0249; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc250; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]251; VI-NEXT: v_mov_b32_e32 v5, s1252; VI-NEXT: v_mov_b32_e32 v4, s0253; VI-NEXT: s_waitcnt vmcnt(0)254; VI-NEXT: v_ffbl_b32_e32 v3, v3255; VI-NEXT: v_ffbl_b32_e32 v2, v2256; VI-NEXT: v_ffbl_b32_e32 v1, v1257; VI-NEXT: v_ffbl_b32_e32 v0, v0258; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]259; VI-NEXT: s_endpgm260;261; EG-LABEL: v_cttz_zero_undef_v4i32:262; EG: ; %bb.0:263; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]264; EG-NEXT: TEX 0 @6265; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]266; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1267; EG-NEXT: CF_END268; EG-NEXT: PAD269; EG-NEXT: Fetch clause starting at 6:270; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1271; EG-NEXT: ALU clause starting at 8:272; EG-NEXT: LSHL * T0.W, T0.X, literal.x,273; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)274; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,275; EG-NEXT: ALU clause starting at 11:276; EG-NEXT: FFBL_INT * T0.W, T0.W,277; EG-NEXT: FFBL_INT * T0.Z, T0.Z,278; EG-NEXT: FFBL_INT * T0.Y, T0.Y,279; EG-NEXT: FFBL_INT T0.X, T0.X,280; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,281; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)282;283; GFX9-GISEL-LABEL: v_cttz_zero_undef_v4i32:284; GFX9-GISEL: ; %bb.0:285; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24286; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 4, v0287; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0288; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)289; GFX9-GISEL-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3]290; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)291; GFX9-GISEL-NEXT: v_ffbl_b32_e32 v0, v0292; GFX9-GISEL-NEXT: v_ffbl_b32_e32 v1, v1293; GFX9-GISEL-NEXT: v_ffbl_b32_e32 v2, v2294; GFX9-GISEL-NEXT: v_ffbl_b32_e32 v3, v3295; GFX9-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]296; GFX9-GISEL-NEXT: s_endpgm297 %tid = call i32 @llvm.amdgcn.workitem.id.x()298 %in.gep = getelementptr <4 x i32>, ptr addrspace(1) %valptr, i32 %tid299 %val = load <4 x i32>, ptr addrspace(1) %in.gep, align 16300 %cttz = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %val, i1 true) nounwind readnone301 store <4 x i32> %cttz, ptr addrspace(1) %out, align 16302 ret void303}304 305define amdgpu_kernel void @s_cttz_zero_undef_i8_with_select(ptr addrspace(1) noalias %out, i8 %val) nounwind {306; SI-LABEL: s_cttz_zero_undef_i8_with_select:307; SI: ; %bb.0:308; SI-NEXT: s_load_dword s2, s[4:5], 0xb309; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9310; SI-NEXT: s_mov_b32 s3, 0xf000311; SI-NEXT: s_waitcnt lgkmcnt(0)312; SI-NEXT: s_ff1_i32_b32 s4, s2313; SI-NEXT: s_mov_b32 s2, -1314; SI-NEXT: v_mov_b32_e32 v0, s4315; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0316; SI-NEXT: s_endpgm317;318; VI-LABEL: s_cttz_zero_undef_i8_with_select:319; VI: ; %bb.0:320; VI-NEXT: s_load_dword s2, s[4:5], 0x2c321; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24322; VI-NEXT: s_waitcnt lgkmcnt(0)323; VI-NEXT: s_ff1_i32_b32 s2, s2324; VI-NEXT: v_mov_b32_e32 v0, s0325; VI-NEXT: v_mov_b32_e32 v1, s1326; VI-NEXT: v_mov_b32_e32 v2, s2327; VI-NEXT: flat_store_byte v[0:1], v2328; VI-NEXT: s_endpgm329;330; EG-LABEL: s_cttz_zero_undef_i8_with_select:331; EG: ; %bb.0:332; EG-NEXT: ALU 0, @8, KC0[], KC1[]333; EG-NEXT: TEX 0 @6334; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[]335; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X336; EG-NEXT: CF_END337; EG-NEXT: PAD338; EG-NEXT: Fetch clause starting at 6:339; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3340; EG-NEXT: ALU clause starting at 8:341; EG-NEXT: MOV * T0.X, 0.0,342; EG-NEXT: ALU clause starting at 9:343; EG-NEXT: FFBL_INT T0.W, T0.X,344; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,345; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)346; EG-NEXT: AND_INT T0.W, PV.W, literal.x,347; EG-NEXT: LSHL * T1.W, PS, literal.y,348; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)349; EG-NEXT: LSHL T0.X, PV.W, PS,350; EG-NEXT: LSHL * T0.W, literal.x, PS,351; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)352; EG-NEXT: MOV T0.Y, 0.0,353; EG-NEXT: MOV * T0.Z, 0.0,354; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,355; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)356;357; GFX9-GISEL-LABEL: s_cttz_zero_undef_i8_with_select:358; GFX9-GISEL: ; %bb.0:359; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c360; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24361; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0362; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)363; GFX9-GISEL-NEXT: s_ff1_i32_b32 s2, s2364; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2365; GFX9-GISEL-NEXT: global_store_byte v1, v0, s[0:1]366; GFX9-GISEL-NEXT: s_endpgm367 %cttz = tail call i8 @llvm.cttz.i8(i8 %val, i1 true) nounwind readnone368 %cttz_ret = icmp ne i8 %val, 0369 %ret = select i1 %cttz_ret, i8 %cttz, i8 32370 store i8 %cttz, ptr addrspace(1) %out, align 4371 ret void372}373 374define amdgpu_kernel void @s_cttz_zero_undef_i16_with_select(ptr addrspace(1) noalias %out, i16 %val) nounwind {375; SI-LABEL: s_cttz_zero_undef_i16_with_select:376; SI: ; %bb.0:377; SI-NEXT: s_load_dword s2, s[4:5], 0xb378; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9379; SI-NEXT: s_mov_b32 s3, 0xf000380; SI-NEXT: s_waitcnt lgkmcnt(0)381; SI-NEXT: s_ff1_i32_b32 s4, s2382; SI-NEXT: s_mov_b32 s2, -1383; SI-NEXT: v_mov_b32_e32 v0, s4384; SI-NEXT: buffer_store_short v0, off, s[0:3], 0385; SI-NEXT: s_endpgm386;387; VI-LABEL: s_cttz_zero_undef_i16_with_select:388; VI: ; %bb.0:389; VI-NEXT: s_load_dword s2, s[4:5], 0x2c390; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24391; VI-NEXT: s_waitcnt lgkmcnt(0)392; VI-NEXT: s_ff1_i32_b32 s2, s2393; VI-NEXT: v_mov_b32_e32 v0, s0394; VI-NEXT: v_mov_b32_e32 v1, s1395; VI-NEXT: v_mov_b32_e32 v2, s2396; VI-NEXT: flat_store_short v[0:1], v2397; VI-NEXT: s_endpgm398;399; EG-LABEL: s_cttz_zero_undef_i16_with_select:400; EG: ; %bb.0:401; EG-NEXT: ALU 0, @8, KC0[], KC1[]402; EG-NEXT: TEX 0 @6403; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[]404; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X405; EG-NEXT: CF_END406; EG-NEXT: PAD407; EG-NEXT: Fetch clause starting at 6:408; EG-NEXT: VTX_READ_16 T0.X, T0.X, 40, #3409; EG-NEXT: ALU clause starting at 8:410; EG-NEXT: MOV * T0.X, 0.0,411; EG-NEXT: ALU clause starting at 9:412; EG-NEXT: FFBL_INT T0.W, T0.X,413; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,414; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)415; EG-NEXT: AND_INT T0.W, PV.W, literal.x,416; EG-NEXT: LSHL * T1.W, PS, literal.y,417; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)418; EG-NEXT: LSHL T0.X, PV.W, PS,419; EG-NEXT: LSHL * T0.W, literal.x, PS,420; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)421; EG-NEXT: MOV T0.Y, 0.0,422; EG-NEXT: MOV * T0.Z, 0.0,423; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,424; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)425;426; GFX9-GISEL-LABEL: s_cttz_zero_undef_i16_with_select:427; GFX9-GISEL: ; %bb.0:428; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c429; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24430; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0431; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)432; GFX9-GISEL-NEXT: s_ff1_i32_b32 s2, s2433; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2434; GFX9-GISEL-NEXT: global_store_short v1, v0, s[0:1]435; GFX9-GISEL-NEXT: s_endpgm436 %cttz = tail call i16 @llvm.cttz.i16(i16 %val, i1 true) nounwind readnone437 %cttz_ret = icmp ne i16 %val, 0438 %ret = select i1 %cttz_ret, i16 %cttz, i16 32439 store i16 %cttz, ptr addrspace(1) %out, align 4440 ret void441}442 443define amdgpu_kernel void @s_cttz_zero_undef_i32_with_select(ptr addrspace(1) noalias %out, i32 %val) nounwind {444; SI-LABEL: s_cttz_zero_undef_i32_with_select:445; SI: ; %bb.0:446; SI-NEXT: s_load_dword s2, s[4:5], 0xb447; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9448; SI-NEXT: s_mov_b32 s3, 0xf000449; SI-NEXT: s_waitcnt lgkmcnt(0)450; SI-NEXT: s_ff1_i32_b32 s4, s2451; SI-NEXT: s_mov_b32 s2, -1452; SI-NEXT: v_mov_b32_e32 v0, s4453; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0454; SI-NEXT: s_endpgm455;456; VI-LABEL: s_cttz_zero_undef_i32_with_select:457; VI: ; %bb.0:458; VI-NEXT: s_load_dword s2, s[4:5], 0x2c459; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24460; VI-NEXT: s_waitcnt lgkmcnt(0)461; VI-NEXT: s_ff1_i32_b32 s2, s2462; VI-NEXT: v_mov_b32_e32 v0, s0463; VI-NEXT: v_mov_b32_e32 v1, s1464; VI-NEXT: v_mov_b32_e32 v2, s2465; VI-NEXT: flat_store_dword v[0:1], v2466; VI-NEXT: s_endpgm467;468; EG-LABEL: s_cttz_zero_undef_i32_with_select:469; EG: ; %bb.0:470; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]471; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1472; EG-NEXT: CF_END473; EG-NEXT: PAD474; EG-NEXT: ALU clause starting at 4:475; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,476; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)477; EG-NEXT: FFBL_INT * T1.X, KC0[2].Z,478;479; GFX9-GISEL-LABEL: s_cttz_zero_undef_i32_with_select:480; GFX9-GISEL: ; %bb.0:481; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c482; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24483; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0484; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)485; GFX9-GISEL-NEXT: s_ff1_i32_b32 s2, s2486; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2487; GFX9-GISEL-NEXT: global_store_dword v1, v0, s[0:1]488; GFX9-GISEL-NEXT: s_endpgm489 %cttz = tail call i32 @llvm.cttz.i32(i32 %val, i1 true) nounwind readnone490 %cttz_ret = icmp ne i32 %val, 0491 %ret = select i1 %cttz_ret, i32 %cttz, i32 32492 store i32 %cttz, ptr addrspace(1) %out, align 4493 ret void494}495 496define amdgpu_kernel void @s_cttz_zero_undef_i64_with_select(ptr addrspace(1) noalias %out, i64 %val) nounwind {497; SI-LABEL: s_cttz_zero_undef_i64_with_select:498; SI: ; %bb.0:499; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9500; SI-NEXT: s_mov_b32 s7, 0xf000501; SI-NEXT: s_mov_b32 s6, -1502; SI-NEXT: s_waitcnt lgkmcnt(0)503; SI-NEXT: s_ff1_i32_b64 s2, s[2:3]504; SI-NEXT: v_mov_b32_e32 v1, 0505; SI-NEXT: s_mov_b32 s4, s0506; SI-NEXT: s_mov_b32 s5, s1507; SI-NEXT: v_mov_b32_e32 v0, s2508; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0509; SI-NEXT: s_endpgm510;511; VI-LABEL: s_cttz_zero_undef_i64_with_select:512; VI: ; %bb.0:513; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24514; VI-NEXT: v_mov_b32_e32 v1, 0515; VI-NEXT: s_waitcnt lgkmcnt(0)516; VI-NEXT: s_ff1_i32_b64 s2, s[2:3]517; VI-NEXT: v_mov_b32_e32 v3, s1518; VI-NEXT: v_mov_b32_e32 v0, s2519; VI-NEXT: v_mov_b32_e32 v2, s0520; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]521; VI-NEXT: s_endpgm522;523; EG-LABEL: s_cttz_zero_undef_i64_with_select:524; EG: ; %bb.0:525; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]526; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1527; EG-NEXT: CF_END528; EG-NEXT: PAD529; EG-NEXT: ALU clause starting at 4:530; EG-NEXT: FFBL_INT * T0.W, KC0[3].X,531; EG-NEXT: FFBL_INT T1.W, KC0[2].W,532; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,533; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)534; EG-NEXT: CNDE_INT T0.X, KC0[2].W, PS, PV.W,535; EG-NEXT: MOV T0.Y, 0.0,536; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,537; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)538;539; GFX9-GISEL-LABEL: s_cttz_zero_undef_i64_with_select:540; GFX9-GISEL: ; %bb.0:541; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24542; GFX9-GISEL-NEXT: s_mov_b32 s5, 0543; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0544; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)545; GFX9-GISEL-NEXT: s_ff1_i32_b64 s4, s[2:3]546; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s4547; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s5548; GFX9-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]549; GFX9-GISEL-NEXT: s_endpgm550 %cttz = tail call i64 @llvm.cttz.i64(i64 %val, i1 true) nounwind readnone551 %cttz_ret = icmp ne i64 %val, 0552 %ret = select i1 %cttz_ret, i64 %cttz, i64 32553 store i64 %cttz, ptr addrspace(1) %out, align 4554 ret void555}556 557define amdgpu_kernel void @v_cttz_zero_undef_i8_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {558; SI-LABEL: v_cttz_zero_undef_i8_with_select:559; SI: ; %bb.0:560; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9561; SI-NEXT: s_mov_b32 s7, 0xf000562; SI-NEXT: s_mov_b32 s6, -1563; SI-NEXT: s_mov_b32 s10, s6564; SI-NEXT: s_mov_b32 s11, s7565; SI-NEXT: s_waitcnt lgkmcnt(0)566; SI-NEXT: s_mov_b32 s8, s2567; SI-NEXT: s_mov_b32 s9, s3568; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0569; SI-NEXT: s_mov_b32 s4, s0570; SI-NEXT: s_mov_b32 s5, s1571; SI-NEXT: s_waitcnt vmcnt(0)572; SI-NEXT: v_ffbl_b32_e32 v1, v0573; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0574; SI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc575; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0576; SI-NEXT: s_endpgm577;578; VI-LABEL: v_cttz_zero_undef_i8_with_select:579; VI: ; %bb.0:580; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24581; VI-NEXT: s_waitcnt lgkmcnt(0)582; VI-NEXT: v_mov_b32_e32 v0, s2583; VI-NEXT: v_mov_b32_e32 v1, s3584; VI-NEXT: flat_load_ubyte v0, v[0:1]585; VI-NEXT: s_waitcnt vmcnt(0)586; VI-NEXT: v_ffbl_b32_e32 v1, v0587; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0588; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0589; VI-NEXT: v_cndmask_b32_e32 v2, 32, v1, vcc590; VI-NEXT: v_mov_b32_e32 v0, s0591; VI-NEXT: v_mov_b32_e32 v1, s1592; VI-NEXT: flat_store_byte v[0:1], v2593; VI-NEXT: s_endpgm594;595; EG-LABEL: v_cttz_zero_undef_i8_with_select:596; EG: ; %bb.0:597; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]598; EG-NEXT: TEX 0 @6599; EG-NEXT: ALU 14, @9, KC0[CB0:0-32], KC1[]600; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X601; EG-NEXT: CF_END602; EG-NEXT: PAD603; EG-NEXT: Fetch clause starting at 6:604; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1605; EG-NEXT: ALU clause starting at 8:606; EG-NEXT: MOV * T0.X, KC0[2].Z,607; EG-NEXT: ALU clause starting at 9:608; EG-NEXT: FFBL_INT T0.W, T0.X,609; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,610; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)611; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W,612; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)613; EG-NEXT: AND_INT T0.W, PV.W, literal.x,614; EG-NEXT: LSHL * T1.W, T1.W, literal.y,615; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)616; EG-NEXT: LSHL T0.X, PV.W, PS,617; EG-NEXT: LSHL * T0.W, literal.x, PS,618; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)619; EG-NEXT: MOV T0.Y, 0.0,620; EG-NEXT: MOV * T0.Z, 0.0,621; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,622; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)623;624; GFX9-GISEL-LABEL: v_cttz_zero_undef_i8_with_select:625; GFX9-GISEL: ; %bb.0:626; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24627; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0628; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)629; GFX9-GISEL-NEXT: global_load_ubyte v1, v0, s[2:3]630; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)631; GFX9-GISEL-NEXT: v_ffbl_b32_e32 v2, v1632; GFX9-GISEL-NEXT: v_cmp_ne_u32_sdwa vcc, v1, v0 src0_sel:BYTE_0 src1_sel:DWORD633; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, 32, v2, vcc634; GFX9-GISEL-NEXT: global_store_byte v0, v1, s[0:1]635; GFX9-GISEL-NEXT: s_endpgm636 %val = load i8, ptr addrspace(1) %arrayidx, align 1637 %cttz = tail call i8 @llvm.cttz.i8(i8 %val, i1 true) nounwind readnone638 %cttz_ret = icmp ne i8 %val, 0639 %ret = select i1 %cttz_ret, i8 %cttz, i8 32640 store i8 %ret, ptr addrspace(1) %out, align 4641 ret void642}643 644define amdgpu_kernel void @v_cttz_zero_undef_i16_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {645; SI-LABEL: v_cttz_zero_undef_i16_with_select:646; SI: ; %bb.0:647; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9648; SI-NEXT: s_mov_b32 s7, 0xf000649; SI-NEXT: s_mov_b32 s6, -1650; SI-NEXT: s_mov_b32 s10, s6651; SI-NEXT: s_mov_b32 s11, s7652; SI-NEXT: s_waitcnt lgkmcnt(0)653; SI-NEXT: s_mov_b32 s8, s2654; SI-NEXT: s_mov_b32 s9, s3655; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:1656; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0657; SI-NEXT: s_mov_b32 s4, s0658; SI-NEXT: s_mov_b32 s5, s1659; SI-NEXT: s_waitcnt vmcnt(1)660; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0661; SI-NEXT: s_waitcnt vmcnt(0)662; SI-NEXT: v_or_b32_e32 v0, v0, v1663; SI-NEXT: v_ffbl_b32_e32 v1, v0664; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0665; SI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc666; SI-NEXT: buffer_store_short v0, off, s[4:7], 0667; SI-NEXT: s_endpgm668;669; VI-LABEL: v_cttz_zero_undef_i16_with_select:670; VI: ; %bb.0:671; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24672; VI-NEXT: s_waitcnt lgkmcnt(0)673; VI-NEXT: s_add_u32 s4, s2, 1674; VI-NEXT: s_addc_u32 s5, s3, 0675; VI-NEXT: v_mov_b32_e32 v2, s4676; VI-NEXT: v_mov_b32_e32 v0, s2677; VI-NEXT: v_mov_b32_e32 v3, s5678; VI-NEXT: v_mov_b32_e32 v1, s3679; VI-NEXT: flat_load_ubyte v2, v[2:3]680; VI-NEXT: flat_load_ubyte v0, v[0:1]681; VI-NEXT: s_waitcnt vmcnt(1)682; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v2683; VI-NEXT: s_waitcnt vmcnt(0)684; VI-NEXT: v_or_b32_e32 v0, v1, v0685; VI-NEXT: v_ffbl_b32_e32 v1, v0686; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0687; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0688; VI-NEXT: v_cndmask_b32_e32 v2, 32, v1, vcc689; VI-NEXT: v_mov_b32_e32 v0, s0690; VI-NEXT: v_mov_b32_e32 v1, s1691; VI-NEXT: flat_store_short v[0:1], v2692; VI-NEXT: s_endpgm693;694; EG-LABEL: v_cttz_zero_undef_i16_with_select:695; EG: ; %bb.0:696; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]697; EG-NEXT: TEX 0 @6698; EG-NEXT: ALU 14, @9, KC0[CB0:0-32], KC1[]699; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X700; EG-NEXT: CF_END701; EG-NEXT: PAD702; EG-NEXT: Fetch clause starting at 6:703; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #1704; EG-NEXT: ALU clause starting at 8:705; EG-NEXT: MOV * T0.X, KC0[2].Z,706; EG-NEXT: ALU clause starting at 9:707; EG-NEXT: FFBL_INT T0.W, T0.X,708; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,709; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)710; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W,711; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)712; EG-NEXT: AND_INT T0.W, PV.W, literal.x,713; EG-NEXT: LSHL * T1.W, T1.W, literal.y,714; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)715; EG-NEXT: LSHL T0.X, PV.W, PS,716; EG-NEXT: LSHL * T0.W, literal.x, PS,717; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)718; EG-NEXT: MOV T0.Y, 0.0,719; EG-NEXT: MOV * T0.Z, 0.0,720; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,721; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)722;723; GFX9-GISEL-LABEL: v_cttz_zero_undef_i16_with_select:724; GFX9-GISEL: ; %bb.0:725; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24726; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0727; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)728; GFX9-GISEL-NEXT: global_load_ubyte v1, v0, s[2:3]729; GFX9-GISEL-NEXT: global_load_ubyte v2, v0, s[2:3] offset:1730; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)731; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, v2, 8, v1732; GFX9-GISEL-NEXT: v_ffbl_b32_e32 v2, v1733; GFX9-GISEL-NEXT: v_cmp_ne_u16_e32 vcc, 0, v1734; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, 32, v2, vcc735; GFX9-GISEL-NEXT: global_store_short v0, v1, s[0:1]736; GFX9-GISEL-NEXT: s_endpgm737 %val = load i16, ptr addrspace(1) %arrayidx, align 1738 %cttz = tail call i16 @llvm.cttz.i16(i16 %val, i1 true) nounwind readnone739 %cttz_ret = icmp ne i16 %val, 0740 %ret = select i1 %cttz_ret, i16 %cttz, i16 32741 store i16 %ret, ptr addrspace(1) %out, align 4742 ret void743}744 745define amdgpu_kernel void @v_cttz_zero_undef_i32_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {746; SI-LABEL: v_cttz_zero_undef_i32_with_select:747; SI: ; %bb.0:748; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9749; SI-NEXT: s_mov_b32 s7, 0xf000750; SI-NEXT: s_mov_b32 s6, -1751; SI-NEXT: s_mov_b32 s10, s6752; SI-NEXT: s_mov_b32 s11, s7753; SI-NEXT: s_waitcnt lgkmcnt(0)754; SI-NEXT: s_mov_b32 s8, s2755; SI-NEXT: s_mov_b32 s9, s3756; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:1757; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:3758; SI-NEXT: buffer_load_ubyte v2, off, s[8:11], 0759; SI-NEXT: buffer_load_ubyte v3, off, s[8:11], 0 offset:2760; SI-NEXT: s_mov_b32 s4, s0761; SI-NEXT: s_mov_b32 s5, s1762; SI-NEXT: s_waitcnt vmcnt(3)763; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0764; SI-NEXT: s_waitcnt vmcnt(2)765; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1766; SI-NEXT: s_waitcnt vmcnt(1)767; SI-NEXT: v_or_b32_e32 v0, v0, v2768; SI-NEXT: s_waitcnt vmcnt(0)769; SI-NEXT: v_or_b32_e32 v1, v1, v3770; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1771; SI-NEXT: v_or_b32_e32 v0, v1, v0772; SI-NEXT: v_ffbl_b32_e32 v0, v0773; SI-NEXT: v_min_u32_e32 v0, 32, v0774; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0775; SI-NEXT: s_endpgm776;777; VI-LABEL: v_cttz_zero_undef_i32_with_select:778; VI: ; %bb.0:779; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24780; VI-NEXT: s_waitcnt lgkmcnt(0)781; VI-NEXT: s_add_u32 s4, s2, 3782; VI-NEXT: s_addc_u32 s5, s3, 0783; VI-NEXT: v_mov_b32_e32 v2, s4784; VI-NEXT: v_mov_b32_e32 v3, s5785; VI-NEXT: s_add_u32 s4, s2, 2786; VI-NEXT: v_mov_b32_e32 v0, s2787; VI-NEXT: s_addc_u32 s5, s3, 0788; VI-NEXT: v_mov_b32_e32 v1, s3789; VI-NEXT: s_add_u32 s2, s2, 1790; VI-NEXT: s_addc_u32 s3, s3, 0791; VI-NEXT: v_mov_b32_e32 v4, s4792; VI-NEXT: v_mov_b32_e32 v7, s3793; VI-NEXT: v_mov_b32_e32 v5, s5794; VI-NEXT: v_mov_b32_e32 v6, s2795; VI-NEXT: flat_load_ubyte v2, v[2:3]796; VI-NEXT: flat_load_ubyte v3, v[4:5]797; VI-NEXT: flat_load_ubyte v4, v[6:7]798; VI-NEXT: flat_load_ubyte v0, v[0:1]799; VI-NEXT: s_waitcnt vmcnt(3)800; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v2801; VI-NEXT: s_waitcnt vmcnt(2)802; VI-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD803; VI-NEXT: s_waitcnt vmcnt(1)804; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v4805; VI-NEXT: s_waitcnt vmcnt(0)806; VI-NEXT: v_or_b32_e32 v0, v2, v0807; VI-NEXT: v_or_b32_e32 v0, v1, v0808; VI-NEXT: v_ffbl_b32_e32 v0, v0809; VI-NEXT: v_min_u32_e32 v2, 32, v0810; VI-NEXT: v_mov_b32_e32 v0, s0811; VI-NEXT: v_mov_b32_e32 v1, s1812; VI-NEXT: flat_store_dword v[0:1], v2813; VI-NEXT: s_endpgm814;815; EG-LABEL: v_cttz_zero_undef_i32_with_select:816; EG: ; %bb.0:817; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]818; EG-NEXT: TEX 1 @6819; EG-NEXT: ALU 6, @11, KC0[CB0:0-32], KC1[]820; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1821; EG-NEXT: CF_END822; EG-NEXT: PAD823; EG-NEXT: Fetch clause starting at 6:824; EG-NEXT: VTX_READ_16 T1.X, T0.X, 2, #1825; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #1826; EG-NEXT: ALU clause starting at 10:827; EG-NEXT: MOV * T0.X, KC0[2].Z,828; EG-NEXT: ALU clause starting at 11:829; EG-NEXT: LSHL * T0.W, T1.X, literal.x,830; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)831; EG-NEXT: OR_INT * T0.W, PV.W, T0.X,832; EG-NEXT: FFBL_INT * T1.W, PV.W,833; EG-NEXT: CNDE_INT T0.X, T0.W, literal.x, PV.W,834; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,835; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45)836;837; GFX9-GISEL-LABEL: v_cttz_zero_undef_i32_with_select:838; GFX9-GISEL: ; %bb.0:839; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24840; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0841; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)842; GFX9-GISEL-NEXT: global_load_ubyte v1, v0, s[2:3]843; GFX9-GISEL-NEXT: global_load_ubyte v2, v0, s[2:3] offset:1844; GFX9-GISEL-NEXT: global_load_ubyte v3, v0, s[2:3] offset:3845; GFX9-GISEL-NEXT: global_load_ubyte v4, v0, s[2:3] offset:2846; GFX9-GISEL-NEXT: s_waitcnt vmcnt(2)847; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, v2, 8, v1848; GFX9-GISEL-NEXT: s_waitcnt vmcnt(1)849; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v3850; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)851; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v4852; GFX9-GISEL-NEXT: v_or3_b32 v1, v2, v3, v1853; GFX9-GISEL-NEXT: v_ffbl_b32_e32 v2, v1854; GFX9-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1855; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, 32, v2, vcc856; GFX9-GISEL-NEXT: global_store_dword v0, v1, s[0:1]857; GFX9-GISEL-NEXT: s_endpgm858 %val = load i32, ptr addrspace(1) %arrayidx, align 1859 %cttz = tail call i32 @llvm.cttz.i32(i32 %val, i1 true) nounwind readnone860 %cttz_ret = icmp ne i32 %val, 0861 %ret = select i1 %cttz_ret, i32 %cttz, i32 32862 store i32 %ret, ptr addrspace(1) %out, align 4863 ret void864}865 866define amdgpu_kernel void @v_cttz_zero_undef_i64_with_select(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {867; SI-LABEL: v_cttz_zero_undef_i64_with_select:868; SI: ; %bb.0:869; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9870; SI-NEXT: s_mov_b32 s3, 0xf000871; SI-NEXT: s_mov_b32 s2, -1872; SI-NEXT: s_mov_b32 s10, s2873; SI-NEXT: s_mov_b32 s11, s3874; SI-NEXT: s_waitcnt lgkmcnt(0)875; SI-NEXT: s_mov_b32 s8, s6876; SI-NEXT: s_mov_b32 s9, s7877; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0878; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:1879; SI-NEXT: buffer_load_ubyte v2, off, s[8:11], 0 offset:2880; SI-NEXT: buffer_load_ubyte v3, off, s[8:11], 0 offset:3881; SI-NEXT: buffer_load_ubyte v4, off, s[8:11], 0 offset:5882; SI-NEXT: buffer_load_ubyte v5, off, s[8:11], 0 offset:7883; SI-NEXT: buffer_load_ubyte v6, off, s[8:11], 0 offset:4884; SI-NEXT: buffer_load_ubyte v7, off, s[8:11], 0 offset:6885; SI-NEXT: s_mov_b32 s0, s4886; SI-NEXT: s_mov_b32 s1, s5887; SI-NEXT: s_waitcnt vmcnt(3)888; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4889; SI-NEXT: s_waitcnt vmcnt(2)890; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5891; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1892; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3893; SI-NEXT: s_waitcnt vmcnt(1)894; SI-NEXT: v_or_b32_e32 v4, v4, v6895; SI-NEXT: s_waitcnt vmcnt(0)896; SI-NEXT: v_or_b32_e32 v5, v5, v7897; SI-NEXT: v_or_b32_e32 v0, v1, v0898; SI-NEXT: v_or_b32_e32 v1, v3, v2899; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v5900; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1901; SI-NEXT: v_or_b32_e32 v2, v2, v4902; SI-NEXT: v_or_b32_e32 v0, v1, v0903; SI-NEXT: v_ffbl_b32_e32 v0, v0904; SI-NEXT: v_ffbl_b32_e32 v1, v2905; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v1906; SI-NEXT: v_min_u32_e32 v0, v1, v0907; SI-NEXT: v_min_u32_e32 v0, 64, v0908; SI-NEXT: v_mov_b32_e32 v1, 0909; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0910; SI-NEXT: s_endpgm911;912; VI-LABEL: v_cttz_zero_undef_i64_with_select:913; VI: ; %bb.0:914; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24915; VI-NEXT: s_waitcnt lgkmcnt(0)916; VI-NEXT: s_add_u32 s4, s2, 5917; VI-NEXT: s_addc_u32 s5, s3, 0918; VI-NEXT: v_mov_b32_e32 v0, s4919; VI-NEXT: v_mov_b32_e32 v1, s5920; VI-NEXT: s_add_u32 s4, s2, 4921; VI-NEXT: s_addc_u32 s5, s3, 0922; VI-NEXT: v_mov_b32_e32 v2, s4923; VI-NEXT: v_mov_b32_e32 v3, s5924; VI-NEXT: s_add_u32 s4, s2, 7925; VI-NEXT: s_addc_u32 s5, s3, 0926; VI-NEXT: v_mov_b32_e32 v4, s4927; VI-NEXT: v_mov_b32_e32 v5, s5928; VI-NEXT: s_add_u32 s4, s2, 6929; VI-NEXT: s_addc_u32 s5, s3, 0930; VI-NEXT: v_mov_b32_e32 v7, s5931; VI-NEXT: v_mov_b32_e32 v6, s4932; VI-NEXT: s_add_u32 s4, s2, 3933; VI-NEXT: s_addc_u32 s5, s3, 0934; VI-NEXT: v_mov_b32_e32 v9, s5935; VI-NEXT: v_mov_b32_e32 v8, s4936; VI-NEXT: s_add_u32 s4, s2, 2937; VI-NEXT: flat_load_ubyte v10, v[0:1]938; VI-NEXT: flat_load_ubyte v11, v[2:3]939; VI-NEXT: flat_load_ubyte v12, v[4:5]940; VI-NEXT: flat_load_ubyte v6, v[6:7]941; VI-NEXT: flat_load_ubyte v7, v[8:9]942; VI-NEXT: s_addc_u32 s5, s3, 0943; VI-NEXT: v_mov_b32_e32 v0, s4944; VI-NEXT: v_mov_b32_e32 v1, s5945; VI-NEXT: s_add_u32 s4, s2, 1946; VI-NEXT: s_addc_u32 s5, s3, 0947; VI-NEXT: v_mov_b32_e32 v2, s4948; VI-NEXT: v_mov_b32_e32 v3, s5949; VI-NEXT: v_mov_b32_e32 v5, s3950; VI-NEXT: v_mov_b32_e32 v4, s2951; VI-NEXT: flat_load_ubyte v0, v[0:1]952; VI-NEXT: flat_load_ubyte v2, v[2:3]953; VI-NEXT: flat_load_ubyte v3, v[4:5]954; VI-NEXT: v_mov_b32_e32 v1, 0955; VI-NEXT: s_waitcnt vmcnt(7)956; VI-NEXT: v_lshlrev_b32_e32 v4, 8, v10957; VI-NEXT: s_waitcnt vmcnt(6)958; VI-NEXT: v_or_b32_e32 v4, v4, v11959; VI-NEXT: s_waitcnt vmcnt(5)960; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v12961; VI-NEXT: s_waitcnt vmcnt(4)962; VI-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD963; VI-NEXT: v_or_b32_e32 v4, v5, v4964; VI-NEXT: s_waitcnt vmcnt(3)965; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v7966; VI-NEXT: v_ffbl_b32_e32 v4, v4967; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v4968; VI-NEXT: s_waitcnt vmcnt(2)969; VI-NEXT: v_or_b32_sdwa v0, v5, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD970; VI-NEXT: s_waitcnt vmcnt(1)971; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2972; VI-NEXT: s_waitcnt vmcnt(0)973; VI-NEXT: v_or_b32_e32 v2, v2, v3974; VI-NEXT: v_or_b32_e32 v0, v0, v2975; VI-NEXT: v_ffbl_b32_e32 v0, v0976; VI-NEXT: v_min_u32_e32 v0, v4, v0977; VI-NEXT: v_mov_b32_e32 v3, s1978; VI-NEXT: v_min_u32_e32 v0, 64, v0979; VI-NEXT: v_mov_b32_e32 v2, s0980; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]981; VI-NEXT: s_endpgm982;983; EG-LABEL: v_cttz_zero_undef_i64_with_select:984; EG: ; %bb.0:985; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]986; EG-NEXT: TEX 3 @6987; EG-NEXT: ALU 15, @15, KC0[CB0:0-32], KC1[]988; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1989; EG-NEXT: CF_END990; EG-NEXT: PAD991; EG-NEXT: Fetch clause starting at 6:992; EG-NEXT: VTX_READ_16 T1.X, T0.X, 6, #1993; EG-NEXT: VTX_READ_16 T2.X, T0.X, 0, #1994; EG-NEXT: VTX_READ_16 T3.X, T0.X, 2, #1995; EG-NEXT: VTX_READ_16 T0.X, T0.X, 4, #1996; EG-NEXT: ALU clause starting at 14:997; EG-NEXT: MOV * T0.X, KC0[2].Z,998; EG-NEXT: ALU clause starting at 15:999; EG-NEXT: LSHL * T0.W, T1.X, literal.x,1000; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)1001; EG-NEXT: OR_INT * T0.W, PV.W, T0.X,1002; EG-NEXT: FFBL_INT T1.W, PV.W,1003; EG-NEXT: LSHL * T2.W, T3.X, literal.x,1004; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)1005; EG-NEXT: CNDE_INT T0.W, T0.W, literal.x, PV.W,1006; EG-NEXT: OR_INT * T1.W, PS, T2.X,1007; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1008; EG-NEXT: FFBL_INT T2.W, PS,1009; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,1010; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1011; EG-NEXT: CNDE_INT T0.X, T1.W, PS, PV.W,1012; EG-NEXT: MOV T0.Y, 0.0,1013; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1014; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1015;1016; GFX9-GISEL-LABEL: v_cttz_zero_undef_i64_with_select:1017; GFX9-GISEL: ; %bb.0:1018; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241019; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 01020; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)1021; GFX9-GISEL-NEXT: global_load_ubyte v0, v1, s[2:3]1022; GFX9-GISEL-NEXT: global_load_ubyte v2, v1, s[2:3] offset:11023; GFX9-GISEL-NEXT: global_load_ubyte v3, v1, s[2:3] offset:21024; GFX9-GISEL-NEXT: global_load_ubyte v4, v1, s[2:3] offset:31025; GFX9-GISEL-NEXT: global_load_ubyte v5, v1, s[2:3] offset:41026; GFX9-GISEL-NEXT: global_load_ubyte v6, v1, s[2:3] offset:51027; GFX9-GISEL-NEXT: global_load_ubyte v7, v1, s[2:3] offset:71028; GFX9-GISEL-NEXT: global_load_ubyte v8, v1, s[2:3] offset:61029; GFX9-GISEL-NEXT: s_waitcnt vmcnt(6)1030; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v2, 8, v01031; GFX9-GISEL-NEXT: s_waitcnt vmcnt(5)1032; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v31033; GFX9-GISEL-NEXT: s_waitcnt vmcnt(4)1034; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v41035; GFX9-GISEL-NEXT: v_or3_b32 v2, v2, v3, v01036; GFX9-GISEL-NEXT: s_waitcnt vmcnt(2)1037; GFX9-GISEL-NEXT: v_lshl_or_b32 v4, v6, 8, v51038; GFX9-GISEL-NEXT: s_waitcnt vmcnt(1)1039; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v5, 24, v71040; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)1041; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v6, 16, v81042; GFX9-GISEL-NEXT: v_or3_b32 v3, v5, v6, v41043; GFX9-GISEL-NEXT: v_ffbl_b32_e32 v4, v31044; GFX9-GISEL-NEXT: v_ffbl_b32_e32 v0, v21045; GFX9-GISEL-NEXT: v_add_u32_e32 v4, 32, v41046; GFX9-GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]1047; GFX9-GISEL-NEXT: v_min_u32_e32 v0, v0, v41048; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 64, v0, vcc1049; GFX9-GISEL-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]1050; GFX9-GISEL-NEXT: s_endpgm1051 %val = load i64, ptr addrspace(1) %arrayidx, align 11052 %cttz = tail call i64 @llvm.cttz.i64(i64 %val, i1 true) nounwind readnone1053 %cttz_ret = icmp ne i64 %val, 01054 %ret = select i1 %cttz_ret, i64 %cttz, i64 641055 store i64 %ret, ptr addrspace(1) %out, align 41056 ret void1057}1058 1059define amdgpu_kernel void @v_cttz_i32_sel_eq_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {1060; SI-LABEL: v_cttz_i32_sel_eq_neg1:1061; SI: ; %bb.0:1062; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91063; SI-NEXT: s_mov_b32 s7, 0xf0001064; SI-NEXT: s_mov_b32 s6, -11065; SI-NEXT: s_mov_b32 s10, s61066; SI-NEXT: s_mov_b32 s11, s71067; SI-NEXT: s_waitcnt lgkmcnt(0)1068; SI-NEXT: s_mov_b32 s8, s21069; SI-NEXT: s_mov_b32 s9, s31070; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:11071; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:31072; SI-NEXT: buffer_load_ubyte v2, off, s[8:11], 01073; SI-NEXT: buffer_load_ubyte v3, off, s[8:11], 0 offset:21074; SI-NEXT: s_mov_b32 s4, s01075; SI-NEXT: s_mov_b32 s5, s11076; SI-NEXT: s_waitcnt vmcnt(3)1077; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v01078; SI-NEXT: s_waitcnt vmcnt(2)1079; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v11080; SI-NEXT: s_waitcnt vmcnt(1)1081; SI-NEXT: v_or_b32_e32 v0, v0, v21082; SI-NEXT: s_waitcnt vmcnt(0)1083; SI-NEXT: v_or_b32_e32 v1, v1, v31084; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v11085; SI-NEXT: v_or_b32_e32 v0, v1, v01086; SI-NEXT: v_ffbl_b32_e32 v0, v01087; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01088; SI-NEXT: s_endpgm1089;1090; VI-LABEL: v_cttz_i32_sel_eq_neg1:1091; VI: ; %bb.0:1092; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241093; VI-NEXT: s_waitcnt lgkmcnt(0)1094; VI-NEXT: s_add_u32 s4, s2, 31095; VI-NEXT: s_addc_u32 s5, s3, 01096; VI-NEXT: v_mov_b32_e32 v2, s41097; VI-NEXT: v_mov_b32_e32 v3, s51098; VI-NEXT: s_add_u32 s4, s2, 21099; VI-NEXT: v_mov_b32_e32 v0, s21100; VI-NEXT: s_addc_u32 s5, s3, 01101; VI-NEXT: v_mov_b32_e32 v1, s31102; VI-NEXT: s_add_u32 s2, s2, 11103; VI-NEXT: s_addc_u32 s3, s3, 01104; VI-NEXT: v_mov_b32_e32 v4, s41105; VI-NEXT: v_mov_b32_e32 v7, s31106; VI-NEXT: v_mov_b32_e32 v5, s51107; VI-NEXT: v_mov_b32_e32 v6, s21108; VI-NEXT: flat_load_ubyte v2, v[2:3]1109; VI-NEXT: flat_load_ubyte v3, v[4:5]1110; VI-NEXT: flat_load_ubyte v4, v[6:7]1111; VI-NEXT: flat_load_ubyte v0, v[0:1]1112; VI-NEXT: s_waitcnt vmcnt(3)1113; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v21114; VI-NEXT: s_waitcnt vmcnt(2)1115; VI-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1116; VI-NEXT: s_waitcnt vmcnt(1)1117; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v41118; VI-NEXT: s_waitcnt vmcnt(0)1119; VI-NEXT: v_or_b32_e32 v0, v2, v01120; VI-NEXT: v_or_b32_e32 v0, v1, v01121; VI-NEXT: v_ffbl_b32_e32 v2, v01122; VI-NEXT: v_mov_b32_e32 v0, s01123; VI-NEXT: v_mov_b32_e32 v1, s11124; VI-NEXT: flat_store_dword v[0:1], v21125; VI-NEXT: s_endpgm1126;1127; EG-LABEL: v_cttz_i32_sel_eq_neg1:1128; EG: ; %bb.0:1129; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]1130; EG-NEXT: TEX 1 @61131; EG-NEXT: ALU 8, @11, KC0[CB0:0-32], KC1[]1132; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11133; EG-NEXT: CF_END1134; EG-NEXT: PAD1135; EG-NEXT: Fetch clause starting at 6:1136; EG-NEXT: VTX_READ_16 T1.X, T0.X, 2, #11137; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #11138; EG-NEXT: ALU clause starting at 10:1139; EG-NEXT: MOV * T0.X, KC0[2].Z,1140; EG-NEXT: ALU clause starting at 11:1141; EG-NEXT: LSHL * T0.W, T1.X, literal.x,1142; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)1143; EG-NEXT: OR_INT * T0.W, PV.W, T0.X,1144; EG-NEXT: FFBL_INT * T1.W, PV.W,1145; EG-NEXT: CNDE_INT * T1.W, T0.W, literal.x, PV.W,1146; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1147; EG-NEXT: CNDE_INT T0.X, T0.W, literal.x, PV.W,1148; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,1149; EG-NEXT: -1(nan), 2(2.802597e-45)1150;1151; GFX9-GISEL-LABEL: v_cttz_i32_sel_eq_neg1:1152; GFX9-GISEL: ; %bb.0:1153; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241154; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 01155; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)1156; GFX9-GISEL-NEXT: global_load_ubyte v1, v0, s[2:3]1157; GFX9-GISEL-NEXT: global_load_ubyte v2, v0, s[2:3] offset:11158; GFX9-GISEL-NEXT: global_load_ubyte v3, v0, s[2:3] offset:31159; GFX9-GISEL-NEXT: global_load_ubyte v4, v0, s[2:3] offset:21160; GFX9-GISEL-NEXT: s_waitcnt vmcnt(2)1161; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, v2, 8, v11162; GFX9-GISEL-NEXT: s_waitcnt vmcnt(1)1163; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v31164; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)1165; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v41166; GFX9-GISEL-NEXT: v_or3_b32 v1, v2, v3, v11167; GFX9-GISEL-NEXT: v_ffbl_b32_e32 v2, v11168; GFX9-GISEL-NEXT: v_min_u32_e32 v2, 32, v21169; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v11170; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, v2, -1, vcc1171; GFX9-GISEL-NEXT: global_store_dword v0, v1, s[0:1]1172; GFX9-GISEL-NEXT: s_endpgm1173 %val = load i32, ptr addrspace(1) %arrayidx, align 11174 %ctlz = call i32 @llvm.cttz.i32(i32 %val, i1 false) nounwind readnone1175 %cmp = icmp eq i32 %val, 01176 %sel = select i1 %cmp, i32 -1, i32 %ctlz1177 store i32 %sel, ptr addrspace(1) %out1178 ret void1179}1180 1181define amdgpu_kernel void @v_cttz_i32_sel_ne_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {1182; SI-LABEL: v_cttz_i32_sel_ne_neg1:1183; SI: ; %bb.0:1184; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91185; SI-NEXT: s_mov_b32 s7, 0xf0001186; SI-NEXT: s_mov_b32 s6, -11187; SI-NEXT: s_mov_b32 s10, s61188; SI-NEXT: s_mov_b32 s11, s71189; SI-NEXT: s_waitcnt lgkmcnt(0)1190; SI-NEXT: s_mov_b32 s8, s21191; SI-NEXT: s_mov_b32 s9, s31192; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:11193; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:31194; SI-NEXT: buffer_load_ubyte v2, off, s[8:11], 01195; SI-NEXT: buffer_load_ubyte v3, off, s[8:11], 0 offset:21196; SI-NEXT: s_mov_b32 s4, s01197; SI-NEXT: s_mov_b32 s5, s11198; SI-NEXT: s_waitcnt vmcnt(3)1199; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v01200; SI-NEXT: s_waitcnt vmcnt(2)1201; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v11202; SI-NEXT: s_waitcnt vmcnt(1)1203; SI-NEXT: v_or_b32_e32 v0, v0, v21204; SI-NEXT: s_waitcnt vmcnt(0)1205; SI-NEXT: v_or_b32_e32 v1, v1, v31206; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v11207; SI-NEXT: v_or_b32_e32 v0, v1, v01208; SI-NEXT: v_ffbl_b32_e32 v0, v01209; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01210; SI-NEXT: s_endpgm1211;1212; VI-LABEL: v_cttz_i32_sel_ne_neg1:1213; VI: ; %bb.0:1214; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241215; VI-NEXT: s_waitcnt lgkmcnt(0)1216; VI-NEXT: s_add_u32 s4, s2, 31217; VI-NEXT: s_addc_u32 s5, s3, 01218; VI-NEXT: v_mov_b32_e32 v2, s41219; VI-NEXT: v_mov_b32_e32 v3, s51220; VI-NEXT: s_add_u32 s4, s2, 21221; VI-NEXT: v_mov_b32_e32 v0, s21222; VI-NEXT: s_addc_u32 s5, s3, 01223; VI-NEXT: v_mov_b32_e32 v1, s31224; VI-NEXT: s_add_u32 s2, s2, 11225; VI-NEXT: s_addc_u32 s3, s3, 01226; VI-NEXT: v_mov_b32_e32 v4, s41227; VI-NEXT: v_mov_b32_e32 v7, s31228; VI-NEXT: v_mov_b32_e32 v5, s51229; VI-NEXT: v_mov_b32_e32 v6, s21230; VI-NEXT: flat_load_ubyte v2, v[2:3]1231; VI-NEXT: flat_load_ubyte v3, v[4:5]1232; VI-NEXT: flat_load_ubyte v4, v[6:7]1233; VI-NEXT: flat_load_ubyte v0, v[0:1]1234; VI-NEXT: s_waitcnt vmcnt(3)1235; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v21236; VI-NEXT: s_waitcnt vmcnt(2)1237; VI-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1238; VI-NEXT: s_waitcnt vmcnt(1)1239; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v41240; VI-NEXT: s_waitcnt vmcnt(0)1241; VI-NEXT: v_or_b32_e32 v0, v2, v01242; VI-NEXT: v_or_b32_e32 v0, v1, v01243; VI-NEXT: v_ffbl_b32_e32 v2, v01244; VI-NEXT: v_mov_b32_e32 v0, s01245; VI-NEXT: v_mov_b32_e32 v1, s11246; VI-NEXT: flat_store_dword v[0:1], v21247; VI-NEXT: s_endpgm1248;1249; EG-LABEL: v_cttz_i32_sel_ne_neg1:1250; EG: ; %bb.0:1251; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]1252; EG-NEXT: TEX 1 @61253; EG-NEXT: ALU 8, @11, KC0[CB0:0-32], KC1[]1254; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11255; EG-NEXT: CF_END1256; EG-NEXT: PAD1257; EG-NEXT: Fetch clause starting at 6:1258; EG-NEXT: VTX_READ_16 T1.X, T0.X, 2, #11259; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #11260; EG-NEXT: ALU clause starting at 10:1261; EG-NEXT: MOV * T0.X, KC0[2].Z,1262; EG-NEXT: ALU clause starting at 11:1263; EG-NEXT: LSHL * T0.W, T1.X, literal.x,1264; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)1265; EG-NEXT: OR_INT * T0.W, PV.W, T0.X,1266; EG-NEXT: FFBL_INT * T1.W, PV.W,1267; EG-NEXT: CNDE_INT * T1.W, T0.W, literal.x, PV.W,1268; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1269; EG-NEXT: CNDE_INT T0.X, T0.W, literal.x, PV.W,1270; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,1271; EG-NEXT: -1(nan), 2(2.802597e-45)1272;1273; GFX9-GISEL-LABEL: v_cttz_i32_sel_ne_neg1:1274; GFX9-GISEL: ; %bb.0:1275; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241276; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 01277; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)1278; GFX9-GISEL-NEXT: global_load_ubyte v1, v0, s[2:3]1279; GFX9-GISEL-NEXT: global_load_ubyte v2, v0, s[2:3] offset:11280; GFX9-GISEL-NEXT: global_load_ubyte v3, v0, s[2:3] offset:31281; GFX9-GISEL-NEXT: global_load_ubyte v4, v0, s[2:3] offset:21282; GFX9-GISEL-NEXT: s_waitcnt vmcnt(2)1283; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, v2, 8, v11284; GFX9-GISEL-NEXT: s_waitcnt vmcnt(1)1285; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v31286; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)1287; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v41288; GFX9-GISEL-NEXT: v_or3_b32 v1, v2, v3, v11289; GFX9-GISEL-NEXT: v_ffbl_b32_e32 v2, v11290; GFX9-GISEL-NEXT: v_min_u32_e32 v2, 32, v21291; GFX9-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11292; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc1293; GFX9-GISEL-NEXT: global_store_dword v0, v1, s[0:1]1294; GFX9-GISEL-NEXT: s_endpgm1295 %val = load i32, ptr addrspace(1) %arrayidx, align 11296 %ctlz = call i32 @llvm.cttz.i32(i32 %val, i1 false) nounwind readnone1297 %cmp = icmp ne i32 %val, 01298 %sel = select i1 %cmp, i32 %ctlz, i32 -11299 store i32 %sel, ptr addrspace(1) %out1300 ret void1301}1302 1303define amdgpu_kernel void @v_cttz_i32_sel_ne_bitwidth(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {1304; SI-LABEL: v_cttz_i32_sel_ne_bitwidth:1305; SI: ; %bb.0:1306; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91307; SI-NEXT: s_mov_b32 s7, 0xf0001308; SI-NEXT: s_mov_b32 s6, -11309; SI-NEXT: s_mov_b32 s10, s61310; SI-NEXT: s_mov_b32 s11, s71311; SI-NEXT: s_waitcnt lgkmcnt(0)1312; SI-NEXT: s_mov_b32 s8, s21313; SI-NEXT: s_mov_b32 s9, s31314; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:11315; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:31316; SI-NEXT: buffer_load_ubyte v2, off, s[8:11], 01317; SI-NEXT: buffer_load_ubyte v3, off, s[8:11], 0 offset:21318; SI-NEXT: s_mov_b32 s4, s01319; SI-NEXT: s_mov_b32 s5, s11320; SI-NEXT: s_waitcnt vmcnt(3)1321; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v01322; SI-NEXT: s_waitcnt vmcnt(2)1323; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v11324; SI-NEXT: s_waitcnt vmcnt(1)1325; SI-NEXT: v_or_b32_e32 v0, v0, v21326; SI-NEXT: s_waitcnt vmcnt(0)1327; SI-NEXT: v_or_b32_e32 v1, v1, v31328; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v11329; SI-NEXT: v_or_b32_e32 v0, v1, v01330; SI-NEXT: v_ffbl_b32_e32 v0, v01331; SI-NEXT: v_min_u32_e32 v0, 32, v01332; SI-NEXT: v_cmp_ne_u32_e32 vcc, 32, v01333; SI-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc1334; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01335; SI-NEXT: s_endpgm1336;1337; VI-LABEL: v_cttz_i32_sel_ne_bitwidth:1338; VI: ; %bb.0:1339; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241340; VI-NEXT: s_waitcnt lgkmcnt(0)1341; VI-NEXT: s_add_u32 s4, s2, 31342; VI-NEXT: s_addc_u32 s5, s3, 01343; VI-NEXT: v_mov_b32_e32 v2, s41344; VI-NEXT: v_mov_b32_e32 v3, s51345; VI-NEXT: s_add_u32 s4, s2, 21346; VI-NEXT: v_mov_b32_e32 v0, s21347; VI-NEXT: s_addc_u32 s5, s3, 01348; VI-NEXT: v_mov_b32_e32 v1, s31349; VI-NEXT: s_add_u32 s2, s2, 11350; VI-NEXT: s_addc_u32 s3, s3, 01351; VI-NEXT: v_mov_b32_e32 v4, s41352; VI-NEXT: v_mov_b32_e32 v7, s31353; VI-NEXT: v_mov_b32_e32 v5, s51354; VI-NEXT: v_mov_b32_e32 v6, s21355; VI-NEXT: flat_load_ubyte v2, v[2:3]1356; VI-NEXT: flat_load_ubyte v3, v[4:5]1357; VI-NEXT: flat_load_ubyte v4, v[6:7]1358; VI-NEXT: flat_load_ubyte v0, v[0:1]1359; VI-NEXT: s_waitcnt vmcnt(3)1360; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v21361; VI-NEXT: s_waitcnt vmcnt(2)1362; VI-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1363; VI-NEXT: s_waitcnt vmcnt(1)1364; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v41365; VI-NEXT: s_waitcnt vmcnt(0)1366; VI-NEXT: v_or_b32_e32 v0, v2, v01367; VI-NEXT: v_or_b32_e32 v0, v1, v01368; VI-NEXT: v_ffbl_b32_e32 v0, v01369; VI-NEXT: v_min_u32_e32 v0, 32, v01370; VI-NEXT: v_cmp_ne_u32_e32 vcc, 32, v01371; VI-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc1372; VI-NEXT: v_mov_b32_e32 v0, s01373; VI-NEXT: v_mov_b32_e32 v1, s11374; VI-NEXT: flat_store_dword v[0:1], v21375; VI-NEXT: s_endpgm1376;1377; EG-LABEL: v_cttz_i32_sel_ne_bitwidth:1378; EG: ; %bb.0:1379; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]1380; EG-NEXT: TEX 1 @61381; EG-NEXT: ALU 10, @11, KC0[CB0:0-32], KC1[]1382; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11383; EG-NEXT: CF_END1384; EG-NEXT: PAD1385; EG-NEXT: Fetch clause starting at 6:1386; EG-NEXT: VTX_READ_16 T1.X, T0.X, 2, #11387; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #11388; EG-NEXT: ALU clause starting at 10:1389; EG-NEXT: MOV * T0.X, KC0[2].Z,1390; EG-NEXT: ALU clause starting at 11:1391; EG-NEXT: LSHL * T0.W, T1.X, literal.x,1392; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)1393; EG-NEXT: OR_INT * T0.W, PV.W, T0.X,1394; EG-NEXT: FFBL_INT * T1.W, PV.W,1395; EG-NEXT: CNDE_INT * T0.W, T0.W, literal.x, PV.W,1396; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1397; EG-NEXT: SETNE_INT * T1.W, PV.W, literal.x,1398; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1399; EG-NEXT: CNDE_INT T0.X, PV.W, literal.x, T0.W,1400; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,1401; EG-NEXT: -1(nan), 2(2.802597e-45)1402;1403; GFX9-GISEL-LABEL: v_cttz_i32_sel_ne_bitwidth:1404; GFX9-GISEL: ; %bb.0:1405; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241406; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 01407; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)1408; GFX9-GISEL-NEXT: global_load_ubyte v1, v0, s[2:3]1409; GFX9-GISEL-NEXT: global_load_ubyte v2, v0, s[2:3] offset:11410; GFX9-GISEL-NEXT: global_load_ubyte v3, v0, s[2:3] offset:31411; GFX9-GISEL-NEXT: global_load_ubyte v4, v0, s[2:3] offset:21412; GFX9-GISEL-NEXT: s_waitcnt vmcnt(2)1413; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, v2, 8, v11414; GFX9-GISEL-NEXT: s_waitcnt vmcnt(1)1415; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v31416; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)1417; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v41418; GFX9-GISEL-NEXT: v_or3_b32 v1, v2, v3, v11419; GFX9-GISEL-NEXT: v_ffbl_b32_e32 v1, v11420; GFX9-GISEL-NEXT: v_min_u32_e32 v1, 32, v11421; GFX9-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 32, v11422; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, -1, v1, vcc1423; GFX9-GISEL-NEXT: global_store_dword v0, v1, s[0:1]1424; GFX9-GISEL-NEXT: s_endpgm1425 %val = load i32, ptr addrspace(1) %arrayidx, align 11426 %ctlz = call i32 @llvm.cttz.i32(i32 %val, i1 false) nounwind readnone1427 %cmp = icmp ne i32 %ctlz, 321428 %sel = select i1 %cmp, i32 %ctlz, i32 -11429 store i32 %sel, ptr addrspace(1) %out1430 ret void1431}1432 1433 define amdgpu_kernel void @v_cttz_i8_sel_eq_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {1434; SI-LABEL: v_cttz_i8_sel_eq_neg1:1435; SI: ; %bb.0:1436; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91437; SI-NEXT: s_mov_b32 s7, 0xf0001438; SI-NEXT: s_mov_b32 s6, -11439; SI-NEXT: s_mov_b32 s10, s61440; SI-NEXT: s_mov_b32 s11, s71441; SI-NEXT: s_waitcnt lgkmcnt(0)1442; SI-NEXT: s_mov_b32 s8, s21443; SI-NEXT: s_mov_b32 s9, s31444; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 01445; SI-NEXT: s_mov_b32 s4, s01446; SI-NEXT: s_mov_b32 s5, s11447; SI-NEXT: s_waitcnt vmcnt(0)1448; SI-NEXT: v_ffbl_b32_e32 v0, v01449; SI-NEXT: buffer_store_byte v0, off, s[4:7], 01450; SI-NEXT: s_endpgm1451;1452; VI-LABEL: v_cttz_i8_sel_eq_neg1:1453; VI: ; %bb.0:1454; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241455; VI-NEXT: s_waitcnt lgkmcnt(0)1456; VI-NEXT: v_mov_b32_e32 v0, s21457; VI-NEXT: v_mov_b32_e32 v1, s31458; VI-NEXT: flat_load_ubyte v0, v[0:1]1459; VI-NEXT: s_waitcnt vmcnt(0)1460; VI-NEXT: v_ffbl_b32_e32 v2, v01461; VI-NEXT: v_mov_b32_e32 v0, s01462; VI-NEXT: v_mov_b32_e32 v1, s11463; VI-NEXT: flat_store_byte v[0:1], v21464; VI-NEXT: s_endpgm1465;1466; EG-LABEL: v_cttz_i8_sel_eq_neg1:1467; EG: ; %bb.0:1468; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]1469; EG-NEXT: TEX 0 @61470; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[]1471; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1472; EG-NEXT: CF_END1473; EG-NEXT: PAD1474; EG-NEXT: Fetch clause starting at 6:1475; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #11476; EG-NEXT: ALU clause starting at 8:1477; EG-NEXT: MOV * T0.X, KC0[2].Z,1478; EG-NEXT: ALU clause starting at 9:1479; EG-NEXT: FFBL_INT T0.W, T0.X,1480; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,1481; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1482; EG-NEXT: AND_INT T0.W, PV.W, literal.x,1483; EG-NEXT: LSHL * T1.W, PS, literal.y,1484; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)1485; EG-NEXT: LSHL T0.X, PV.W, PS,1486; EG-NEXT: LSHL * T0.W, literal.x, PS,1487; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)1488; EG-NEXT: MOV T0.Y, 0.0,1489; EG-NEXT: MOV * T0.Z, 0.0,1490; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1491; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1492;1493; GFX9-GISEL-LABEL: v_cttz_i8_sel_eq_neg1:1494; GFX9-GISEL: ; %bb.0:1495; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241496; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 01497; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff1498; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)1499; GFX9-GISEL-NEXT: global_load_ubyte v1, v0, s[2:3]1500; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)1501; GFX9-GISEL-NEXT: v_or_b32_e32 v3, 0x100, v11502; GFX9-GISEL-NEXT: v_ffbl_b32_e32 v3, v31503; GFX9-GISEL-NEXT: v_cmp_eq_u32_sdwa vcc, v1, v0 src0_sel:BYTE_0 src1_sel:DWORD1504; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc1505; GFX9-GISEL-NEXT: global_store_byte v0, v1, s[0:1]1506; GFX9-GISEL-NEXT: s_endpgm1507 %val = load i8, ptr addrspace(1) %arrayidx, align 11508 %ctlz = call i8 @llvm.cttz.i8(i8 %val, i1 false) nounwind readnone1509 %cmp = icmp eq i8 %val, 01510 %sel = select i1 %cmp, i8 -1, i8 %ctlz1511 store i8 %sel, ptr addrspace(1) %out1512 ret void1513}1514 1515 define amdgpu_kernel void @v_cttz_i16_sel_eq_neg1(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind {1516; SI-LABEL: v_cttz_i16_sel_eq_neg1:1517; SI: ; %bb.0:1518; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91519; SI-NEXT: s_mov_b32 s7, 0xf0001520; SI-NEXT: s_mov_b32 s6, -11521; SI-NEXT: s_mov_b32 s10, s61522; SI-NEXT: s_mov_b32 s11, s71523; SI-NEXT: s_waitcnt lgkmcnt(0)1524; SI-NEXT: s_mov_b32 s8, s21525; SI-NEXT: s_mov_b32 s9, s31526; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:11527; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 01528; SI-NEXT: s_mov_b32 s4, s01529; SI-NEXT: s_mov_b32 s5, s11530; SI-NEXT: s_waitcnt vmcnt(1)1531; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v01532; SI-NEXT: s_waitcnt vmcnt(0)1533; SI-NEXT: v_or_b32_e32 v0, v0, v11534; SI-NEXT: v_ffbl_b32_e32 v0, v01535; SI-NEXT: buffer_store_short v0, off, s[4:7], 01536; SI-NEXT: s_endpgm1537;1538; VI-LABEL: v_cttz_i16_sel_eq_neg1:1539; VI: ; %bb.0:1540; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241541; VI-NEXT: s_waitcnt lgkmcnt(0)1542; VI-NEXT: s_add_u32 s4, s2, 11543; VI-NEXT: s_addc_u32 s5, s3, 01544; VI-NEXT: v_mov_b32_e32 v2, s41545; VI-NEXT: v_mov_b32_e32 v0, s21546; VI-NEXT: v_mov_b32_e32 v3, s51547; VI-NEXT: v_mov_b32_e32 v1, s31548; VI-NEXT: flat_load_ubyte v2, v[2:3]1549; VI-NEXT: flat_load_ubyte v0, v[0:1]1550; VI-NEXT: s_waitcnt vmcnt(1)1551; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v21552; VI-NEXT: s_waitcnt vmcnt(0)1553; VI-NEXT: v_or_b32_e32 v0, v1, v01554; VI-NEXT: v_ffbl_b32_e32 v2, v01555; VI-NEXT: v_mov_b32_e32 v0, s01556; VI-NEXT: v_mov_b32_e32 v1, s11557; VI-NEXT: flat_store_short v[0:1], v21558; VI-NEXT: s_endpgm1559;1560; EG-LABEL: v_cttz_i16_sel_eq_neg1:1561; EG: ; %bb.0:1562; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]1563; EG-NEXT: TEX 0 @61564; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[]1565; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1566; EG-NEXT: CF_END1567; EG-NEXT: PAD1568; EG-NEXT: Fetch clause starting at 6:1569; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #11570; EG-NEXT: ALU clause starting at 8:1571; EG-NEXT: MOV * T0.X, KC0[2].Z,1572; EG-NEXT: ALU clause starting at 9:1573; EG-NEXT: FFBL_INT T0.W, T0.X,1574; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,1575; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1576; EG-NEXT: AND_INT T0.W, PV.W, literal.x,1577; EG-NEXT: LSHL * T1.W, PS, literal.y,1578; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)1579; EG-NEXT: LSHL T0.X, PV.W, PS,1580; EG-NEXT: LSHL * T0.W, literal.x, PS,1581; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1582; EG-NEXT: MOV T0.Y, 0.0,1583; EG-NEXT: MOV * T0.Z, 0.0,1584; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1585; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1586;1587; GFX9-GISEL-LABEL: v_cttz_i16_sel_eq_neg1:1588; GFX9-GISEL: ; %bb.0:1589; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241590; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 01591; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xffff1592; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)1593; GFX9-GISEL-NEXT: global_load_ubyte v1, v0, s[2:3]1594; GFX9-GISEL-NEXT: global_load_ubyte v2, v0, s[2:3] offset:11595; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)1596; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, v2, 8, v11597; GFX9-GISEL-NEXT: v_or_b32_e32 v2, 0x10000, v11598; GFX9-GISEL-NEXT: v_ffbl_b32_e32 v2, v21599; GFX9-GISEL-NEXT: v_cmp_eq_u16_e32 vcc, 0, v11600; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc1601; GFX9-GISEL-NEXT: global_store_short v0, v1, s[0:1]1602; GFX9-GISEL-NEXT: s_endpgm1603 %val = load i16, ptr addrspace(1) %arrayidx, align 11604 %ctlz = call i16 @llvm.cttz.i16(i16 %val, i1 false) nounwind readnone1605 %cmp = icmp eq i16 %val, 01606 %sel = select i1 %cmp, i16 -1, i16 %ctlz1607 store i16 %sel, ptr addrspace(1) %out1608 ret void1609}1610 1611 1612