87 lines · plain
1; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s2; RUN: llc -mtriple=amdgcn -enable-no-nans-fp-math < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s4 5declare float @llvm.fabs.f32(float) #16declare float @llvm.floor.f32(float) #17 8; FUNC-LABEL: {{^}}cvt_flr_i32_f32_0:9; SI-SAFE-NOT: v_cvt_flr_i32_f3210; SI-NOT: add11; SI-NONAN: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}12; SI: s_endpgm13define amdgpu_kernel void @cvt_flr_i32_f32_0(ptr addrspace(1) %out, float %x) #0 {14 %floor = call float @llvm.floor.f32(float %x) #115 %cvt = fptosi float %floor to i3216 store i32 %cvt, ptr addrspace(1) %out17 ret void18}19 20; FUNC-LABEL: {{^}}cvt_flr_i32_f32_1:21; SI: v_add_f32_e64 [[TMP:v[0-9]+]], s{{[0-9]+}}, 1.022; SI-SAFE-NOT: v_cvt_flr_i32_f3223; SI-NONAN: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, [[TMP]]24; SI: s_endpgm25define amdgpu_kernel void @cvt_flr_i32_f32_1(ptr addrspace(1) %out, float %x) #0 {26 %fadd = fadd float %x, 1.027 %floor = call float @llvm.floor.f32(float %fadd) #128 %cvt = fptosi float %floor to i3229 store i32 %cvt, ptr addrspace(1) %out30 ret void31}32 33; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fabs:34; SI-NOT: add35; SI-SAFE-NOT: v_cvt_flr_i32_f3236; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|37; SI: s_endpgm38define amdgpu_kernel void @cvt_flr_i32_f32_fabs(ptr addrspace(1) %out, float %x) #0 {39 %x.fabs = call float @llvm.fabs.f32(float %x) #140 %floor = call float @llvm.floor.f32(float %x.fabs) #141 %cvt = fptosi float %floor to i3242 store i32 %cvt, ptr addrspace(1) %out43 ret void44}45 46; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fneg:47; SI-NOT: add48; SI-SAFE-NOT: v_cvt_flr_i32_f3249; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}50; SI: s_endpgm51define amdgpu_kernel void @cvt_flr_i32_f32_fneg(ptr addrspace(1) %out, float %x) #0 {52 %x.fneg = fsub float -0.000000e+00, %x53 %floor = call float @llvm.floor.f32(float %x.fneg) #154 %cvt = fptosi float %floor to i3255 store i32 %cvt, ptr addrspace(1) %out56 ret void57}58 59; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fabs_fneg:60; SI-NOT: add61; SI-SAFE-NOT: v_cvt_flr_i32_f3262; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|63; SI: s_endpgm64define amdgpu_kernel void @cvt_flr_i32_f32_fabs_fneg(ptr addrspace(1) %out, float %x) #0 {65 %x.fabs = call float @llvm.fabs.f32(float %x) #166 %x.fabs.fneg = fsub float -0.000000e+00, %x.fabs67 %floor = call float @llvm.floor.f32(float %x.fabs.fneg) #168 %cvt = fptosi float %floor to i3269 store i32 %cvt, ptr addrspace(1) %out70 ret void71}72 73; FUNC-LABEL: {{^}}no_cvt_flr_i32_f32_0:74; SI-NOT: v_cvt_flr_i32_f3275; SI: v_floor_f3276; SI: v_cvt_u32_f32_e3277; SI: s_endpgm78define amdgpu_kernel void @no_cvt_flr_i32_f32_0(ptr addrspace(1) %out, float %x) #0 {79 %floor = call float @llvm.floor.f32(float %x) #180 %cvt = fptoui float %floor to i3281 store i32 %cvt, ptr addrspace(1) %out82 ret void83}84 85attributes #0 = { nounwind }86attributes #1 = { nounwind readnone }87