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1; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s2; RUN: llc -mtriple=amdgcn -enable-no-nans-fp-math < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s4 5declare float @llvm.fabs.f32(float) #16declare float @llvm.floor.f32(float) #17 8; FUNC-LABEL: {{^}}cvt_rpi_i32_f32:9; SI-SAFE-NOT: v_cvt_rpi_i32_f3210; SI-NONAN: v_cvt_rpi_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}11; SI: s_endpgm12define amdgpu_kernel void @cvt_rpi_i32_f32(ptr addrspace(1) %out, float %x) #0 {13 %fadd = fadd float %x, 0.514 %floor = call float @llvm.floor.f32(float %fadd) #115 %cvt = fptosi float %floor to i3216 store i32 %cvt, ptr addrspace(1) %out17 ret void18}19 20; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fabs:21; SI-SAFE-NOT: v_cvt_rpi_i32_f3222; SI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|{{$}}23; SI: s_endpgm24define amdgpu_kernel void @cvt_rpi_i32_f32_fabs(ptr addrspace(1) %out, float %x) #0 {25 %x.fabs = call float @llvm.fabs.f32(float %x) #126 %fadd = fadd float %x.fabs, 0.527 %floor = call float @llvm.floor.f32(float %fadd) #128 %cvt = fptosi float %floor to i3229 store i32 %cvt, ptr addrspace(1) %out30 ret void31}32 33; FIXME: This doesn't work because it forms fsub 0.5, x34; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fneg:35; XSI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}36; SI: v_sub_f32_e64 [[TMP:v[0-9]+]], 0.5, s{{[0-9]+}}37; SI-SAFE-NOT: v_cvt_flr_i32_f3238; SI-NONAN: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]39; SI: s_endpgm40define amdgpu_kernel void @cvt_rpi_i32_f32_fneg(ptr addrspace(1) %out, float %x) #0 {41 %x.fneg = fsub float -0.000000e+00, %x42 %fadd = fadd float %x.fneg, 0.543 %floor = call float @llvm.floor.f32(float %fadd) #144 %cvt = fptosi float %floor to i3245 store i32 %cvt, ptr addrspace(1) %out46 ret void47}48 49; FIXME: This doesn't work for same reason as above50; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fabs_fneg:51; SI-SAFE-NOT: v_cvt_rpi_i32_f3252; XSI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|53 54; SI: v_sub_f32_e64 [[TMP:v[0-9]+]], 0.5, |s{{[0-9]+}}|55; SI-SAFE-NOT: v_cvt_flr_i32_f3256; SI-NONAN: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]57; SI: s_endpgm58define amdgpu_kernel void @cvt_rpi_i32_f32_fabs_fneg(ptr addrspace(1) %out, float %x) #0 {59 %x.fabs = call float @llvm.fabs.f32(float %x) #160 %x.fabs.fneg = fsub float -0.000000e+00, %x.fabs61 %fadd = fadd float %x.fabs.fneg, 0.562 %floor = call float @llvm.floor.f32(float %fadd) #163 %cvt = fptosi float %floor to i3264 store i32 %cvt, ptr addrspace(1) %out65 ret void66}67 68; FUNC-LABEL: {{^}}no_cvt_rpi_i32_f32_0:69; SI-NOT: v_cvt_rpi_i32_f3270; SI: v_add_f3271; SI: v_floor_f3272; SI: v_cvt_u32_f3273; SI: s_endpgm74define amdgpu_kernel void @no_cvt_rpi_i32_f32_0(ptr addrspace(1) %out, float %x) #0 {75 %fadd = fadd float %x, 0.576 %floor = call float @llvm.floor.f32(float %fadd) #177 %cvt = fptoui float %floor to i3278 store i32 %cvt, ptr addrspace(1) %out79 ret void80}81 82attributes #0 = { nounwind }83attributes #1 = { nounwind readnone }84