167 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s3 4define i32 @mullohi_u32(i32 %arg, i32 %arg1, ptr %arg2) {5; CHECK-LABEL: mullohi_u32:6; CHECK: ; %bb.0: ; %bb7; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v1, v0, 09; CHECK-NEXT: flat_store_dword v[2:3], v110; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)11; CHECK-NEXT: s_setpc_b64 s[30:31]12bb:13 %i = zext i32 %arg to i6414 %i3 = zext i32 %arg1 to i6415 %i4 = mul nuw i64 %i3, %i16 %i5 = lshr i64 %i4, 3217 %i6 = trunc i64 %i5 to i3218 store i32 %i6, ptr %arg2, align 419 %i7 = trunc i64 %i4 to i3220 ret i32 %i721}22 23define i32 @mullohi_s32(i32 %arg, i32 %arg1, ptr %arg2) {24; CHECK-LABEL: mullohi_s32:25; CHECK: ; %bb.0: ; %bb26; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)27; CHECK-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v1, v0, 028; CHECK-NEXT: flat_store_dword v[2:3], v129; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)30; CHECK-NEXT: s_setpc_b64 s[30:31]31bb:32 %i = sext i32 %arg to i6433 %i3 = sext i32 %arg1 to i6434 %i4 = mul nsw i64 %i3, %i35 %i5 = ashr i64 %i4, 3236 %i6 = trunc i64 %i5 to i3237 store i32 %i6, ptr %arg2, align 438 %i7 = trunc i64 %i4 to i3239 ret i32 %i740}41 42define i32 @mullohi_u32_non_const_shift(i32 %arg, i32 %arg1, ptr %arg2, i64 %shift) {43; CHECK-LABEL: mullohi_u32_non_const_shift:44; CHECK: ; %bb.0: ; %bb45; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)46; CHECK-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v1, v0, 047; CHECK-NEXT: v_lshrrev_b64 v[0:1], v4, v[5:6]48; CHECK-NEXT: flat_store_dword v[2:3], v649; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)50; CHECK-NEXT: s_setpc_b64 s[30:31]51bb:52 %i = zext i32 %arg to i6453 %i3 = zext i32 %arg1 to i6454 %i4 = mul nuw i64 %i3, %i55 %i5 = lshr i64 %i4, 3256 %i6 = trunc i64 %i5 to i3257 store i32 %i6, ptr %arg2, align 458 %i7 = lshr i64 %i4, %shift59 %i8 = trunc i64 %i7 to i3260 ret i32 %i861}62 63define <2 x i32> @mullohi_2xu32(<2 x i32> %arg, <2 x i32> %arg1, ptr %arg2) {64; CHECK-LABEL: mullohi_2xu32:65; CHECK: ; %bb.0: ; %bb66; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)67; CHECK-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v3, v1, 068; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v0, 069; CHECK-NEXT: v_mov_b32_e32 v2, v770; CHECK-NEXT: flat_store_dwordx2 v[4:5], v[1:2]71; CHECK-NEXT: v_mov_b32_e32 v1, v672; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)73; CHECK-NEXT: s_setpc_b64 s[30:31]74bb:75 %i = zext <2 x i32> %arg to <2 x i64>76 %i3 = zext <2 x i32> %arg1 to <2 x i64>77 %i4 = mul nuw <2 x i64> %i3, %i78 %i5 = lshr <2 x i64> %i4, <i64 32, i64 32>79 %i6 = trunc <2 x i64> %i5 to <2 x i32>80 store <2 x i32> %i6, ptr %arg2, align 881 %i7 = trunc <2 x i64> %i4 to <2 x i32>82 ret <2 x i32> %i783}84 85define i8 @mullohi_illegal_ty(i8 %arg, i8 %arg1, ptr %arg2) {86; CHECK-LABEL: mullohi_illegal_ty:87; CHECK: ; %bb.0: ; %bb88; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)89; CHECK-NEXT: v_mul_lo_u16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_090; CHECK-NEXT: v_lshrrev_b16_e32 v1, 8, v091; CHECK-NEXT: flat_store_byte v[2:3], v192; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)93; CHECK-NEXT: s_setpc_b64 s[30:31]94bb:95 %i = zext i8 %arg to i1696 %i3 = zext i8 %arg1 to i1697 %i4 = mul nuw i16 %i3, %i98 %i5 = lshr i16 %i4, 899 %i6 = trunc i16 %i5 to i8100 store i8 %i6, ptr %arg2, align 1101 %i7 = trunc i16 %i4 to i8102 ret i8 %i7103}104 105define i32 @mul_one_bit_low_hi_u32(i32 %arg, i32 %arg1, ptr %arg2) {106; CHECK-LABEL: mul_one_bit_low_hi_u32:107; CHECK: ; %bb.0: ; %bb108; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)109; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v1, v0, 0110; CHECK-NEXT: v_alignbit_b32 v0, v1, v0, 31111; CHECK-NEXT: flat_store_dword v[2:3], v1112; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)113; CHECK-NEXT: s_setpc_b64 s[30:31]114bb:115 %i = zext i32 %arg to i64116 %i3 = zext i32 %arg1 to i64117 %i4 = mul nsw i64 %i3, %i118 %i5 = lshr i64 %i4, 32119 %i6 = trunc i64 %i5 to i32120 store i32 %i6, ptr %arg2, align 4121 %i7 = lshr i64 %i4, 31122 %i8 = trunc i64 %i7 to i32123 ret i32 %i8124}125 126define i32 @mul_one_bit_hi_hi_u32_lshr_lshr(i32 %arg, i32 %arg1, ptr %arg2) {127; CHECK-LABEL: mul_one_bit_hi_hi_u32_lshr_lshr:128; CHECK: ; %bb.0: ; %bb129; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)130; CHECK-NEXT: v_mul_hi_u32 v0, v1, v0131; CHECK-NEXT: flat_store_dword v[2:3], v0132; CHECK-NEXT: v_lshrrev_b32_e32 v0, 1, v0133; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)134; CHECK-NEXT: s_setpc_b64 s[30:31]135bb:136 %i = zext i32 %arg to i64137 %i3 = zext i32 %arg1 to i64138 %i4 = mul nsw i64 %i3, %i139 %i5 = lshr i64 %i4, 32140 %i6 = trunc i64 %i5 to i32141 store i32 %i6, ptr %arg2, align 4142 %i7 = lshr i64 %i4, 33143 %i8 = trunc i64 %i7 to i32144 ret i32 %i8145}146 147define i32 @mul_one_bit_hi_hi_u32_lshr_ashr(i32 %arg, i32 %arg1, ptr %arg2) {148; CHECK-LABEL: mul_one_bit_hi_hi_u32_lshr_ashr:149; CHECK: ; %bb.0: ; %bb150; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)151; CHECK-NEXT: v_mul_hi_u32 v0, v1, v0152; CHECK-NEXT: flat_store_dword v[2:3], v0153; CHECK-NEXT: v_ashrrev_i32_e32 v0, 1, v0154; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)155; CHECK-NEXT: s_setpc_b64 s[30:31]156bb:157 %i = zext i32 %arg to i64158 %i3 = zext i32 %arg1 to i64159 %i4 = mul nsw i64 %i3, %i160 %i5 = lshr i64 %i4, 32161 %i6 = trunc i64 %i5 to i32162 store i32 %i6, ptr %arg2, align 4163 %i7 = ashr i64 %i4, 33164 %i8 = trunc i64 %i7 to i32165 ret i32 %i8166}167