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1; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s2 3; We are only checking that instruction selection can succeed in this case. This4; cut down test results in no instructions, but that's fine.5;6; See https://llvm.org/PR33743 for details of the bug being addressed7;8; Checking that shufflevector with 3-vec mask is handled in9; combineShuffleToVectorExtend10;11; GCN: s_endpgm12 13define amdgpu_ps void @main(i32 %in1, i32 inreg %arg) local_unnamed_addr {14.entry:15 %cond = icmp eq i32 %arg, 016 br i1 %cond, label %bb12, label %bb17 18bb:19 %__llpc_global_proxy_r5.12.vec.insert = insertelement <4 x i32> poison, i32 %in1, i32 320 %tmp3 = shufflevector <4 x i32> %__llpc_global_proxy_r5.12.vec.insert, <4 x i32> poison, <3 x i32> <i32 poison, i32 poison, i32 1>21 %tmp4 = bitcast <3 x i32> %tmp3 to <3 x float>22 %a2.i123 = extractelement <3 x float> %tmp4, i32 223 %tmp5 = bitcast float %a2.i123 to i3224 %__llpc_global_proxy_r2.0.vec.insert196 = insertelement <4 x i32> poison, i32 %tmp5, i32 025 br label %bb1226 27bb12:28 %__llpc_global_proxy_r2.0 = phi <4 x i32> [ %__llpc_global_proxy_r2.0.vec.insert196, %bb ], [ poison, %.entry ]29 %tmp6 = shufflevector <4 x i32> %__llpc_global_proxy_r2.0, <4 x i32> poison, <3 x i32> <i32 1, i32 2, i32 3>30 %tmp7 = bitcast <3 x i32> %tmp6 to <3 x float>31 %a0.i = extractelement <3 x float> %tmp7, i32 032 ret void33}34