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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -start-before=amdgpu-isel -stop-after=amdgpu-isel < %s | FileCheck %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -enable-new-pm -start-before=amdgpu-isel -stop-after=amdgpu-isel < %s | FileCheck %s4 5define void @main(float %arg) {6 ; CHECK-LABEL: name: main7 ; CHECK: bb.0.bb:8 ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)9 ; CHECK-NEXT: liveins: $vgpr010 ; CHECK-NEXT: {{ $}}11 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr012 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 013 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -114 ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF15 ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 $exec_lo, [[S_MOV_B32_1]], implicit-def dead $scc16 ; CHECK-NEXT: $vcc_lo = COPY [[S_AND_B32_]]17 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc18 ; CHECK-NEXT: S_BRANCH %bb.119 ; CHECK-NEXT: {{ $}}20 ; CHECK-NEXT: bb.1.bb2:21 ; CHECK-NEXT: successors: %bb.2(0x80000000)22 ; CHECK-NEXT: {{ $}}23 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec24 ; CHECK-NEXT: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = contract reassoc nofpexcept V_FMAC_F32_e64 0, [[S_MOV_B32_]], 0, [[S_MOV_B32_]], 0, [[V_MOV_B32_e32_]], 0, 0, implicit $mode, implicit $exec25 ; CHECK-NEXT: [[V_FMAC_F32_e64_1:%[0-9]+]]:vgpr_32 = contract reassoc nofpexcept V_FMAC_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[V_FMAC_F32_e64_]], 0, 0, implicit $mode, implicit $exec26 ; CHECK-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = contract reassoc nofpexcept V_ADD_F32_e64 0, [[V_FMAC_F32_e64_1]], 0, [[V_MOV_B32_e32_]], 0, 0, implicit $mode, implicit $exec27 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 028 ; CHECK-NEXT: {{ $}}29 ; CHECK-NEXT: bb.2.bb11:30 ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)31 ; CHECK-NEXT: {{ $}}32 ; CHECK-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[DEF]], %bb.0, [[V_FMAC_F32_e64_1]], %bb.133 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[DEF]], %bb.0, [[V_ADD_F32_e64_]], %bb.134 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:sreg_32_xm0_xexec = PHI [[S_MOV_B32_1]], %bb.0, [[S_MOV_B32_2]], %bb.135 ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[PHI2]], implicit $exec36 ; CHECK-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 137 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_CNDMASK_B32_e64_]]38 ; CHECK-NEXT: S_CMP_LG_U32 killed [[COPY1]], killed [[S_MOV_B32_3]], implicit-def $scc39 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc40 ; CHECK-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 $exec_lo, killed [[COPY2]], implicit-def dead $scc41 ; CHECK-NEXT: $vcc_lo = COPY [[S_AND_B32_1]]42 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit $vcc43 ; CHECK-NEXT: S_BRANCH %bb.344 ; CHECK-NEXT: {{ $}}45 ; CHECK-NEXT: bb.3.bb15:46 ; CHECK-NEXT: successors: %bb.4(0x80000000)47 ; CHECK-NEXT: {{ $}}48 ; CHECK-NEXT: bb.4.bb17:49 ; CHECK-NEXT: SI_RETURN50bb:51 %i = fadd reassoc contract float 0.000000e+00, 0.000000e+0052 %i1 = icmp ne i32 0, 053 br i1 %i1, label %bb2, label %bb1154 55bb2:56 %i3 = fmul reassoc contract float %i, %i57 %i4 = fmul reassoc contract float %arg, %arg58 %i5 = fadd reassoc contract float %i3, 1.000000e+0059 %i6 = fadd reassoc contract float %i5, %i460 %i7 = fmul reassoc contract float %arg, %arg61 %i8 = fmul reassoc contract float %i, %i62 %i9 = fadd reassoc contract float %i7, %i863 %i10 = fadd reassoc contract float %i9, 1.000000e+0064 br label %bb1165 66bb11:67 %i12 = phi float [ %i6, %bb2 ], [ poison, %bb ]68 %i13 = phi float [ %i10, %bb2 ], [ poison, %bb ]69 %i14 = phi i1 [ false, %bb2 ], [ true, %bb ]70 br i1 %i14, label %bb15, label %bb1771 72bb15:73 %i16 = fmul reassoc contract float %i, 0.000000e+0074 br label %bb1775 76bb17:77 %i18 = phi float [ %i13, %bb11 ], [ 0.000000e+00, %bb15 ]78 %i19 = phi float [ %i12, %bb11 ], [ 0.000000e+00, %bb15 ]79 ret void80}81 82define float @test2(float %arg, float %arg1) {83 ; CHECK-LABEL: name: test284 ; CHECK: bb.0.bb:85 ; CHECK-NEXT: liveins: $vgpr0, $vgpr186 ; CHECK-NEXT: {{ $}}87 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr188 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr089 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1082130432, implicit $exec90 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 112053452891 ; CHECK-NEXT: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = nsz contract reassoc nofpexcept V_FMAC_F32_e64 0, [[COPY]], 0, killed [[S_MOV_B32_]], 0, [[V_MOV_B32_e32_]], 0, 0, implicit $mode, implicit $exec92 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 093 ; CHECK-NEXT: [[V_FMAC_F32_e64_1:%[0-9]+]]:vgpr_32 = nsz contract nofpexcept V_FMAC_F32_e64 0, [[COPY1]], 0, killed [[S_MOV_B32_1]], 0, [[V_FMAC_F32_e64_]], 0, 0, implicit $mode, implicit $exec94 ; CHECK-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nsz contract reassoc nofpexcept V_ADD_F32_e64 0, [[V_FMAC_F32_e64_1]], 0, [[V_MOV_B32_e32_]], 0, 0, implicit $mode, implicit $exec95 ; CHECK-NEXT: [[V_RCP_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_RCP_F32_e64 0, [[V_FMAC_F32_e64_1]], 0, 0, implicit $mode, implicit $exec96 ; CHECK-NEXT: [[V_RCP_F32_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_RCP_F32_e64 0, killed [[V_ADD_F32_e64_]], 0, 0, implicit $mode, implicit $exec97 ; CHECK-NEXT: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_MUL_F32_e64 0, [[V_RCP_F32_e64_1]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec98 ; CHECK-NEXT: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_MAX_F32_e64 0, killed [[V_MUL_F32_e64_]], 0, [[V_RCP_F32_e64_1]], 0, 0, implicit $mode, implicit $exec99 ; CHECK-NEXT: [[V_ADD_F32_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, killed [[V_MAX_F32_e64_]], 0, killed [[V_RCP_F32_e64_]], 0, 0, implicit $mode, implicit $exec100 ; CHECK-NEXT: $vgpr0 = COPY [[V_ADD_F32_e64_1]]101 ; CHECK-NEXT: SI_RETURN implicit $vgpr0102bb:103 %i = fmul contract float %arg1, 1.000000e+02104 %i2 = fmul contract float %arg, 0.000000e+00105 %i3 = fadd reassoc nsz contract float %i, %arg1106 %i4 = fadd nsz contract float %i3, %i2107 %i5 = fsub reassoc nsz contract float 1.000000e+00, %i4108 %i6 = fdiv afn float 1.000000e+00, %i5109 %i7 = fneg float %arg110 %i9 = fmul float %i6, %i7111 %i10 = fmul float %i6, -1.000000e+00112 %i13 = call float @llvm.maxnum.f32(float %i9, float %i10)113 %ret = fadd float %i10, %i13114 ret float %ret115}116 117declare float @llvm.maxnum.f32(float, float)118