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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX942 %s4 5define amdgpu_kernel void @select_and1(ptr addrspace(1) %p, i32 %x, i32 %y) {6; GCN-LABEL: select_and1:7; GCN: ; %bb.0:8; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x249; GCN-NEXT: v_mov_b32_e32 v0, 010; GCN-NEXT: s_waitcnt lgkmcnt(0)11; GCN-NEXT: s_cmp_gt_i32 s2, 1012; GCN-NEXT: s_cselect_b32 s2, s3, 013; GCN-NEXT: v_mov_b32_e32 v1, s214; GCN-NEXT: global_store_dword v0, v1, s[0:1]15; GCN-NEXT: s_endpgm16 %c = icmp slt i32 %x, 1117 %s = select i1 %c, i32 0, i32 -118 %a = and i32 %y, %s19 store i32 %a, ptr addrspace(1) %p, align 420 ret void21}22 23define amdgpu_kernel void @select_and2(ptr addrspace(1) %p, i32 %x, i32 %y) {24; GCN-LABEL: select_and2:25; GCN: ; %bb.0:26; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2427; GCN-NEXT: v_mov_b32_e32 v0, 028; GCN-NEXT: s_waitcnt lgkmcnt(0)29; GCN-NEXT: s_cmp_gt_i32 s2, 1030; GCN-NEXT: s_cselect_b32 s2, s3, 031; GCN-NEXT: v_mov_b32_e32 v1, s232; GCN-NEXT: global_store_dword v0, v1, s[0:1]33; GCN-NEXT: s_endpgm34 %c = icmp slt i32 %x, 1135 %s = select i1 %c, i32 0, i32 -136 %a = and i32 %s, %y37 store i32 %a, ptr addrspace(1) %p, align 438 ret void39}40 41define amdgpu_kernel void @select_and3(ptr addrspace(1) %p, i32 %x, i32 %y) {42; GCN-LABEL: select_and3:43; GCN: ; %bb.0:44; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2445; GCN-NEXT: v_mov_b32_e32 v0, 046; GCN-NEXT: s_waitcnt lgkmcnt(0)47; GCN-NEXT: s_cmp_lt_i32 s2, 1148; GCN-NEXT: s_cselect_b32 s2, s3, 049; GCN-NEXT: v_mov_b32_e32 v1, s250; GCN-NEXT: global_store_dword v0, v1, s[0:1]51; GCN-NEXT: s_endpgm52 %c = icmp slt i32 %x, 1153 %s = select i1 %c, i32 -1, i32 054 %a = and i32 %y, %s55 store i32 %a, ptr addrspace(1) %p, align 456 ret void57}58 59define amdgpu_kernel void @select_and_v4(ptr addrspace(1) %p, i32 %x, <4 x i32> %y) {60; GFX9-LABEL: select_and_v4:61; GFX9: ; %bb.0:62; GFX9-NEXT: s_load_dword s8, s[4:5], 0x2c63; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x3464; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x2465; GFX9-NEXT: v_mov_b32_e32 v4, 066; GFX9-NEXT: s_waitcnt lgkmcnt(0)67; GFX9-NEXT: s_cmp_gt_i32 s8, 1068; GFX9-NEXT: s_cselect_b32 s3, s3, 069; GFX9-NEXT: s_cselect_b32 s2, s2, 070; GFX9-NEXT: s_cselect_b32 s1, s1, 071; GFX9-NEXT: s_cselect_b32 s0, s0, 072; GFX9-NEXT: v_mov_b32_e32 v0, s073; GFX9-NEXT: v_mov_b32_e32 v1, s174; GFX9-NEXT: v_mov_b32_e32 v2, s275; GFX9-NEXT: v_mov_b32_e32 v3, s376; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]77; GFX9-NEXT: s_endpgm78;79; GFX942-LABEL: select_and_v4:80; GFX942: ; %bb.0:81; GFX942-NEXT: s_load_dword s8, s[4:5], 0x2c82; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x3483; GFX942-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x2484; GFX942-NEXT: v_mov_b32_e32 v0, 085; GFX942-NEXT: s_waitcnt lgkmcnt(0)86; GFX942-NEXT: s_cmp_gt_i32 s8, 1087; GFX942-NEXT: s_cselect_b32 s3, s3, 088; GFX942-NEXT: s_cselect_b32 s2, s2, 089; GFX942-NEXT: s_cselect_b32 s1, s1, 090; GFX942-NEXT: s_cselect_b32 s0, s0, 091; GFX942-NEXT: v_mov_b32_e32 v2, s092; GFX942-NEXT: v_mov_b32_e32 v3, s193; GFX942-NEXT: v_mov_b32_e32 v4, s294; GFX942-NEXT: v_mov_b32_e32 v5, s395; GFX942-NEXT: global_store_dwordx4 v0, v[2:5], s[6:7]96; GFX942-NEXT: s_endpgm97 %c = icmp slt i32 %x, 1198 %s = select i1 %c, <4 x i32> zeroinitializer, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>99 %a = and <4 x i32> %s, %y100 store <4 x i32> %a, ptr addrspace(1) %p, align 32101 ret void102}103 104define amdgpu_kernel void @select_or1(ptr addrspace(1) %p, i32 %x, i32 %y) {105; GCN-LABEL: select_or1:106; GCN: ; %bb.0:107; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24108; GCN-NEXT: v_mov_b32_e32 v0, 0109; GCN-NEXT: s_waitcnt lgkmcnt(0)110; GCN-NEXT: s_cmp_lt_i32 s2, 11111; GCN-NEXT: s_cselect_b32 s2, s3, -1112; GCN-NEXT: v_mov_b32_e32 v1, s2113; GCN-NEXT: global_store_dword v0, v1, s[0:1]114; GCN-NEXT: s_endpgm115 %c = icmp slt i32 %x, 11116 %s = select i1 %c, i32 0, i32 -1117 %a = or i32 %y, %s118 store i32 %a, ptr addrspace(1) %p, align 4119 ret void120}121 122define amdgpu_kernel void @select_or2(ptr addrspace(1) %p, i32 %x, i32 %y) {123; GCN-LABEL: select_or2:124; GCN: ; %bb.0:125; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24126; GCN-NEXT: v_mov_b32_e32 v0, 0127; GCN-NEXT: s_waitcnt lgkmcnt(0)128; GCN-NEXT: s_cmp_lt_i32 s2, 11129; GCN-NEXT: s_cselect_b32 s2, s3, -1130; GCN-NEXT: v_mov_b32_e32 v1, s2131; GCN-NEXT: global_store_dword v0, v1, s[0:1]132; GCN-NEXT: s_endpgm133 %c = icmp slt i32 %x, 11134 %s = select i1 %c, i32 0, i32 -1135 %a = or i32 %s, %y136 store i32 %a, ptr addrspace(1) %p, align 4137 ret void138}139 140define amdgpu_kernel void @select_or3(ptr addrspace(1) %p, i32 %x, i32 %y) {141; GCN-LABEL: select_or3:142; GCN: ; %bb.0:143; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24144; GCN-NEXT: v_mov_b32_e32 v0, 0145; GCN-NEXT: s_waitcnt lgkmcnt(0)146; GCN-NEXT: s_cmp_gt_i32 s2, 10147; GCN-NEXT: s_cselect_b32 s2, s3, -1148; GCN-NEXT: v_mov_b32_e32 v1, s2149; GCN-NEXT: global_store_dword v0, v1, s[0:1]150; GCN-NEXT: s_endpgm151 %c = icmp slt i32 %x, 11152 %s = select i1 %c, i32 -1, i32 0153 %a = or i32 %y, %s154 store i32 %a, ptr addrspace(1) %p, align 4155 ret void156}157 158define amdgpu_kernel void @select_or_v4(ptr addrspace(1) %p, i32 %x, <4 x i32> %y) {159; GFX9-LABEL: select_or_v4:160; GFX9: ; %bb.0:161; GFX9-NEXT: s_load_dword s8, s[4:5], 0x2c162; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34163; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24164; GFX9-NEXT: v_mov_b32_e32 v4, 0165; GFX9-NEXT: s_waitcnt lgkmcnt(0)166; GFX9-NEXT: s_cmp_lt_i32 s8, 11167; GFX9-NEXT: s_cselect_b32 s3, s3, -1168; GFX9-NEXT: s_cselect_b32 s2, s2, -1169; GFX9-NEXT: s_cselect_b32 s1, s1, -1170; GFX9-NEXT: s_cselect_b32 s0, s0, -1171; GFX9-NEXT: v_mov_b32_e32 v0, s0172; GFX9-NEXT: v_mov_b32_e32 v1, s1173; GFX9-NEXT: v_mov_b32_e32 v2, s2174; GFX9-NEXT: v_mov_b32_e32 v3, s3175; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]176; GFX9-NEXT: s_endpgm177;178; GFX942-LABEL: select_or_v4:179; GFX942: ; %bb.0:180; GFX942-NEXT: s_load_dword s8, s[4:5], 0x2c181; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34182; GFX942-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24183; GFX942-NEXT: v_mov_b32_e32 v0, 0184; GFX942-NEXT: s_waitcnt lgkmcnt(0)185; GFX942-NEXT: s_cmp_lt_i32 s8, 11186; GFX942-NEXT: s_cselect_b32 s3, s3, -1187; GFX942-NEXT: s_cselect_b32 s2, s2, -1188; GFX942-NEXT: s_cselect_b32 s1, s1, -1189; GFX942-NEXT: s_cselect_b32 s0, s0, -1190; GFX942-NEXT: v_mov_b32_e32 v2, s0191; GFX942-NEXT: v_mov_b32_e32 v3, s1192; GFX942-NEXT: v_mov_b32_e32 v4, s2193; GFX942-NEXT: v_mov_b32_e32 v5, s3194; GFX942-NEXT: global_store_dwordx4 v0, v[2:5], s[6:7]195; GFX942-NEXT: s_endpgm196 %c = icmp slt i32 %x, 11197 %s = select i1 %c, <4 x i32> zeroinitializer, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>198 %a = or <4 x i32> %s, %y199 store <4 x i32> %a, ptr addrspace(1) %p, align 32200 ret void201}202 203define amdgpu_kernel void @sel_constants_sub_constant_sel_constants(ptr addrspace(1) %p, i1 %cond) {204; GCN-LABEL: sel_constants_sub_constant_sel_constants:205; GCN: ; %bb.0:206; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c207; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24208; GCN-NEXT: v_mov_b32_e32 v0, 0209; GCN-NEXT: s_waitcnt lgkmcnt(0)210; GCN-NEXT: s_bitcmp1_b32 s2, 0211; GCN-NEXT: s_cselect_b32 s2, 9, 2212; GCN-NEXT: v_mov_b32_e32 v1, s2213; GCN-NEXT: global_store_dword v0, v1, s[0:1]214; GCN-NEXT: s_endpgm215 %sel = select i1 %cond, i32 -4, i32 3216 %bo = sub i32 5, %sel217 store i32 %bo, ptr addrspace(1) %p, align 4218 ret void219}220 221define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_i16(ptr addrspace(1) %p, i1 %cond) {222; GCN-LABEL: sel_constants_sub_constant_sel_constants_i16:223; GCN: ; %bb.0:224; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c225; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24226; GCN-NEXT: v_mov_b32_e32 v0, 0227; GCN-NEXT: s_waitcnt lgkmcnt(0)228; GCN-NEXT: s_bitcmp1_b32 s2, 0229; GCN-NEXT: s_cselect_b32 s2, 9, 2230; GCN-NEXT: v_mov_b32_e32 v1, s2231; GCN-NEXT: global_store_short v0, v1, s[0:1]232; GCN-NEXT: s_endpgm233 %sel = select i1 %cond, i16 -4, i16 3234 %bo = sub i16 5, %sel235 store i16 %bo, ptr addrspace(1) %p, align 2236 ret void237}238 239define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_i16_neg(ptr addrspace(1) %p, i1 %cond) {240; GCN-LABEL: sel_constants_sub_constant_sel_constants_i16_neg:241; GCN: ; %bb.0:242; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c243; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24244; GCN-NEXT: v_mov_b32_e32 v0, 0245; GCN-NEXT: s_waitcnt lgkmcnt(0)246; GCN-NEXT: s_bitcmp1_b32 s2, 0247; GCN-NEXT: s_mov_b32 s2, 0xfffd248; GCN-NEXT: s_cselect_b32 s2, s2, 0xf449249; GCN-NEXT: v_mov_b32_e32 v1, s2250; GCN-NEXT: global_store_short v0, v1, s[0:1]251; GCN-NEXT: s_endpgm252 %sel = select i1 %cond, i16 4, i16 3000253 %bo = sub i16 1, %sel254 store i16 %bo, ptr addrspace(1) %p, align 2255 ret void256}257 258define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_v2i16(ptr addrspace(1) %p, i1 %cond) {259; GCN-LABEL: sel_constants_sub_constant_sel_constants_v2i16:260; GCN: ; %bb.0:261; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c262; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24263; GCN-NEXT: v_mov_b32_e32 v0, 0264; GCN-NEXT: s_waitcnt lgkmcnt(0)265; GCN-NEXT: s_bitcmp1_b32 s2, 0266; GCN-NEXT: s_mov_b32 s2, 0x50009267; GCN-NEXT: s_cselect_b32 s2, s2, 0x60002268; GCN-NEXT: v_mov_b32_e32 v1, s2269; GCN-NEXT: global_store_dword v0, v1, s[0:1]270; GCN-NEXT: s_endpgm271 %sel = select i1 %cond, <2 x i16> <i16 -4, i16 2>, <2 x i16> <i16 3, i16 1>272 %bo = sub <2 x i16> <i16 5, i16 7>, %sel273 store <2 x i16> %bo, ptr addrspace(1) %p, align 4274 ret void275}276 277define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_v4i32(ptr addrspace(1) %p, i1 %cond) {278; GFX9-LABEL: sel_constants_sub_constant_sel_constants_v4i32:279; GFX9: ; %bb.0:280; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c281; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24282; GFX9-NEXT: v_mov_b32_e32 v4, 0283; GFX9-NEXT: s_waitcnt lgkmcnt(0)284; GFX9-NEXT: s_bitcmp1_b32 s2, 0285; GFX9-NEXT: s_cselect_b32 s2, 7, 14286; GFX9-NEXT: s_cselect_b32 s3, 6, 10287; GFX9-NEXT: s_cselect_b32 s4, 5, 6288; GFX9-NEXT: s_cselect_b32 s5, 9, 2289; GFX9-NEXT: v_mov_b32_e32 v0, s5290; GFX9-NEXT: v_mov_b32_e32 v1, s4291; GFX9-NEXT: v_mov_b32_e32 v2, s3292; GFX9-NEXT: v_mov_b32_e32 v3, s2293; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]294; GFX9-NEXT: s_endpgm295;296; GFX942-LABEL: sel_constants_sub_constant_sel_constants_v4i32:297; GFX942: ; %bb.0:298; GFX942-NEXT: s_load_dword s2, s[4:5], 0x2c299; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24300; GFX942-NEXT: v_mov_b32_e32 v0, 0301; GFX942-NEXT: s_waitcnt lgkmcnt(0)302; GFX942-NEXT: s_bitcmp1_b32 s2, 0303; GFX942-NEXT: s_cselect_b32 s2, 7, 14304; GFX942-NEXT: s_cselect_b32 s3, 6, 10305; GFX942-NEXT: s_cselect_b32 s4, 5, 6306; GFX942-NEXT: s_cselect_b32 s5, 9, 2307; GFX942-NEXT: v_mov_b32_e32 v2, s5308; GFX942-NEXT: v_mov_b32_e32 v3, s4309; GFX942-NEXT: v_mov_b32_e32 v4, s3310; GFX942-NEXT: v_mov_b32_e32 v5, s2311; GFX942-NEXT: global_store_dwordx4 v0, v[2:5], s[0:1]312; GFX942-NEXT: s_endpgm313 %sel = select i1 %cond, <4 x i32> <i32 -4, i32 2, i32 3, i32 4>, <4 x i32> <i32 3, i32 1, i32 -1, i32 -3>314 %bo = sub <4 x i32> <i32 5, i32 7, i32 9, i32 11>, %sel315 store <4 x i32> %bo, ptr addrspace(1) %p, align 32316 ret void317}318 319define amdgpu_kernel void @sdiv_constant_sel_constants_i64(ptr addrspace(1) %p, i1 %cond) {320; GCN-LABEL: sdiv_constant_sel_constants_i64:321; GCN: ; %bb.0:322; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c323; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24324; GCN-NEXT: v_mov_b32_e32 v1, 0325; GCN-NEXT: s_waitcnt lgkmcnt(0)326; GCN-NEXT: s_bitcmp1_b32 s2, 0327; GCN-NEXT: s_cselect_b32 s2, 0, 5328; GCN-NEXT: v_mov_b32_e32 v0, s2329; GCN-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]330; GCN-NEXT: s_endpgm331 %sel = select i1 %cond, i64 121, i64 23332 %bo = sdiv i64 120, %sel333 store i64 %bo, ptr addrspace(1) %p, align 8334 ret void335}336 337define amdgpu_kernel void @sdiv_constant_sel_constants_i32(ptr addrspace(1) %p, i1 %cond) {338; GCN-LABEL: sdiv_constant_sel_constants_i32:339; GCN: ; %bb.0:340; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c341; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24342; GCN-NEXT: v_mov_b32_e32 v0, 0343; GCN-NEXT: s_waitcnt lgkmcnt(0)344; GCN-NEXT: s_bitcmp1_b32 s2, 0345; GCN-NEXT: s_cselect_b32 s2, 26, 8346; GCN-NEXT: v_mov_b32_e32 v1, s2347; GCN-NEXT: global_store_dword v0, v1, s[0:1]348; GCN-NEXT: s_endpgm349 %sel = select i1 %cond, i32 7, i32 23350 %bo = sdiv i32 184, %sel351 store i32 %bo, ptr addrspace(1) %p, align 8352 ret void353}354 355define amdgpu_kernel void @udiv_constant_sel_constants_i64(ptr addrspace(1) %p, i1 %cond) {356; GCN-LABEL: udiv_constant_sel_constants_i64:357; GCN: ; %bb.0:358; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c359; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24360; GCN-NEXT: v_mov_b32_e32 v1, 0361; GCN-NEXT: s_waitcnt lgkmcnt(0)362; GCN-NEXT: s_bitcmp1_b32 s2, 0363; GCN-NEXT: s_cselect_b32 s2, 0, 5364; GCN-NEXT: v_mov_b32_e32 v0, s2365; GCN-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]366; GCN-NEXT: s_endpgm367 %sel = select i1 %cond, i64 -4, i64 23368 %bo = udiv i64 120, %sel369 store i64 %bo, ptr addrspace(1) %p, align 8370 ret void371}372 373define amdgpu_kernel void @srem_constant_sel_constants(ptr addrspace(1) %p, i1 %cond) {374; GCN-LABEL: srem_constant_sel_constants:375; GCN: ; %bb.0:376; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c377; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24378; GCN-NEXT: v_mov_b32_e32 v1, 0379; GCN-NEXT: s_waitcnt lgkmcnt(0)380; GCN-NEXT: s_bitcmp1_b32 s2, 0381; GCN-NEXT: s_cselect_b32 s2, 33, 3382; GCN-NEXT: v_mov_b32_e32 v0, s2383; GCN-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]384; GCN-NEXT: s_endpgm385 %sel = select i1 %cond, i64 34, i64 15386 %bo = srem i64 33, %sel387 store i64 %bo, ptr addrspace(1) %p, align 8388 ret void389}390 391define amdgpu_kernel void @urem_constant_sel_constants(ptr addrspace(1) %p, i1 %cond) {392; GCN-LABEL: urem_constant_sel_constants:393; GCN: ; %bb.0:394; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c395; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24396; GCN-NEXT: v_mov_b32_e32 v1, 0397; GCN-NEXT: s_waitcnt lgkmcnt(0)398; GCN-NEXT: s_bitcmp1_b32 s2, 0399; GCN-NEXT: s_cselect_b32 s2, 33, 3400; GCN-NEXT: v_mov_b32_e32 v0, s2401; GCN-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]402; GCN-NEXT: s_endpgm403 %sel = select i1 %cond, i64 34, i64 15404 %bo = urem i64 33, %sel405 store i64 %bo, ptr addrspace(1) %p, align 8406 ret void407}408 409define amdgpu_kernel void @shl_constant_sel_constants(ptr addrspace(1) %p, i1 %cond) {410; GCN-LABEL: shl_constant_sel_constants:411; GCN: ; %bb.0:412; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c413; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24414; GCN-NEXT: v_mov_b32_e32 v0, 0415; GCN-NEXT: s_waitcnt lgkmcnt(0)416; GCN-NEXT: s_bitcmp1_b32 s2, 0417; GCN-NEXT: s_cselect_b32 s2, 4, 8418; GCN-NEXT: v_mov_b32_e32 v1, s2419; GCN-NEXT: global_store_dword v0, v1, s[0:1]420; GCN-NEXT: s_endpgm421 %sel = select i1 %cond, i32 2, i32 3422 %bo = shl i32 1, %sel423 store i32 %bo, ptr addrspace(1) %p, align 4424 ret void425}426 427define amdgpu_kernel void @lshr_constant_sel_constants(ptr addrspace(1) %p, i1 %cond) {428; GCN-LABEL: lshr_constant_sel_constants:429; GCN: ; %bb.0:430; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c431; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24432; GCN-NEXT: v_mov_b32_e32 v0, 0433; GCN-NEXT: s_waitcnt lgkmcnt(0)434; GCN-NEXT: s_bitcmp1_b32 s2, 0435; GCN-NEXT: s_cselect_b32 s2, 16, 8436; GCN-NEXT: v_mov_b32_e32 v1, s2437; GCN-NEXT: global_store_dword v0, v1, s[0:1]438; GCN-NEXT: s_endpgm439 %sel = select i1 %cond, i32 2, i32 3440 %bo = lshr i32 64, %sel441 store i32 %bo, ptr addrspace(1) %p, align 4442 ret void443}444 445define amdgpu_kernel void @ashr_constant_sel_constants(ptr addrspace(1) %p, i1 %cond) {446; GCN-LABEL: ashr_constant_sel_constants:447; GCN: ; %bb.0:448; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c449; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24450; GCN-NEXT: v_mov_b32_e32 v0, 0451; GCN-NEXT: s_waitcnt lgkmcnt(0)452; GCN-NEXT: s_bitcmp1_b32 s2, 0453; GCN-NEXT: s_cselect_b32 s2, 32, 16454; GCN-NEXT: v_mov_b32_e32 v1, s2455; GCN-NEXT: global_store_dword v0, v1, s[0:1]456; GCN-NEXT: s_endpgm457 %sel = select i1 %cond, i32 2, i32 3458 %bo = ashr i32 128, %sel459 store i32 %bo, ptr addrspace(1) %p, align 4460 ret void461}462 463define amdgpu_kernel void @fsub_constant_sel_constants(ptr addrspace(1) %p, i1 %cond) {464; GCN-LABEL: fsub_constant_sel_constants:465; GCN: ; %bb.0:466; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c467; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24468; GCN-NEXT: v_mov_b32_e32 v0, 0469; GCN-NEXT: s_waitcnt lgkmcnt(0)470; GCN-NEXT: s_bitcmp1_b32 s2, 0471; GCN-NEXT: s_cselect_b64 s[2:3], -1, 0472; GCN-NEXT: v_cndmask_b32_e64 v1, -4.0, 1.0, s[2:3]473; GCN-NEXT: global_store_dword v0, v1, s[0:1]474; GCN-NEXT: s_endpgm475 %sel = select i1 %cond, float -2.0, float 3.0476 %bo = fsub float -1.0, %sel477 store float %bo, ptr addrspace(1) %p, align 4478 ret void479}480 481; TODO: it shall be possible to fold constants with OpSel482define amdgpu_kernel void @fsub_constant_sel_constants_f16(ptr addrspace(1) %p, i1 %cond) {483; GCN-LABEL: fsub_constant_sel_constants_f16:484; GCN: ; %bb.0:485; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c486; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24487; GCN-NEXT: v_mov_b32_e32 v1, 0xc400488; GCN-NEXT: v_mov_b32_e32 v2, 0x3c00489; GCN-NEXT: v_mov_b32_e32 v0, 0490; GCN-NEXT: s_waitcnt lgkmcnt(0)491; GCN-NEXT: s_bitcmp1_b32 s2, 0492; GCN-NEXT: s_cselect_b64 vcc, -1, 0493; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc494; GCN-NEXT: global_store_short v0, v1, s[0:1]495; GCN-NEXT: s_endpgm496 %sel = select i1 %cond, half -2.0, half 3.0497 %bo = fsub half -1.0, %sel498 store half %bo, ptr addrspace(1) %p, align 2499 ret void500}501 502define amdgpu_kernel void @fsub_constant_sel_constants_v2f16(ptr addrspace(1) %p, i1 %cond) {503; GCN-LABEL: fsub_constant_sel_constants_v2f16:504; GCN: ; %bb.0:505; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c506; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24507; GCN-NEXT: v_mov_b32_e32 v0, 0508; GCN-NEXT: s_waitcnt lgkmcnt(0)509; GCN-NEXT: s_bitcmp1_b32 s2, 0510; GCN-NEXT: s_cselect_b32 s2, 0x45003c00, -2.0511; GCN-NEXT: v_mov_b32_e32 v1, s2512; GCN-NEXT: global_store_dword v0, v1, s[0:1]513; GCN-NEXT: s_endpgm514 %sel = select i1 %cond, <2 x half> <half -2.0, half -3.0>, <2 x half> <half -1.0, half 4.0>515 %bo = fsub <2 x half> <half -1.0, half 2.0>, %sel516 store <2 x half> %bo, ptr addrspace(1) %p, align 4517 ret void518}519 520define amdgpu_kernel void @fsub_constant_sel_constants_v4f32(ptr addrspace(1) %p, i1 %cond) {521; GFX9-LABEL: fsub_constant_sel_constants_v4f32:522; GFX9: ; %bb.0:523; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c524; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24525; GFX9-NEXT: s_mov_b32 s3, 0x41500000526; GFX9-NEXT: v_mov_b32_e32 v4, 0527; GFX9-NEXT: s_waitcnt lgkmcnt(0)528; GFX9-NEXT: s_bitcmp1_b32 s2, 0529; GFX9-NEXT: s_cselect_b32 s2, s3, 0x40c00000530; GFX9-NEXT: s_cselect_b32 s3, 0x41100000, 4.0531; GFX9-NEXT: s_cselect_b32 s4, 0x40a00000, 2.0532; GFX9-NEXT: s_cselect_b32 s5, 1.0, 0533; GFX9-NEXT: v_mov_b32_e32 v0, s5534; GFX9-NEXT: v_mov_b32_e32 v1, s4535; GFX9-NEXT: v_mov_b32_e32 v2, s3536; GFX9-NEXT: v_mov_b32_e32 v3, s2537; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]538; GFX9-NEXT: s_endpgm539;540; GFX942-LABEL: fsub_constant_sel_constants_v4f32:541; GFX942: ; %bb.0:542; GFX942-NEXT: s_load_dword s2, s[4:5], 0x2c543; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24544; GFX942-NEXT: s_mov_b32 s3, 0x41500000545; GFX942-NEXT: v_mov_b32_e32 v0, 0546; GFX942-NEXT: s_waitcnt lgkmcnt(0)547; GFX942-NEXT: s_bitcmp1_b32 s2, 0548; GFX942-NEXT: s_cselect_b32 s2, s3, 0x40c00000549; GFX942-NEXT: s_cselect_b32 s3, 0x41100000, 4.0550; GFX942-NEXT: s_cselect_b32 s4, 0x40a00000, 2.0551; GFX942-NEXT: s_cselect_b32 s5, 1.0, 0552; GFX942-NEXT: v_mov_b32_e32 v2, s5553; GFX942-NEXT: v_mov_b32_e32 v3, s4554; GFX942-NEXT: v_mov_b32_e32 v4, s3555; GFX942-NEXT: v_mov_b32_e32 v5, s2556; GFX942-NEXT: global_store_dwordx4 v0, v[2:5], s[0:1]557; GFX942-NEXT: s_endpgm558 %sel = select i1 %cond, <4 x float> <float -2.0, float -3.0, float -4.0, float -5.0>, <4 x float> <float -1.0, float 0.0, float 1.0, float 2.0>559 %bo = fsub <4 x float> <float -1.0, float 2.0, float 5.0, float 8.0>, %sel560 store <4 x float> %bo, ptr addrspace(1) %p, align 32561 ret void562}563 564define amdgpu_kernel void @fdiv_constant_sel_constants(ptr addrspace(1) %p, i1 %cond) {565; GCN-LABEL: fdiv_constant_sel_constants:566; GCN: ; %bb.0:567; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c568; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24569; GCN-NEXT: v_mov_b32_e32 v0, 0570; GCN-NEXT: s_waitcnt lgkmcnt(0)571; GCN-NEXT: s_bitcmp1_b32 s2, 0572; GCN-NEXT: s_cselect_b64 s[2:3], -1, 0573; GCN-NEXT: v_cndmask_b32_e64 v1, 4.0, -2.0, s[2:3]574; GCN-NEXT: global_store_dword v0, v1, s[0:1]575; GCN-NEXT: s_endpgm576 %sel = select i1 %cond, float -4.0, float 2.0577 %bo = fdiv float 8.0, %sel578 store float %bo, ptr addrspace(1) %p, align 4579 ret void580}581 582; ExpandFp now expands frem before it reaches dagcombine.583; TODO Implement this optimization in/before ExpandFP584define amdgpu_kernel void @frem_constant_sel_constants(ptr addrspace(1) %p, i1 %cond) {585; GFX9-LABEL: frem_constant_sel_constants:586; GFX9: ; %bb.0:587; GFX9-NEXT: s_load_dword s0, s[4:5], 0x2c588; GFX9-NEXT: v_mov_b32_e32 v0, 0x40400000589; GFX9-NEXT: s_waitcnt lgkmcnt(0)590; GFX9-NEXT: s_bitcmp1_b32 s0, 0591; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0592; GFX9-NEXT: v_cndmask_b32_e64 v1, v0, -4.0, s[0:1]593; GFX9-NEXT: s_mov_b32 s0, 0x40a00000594; GFX9-NEXT: v_cmp_nlt_f32_e64 s[2:3], |v1|, s0595; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]596; GFX9-NEXT: s_cbranch_vccz .LBB26_2597; GFX9-NEXT: ; %bb.1: ; %frem.else598; GFX9-NEXT: v_mov_b32_e32 v0, 0x40a00000599; GFX9-NEXT: v_cmp_eq_f32_e64 s[0:1], |v1|, s0600; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1]601; GFX9-NEXT: s_cbranch_execz .LBB26_3602; GFX9-NEXT: s_branch .LBB26_7603; GFX9-NEXT: .LBB26_2:604; GFX9-NEXT: ; implicit-def: $vgpr0605; GFX9-NEXT: .LBB26_3: ; %frem.compute606; GFX9-NEXT: v_frexp_mant_f32_e64 v0, |v1|607; GFX9-NEXT: v_ldexp_f32 v0, v0, 1608; GFX9-NEXT: v_div_scale_f32 v2, s[0:1], v0, v0, 1.0609; GFX9-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0610; GFX9-NEXT: v_rcp_f32_e32 v4, v2611; GFX9-NEXT: v_fma_f32 v5, -v2, v4, 1.0612; GFX9-NEXT: v_fma_f32 v4, v5, v4, v4613; GFX9-NEXT: v_mul_f32_e32 v5, v3, v4614; GFX9-NEXT: v_fma_f32 v6, -v2, v5, v3615; GFX9-NEXT: v_fma_f32 v5, v6, v4, v5616; GFX9-NEXT: v_fma_f32 v2, -v2, v5, v3617; GFX9-NEXT: v_div_fmas_f32 v3, v2, v4, v5618; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v2, v1619; GFX9-NEXT: v_sub_u32_e32 v1, 3, v2620; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v1621; GFX9-NEXT: v_mov_b32_e32 v4, 0x45200000622; GFX9-NEXT: v_div_fixup_f32 v3, v3, v0, 1.0623; GFX9-NEXT: s_cbranch_vccnz .LBB26_6624; GFX9-NEXT: ; %bb.4: ; %frem.loop_body.preheader625; GFX9-NEXT: v_sub_u32_e32 v1, 15, v2626; GFX9-NEXT: v_mov_b32_e32 v5, 0x45200000627; GFX9-NEXT: .LBB26_5: ; %frem.loop_body628; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1629; GFX9-NEXT: v_mov_b32_e32 v4, v5630; GFX9-NEXT: v_mul_f32_e32 v5, v4, v3631; GFX9-NEXT: v_rndne_f32_e32 v5, v5632; GFX9-NEXT: v_fma_f32 v5, -v5, v0, v4633; GFX9-NEXT: v_add_f32_e32 v6, v5, v0634; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5635; GFX9-NEXT: v_add_u32_e32 v1, -12, v1636; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc637; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v1638; GFX9-NEXT: v_ldexp_f32 v5, v5, 12639; GFX9-NEXT: s_cbranch_vccnz .LBB26_5640; GFX9-NEXT: .LBB26_6: ; %Flow12641; GFX9-NEXT: v_add_u32_e32 v1, -11, v1642; GFX9-NEXT: v_ldexp_f32 v1, v4, v1643; GFX9-NEXT: v_mul_f32_e32 v3, v1, v3644; GFX9-NEXT: v_rndne_f32_e32 v3, v3645; GFX9-NEXT: v_fma_f32 v1, -v3, v0, v1646; GFX9-NEXT: v_add_f32_e32 v0, v1, v0647; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1648; GFX9-NEXT: v_add_u32_e32 v2, -1, v2649; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc650; GFX9-NEXT: v_ldexp_f32 v0, v0, v2651; GFX9-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0652; GFX9-NEXT: .LBB26_7: ; %Flow14653; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24654; GFX9-NEXT: v_mov_b32_e32 v1, 0655; GFX9-NEXT: s_waitcnt lgkmcnt(0)656; GFX9-NEXT: global_store_dword v1, v0, s[0:1]657; GFX9-NEXT: s_endpgm658;659; GFX942-LABEL: frem_constant_sel_constants:660; GFX942: ; %bb.0:661; GFX942-NEXT: s_load_dword s0, s[4:5], 0x2c662; GFX942-NEXT: v_mov_b32_e32 v0, 0x40400000663; GFX942-NEXT: s_waitcnt lgkmcnt(0)664; GFX942-NEXT: s_bitcmp1_b32 s0, 0665; GFX942-NEXT: s_cselect_b64 s[0:1], -1, 0666; GFX942-NEXT: v_cndmask_b32_e64 v1, v0, -4.0, s[0:1]667; GFX942-NEXT: s_mov_b32 s0, 0x40a00000668; GFX942-NEXT: v_cmp_nlt_f32_e64 s[2:3], |v1|, s0669; GFX942-NEXT: s_and_b64 vcc, exec, s[2:3]670; GFX942-NEXT: s_cbranch_vccz .LBB26_2671; GFX942-NEXT: ; %bb.1: ; %frem.else672; GFX942-NEXT: v_mov_b32_e32 v0, 0x40a00000673; GFX942-NEXT: v_cmp_eq_f32_e64 s[0:1], |v1|, s0674; GFX942-NEXT: s_nop 1675; GFX942-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1]676; GFX942-NEXT: s_cbranch_execz .LBB26_3677; GFX942-NEXT: s_branch .LBB26_7678; GFX942-NEXT: .LBB26_2:679; GFX942-NEXT: ; implicit-def: $vgpr0680; GFX942-NEXT: .LBB26_3: ; %frem.compute681; GFX942-NEXT: v_frexp_mant_f32_e64 v0, |v1|682; GFX942-NEXT: v_ldexp_f32 v0, v0, 1683; GFX942-NEXT: v_div_scale_f32 v3, s[0:1], v0, v0, 1.0684; GFX942-NEXT: v_rcp_f32_e32 v4, v3685; GFX942-NEXT: v_frexp_exp_i32_f32_e32 v2, v1686; GFX942-NEXT: v_sub_u32_e32 v1, 3, v2687; GFX942-NEXT: v_fma_f32 v5, -v3, v4, 1.0688; GFX942-NEXT: v_fmac_f32_e32 v4, v5, v4689; GFX942-NEXT: v_div_scale_f32 v5, vcc, 1.0, v0, 1.0690; GFX942-NEXT: v_mul_f32_e32 v6, v5, v4691; GFX942-NEXT: v_fma_f32 v7, -v3, v6, v5692; GFX942-NEXT: v_fmac_f32_e32 v6, v7, v4693; GFX942-NEXT: v_fma_f32 v3, -v3, v6, v5694; GFX942-NEXT: v_div_fmas_f32 v3, v3, v4, v6695; GFX942-NEXT: v_cmp_gt_i32_e32 vcc, 13, v1696; GFX942-NEXT: v_div_fixup_f32 v3, v3, v0, 1.0697; GFX942-NEXT: v_mov_b32_e32 v4, 0x45200000698; GFX942-NEXT: s_cbranch_vccnz .LBB26_6699; GFX942-NEXT: ; %bb.4: ; %frem.loop_body.preheader700; GFX942-NEXT: v_sub_u32_e32 v1, 15, v2701; GFX942-NEXT: v_mov_b32_e32 v5, 0x45200000702; GFX942-NEXT: .LBB26_5: ; %frem.loop_body703; GFX942-NEXT: ; =>This Inner Loop Header: Depth=1704; GFX942-NEXT: v_mov_b32_e32 v4, v5705; GFX942-NEXT: v_mul_f32_e32 v5, v4, v3706; GFX942-NEXT: v_rndne_f32_e32 v5, v5707; GFX942-NEXT: v_fma_f32 v5, -v5, v0, v4708; GFX942-NEXT: v_add_f32_e32 v6, v5, v0709; GFX942-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5710; GFX942-NEXT: v_add_u32_e32 v1, -12, v1711; GFX942-NEXT: s_nop 0712; GFX942-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc713; GFX942-NEXT: v_cmp_lt_i32_e32 vcc, 12, v1714; GFX942-NEXT: v_ldexp_f32 v5, v5, 12715; GFX942-NEXT: s_cbranch_vccnz .LBB26_5716; GFX942-NEXT: .LBB26_6: ; %Flow12717; GFX942-NEXT: v_add_u32_e32 v1, -11, v1718; GFX942-NEXT: v_ldexp_f32 v1, v4, v1719; GFX942-NEXT: v_mul_f32_e32 v3, v1, v3720; GFX942-NEXT: v_rndne_f32_e32 v3, v3721; GFX942-NEXT: v_fma_f32 v1, -v3, v0, v1722; GFX942-NEXT: v_add_f32_e32 v0, v1, v0723; GFX942-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1724; GFX942-NEXT: v_add_u32_e32 v2, -1, v2725; GFX942-NEXT: s_nop 0726; GFX942-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc727; GFX942-NEXT: v_ldexp_f32 v0, v0, v2728; GFX942-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0729; GFX942-NEXT: .LBB26_7: ; %Flow14730; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24731; GFX942-NEXT: v_mov_b32_e32 v1, 0732; GFX942-NEXT: s_waitcnt lgkmcnt(0)733; GFX942-NEXT: global_store_dword v1, v0, s[0:1]734; GFX942-NEXT: s_endpgm735 %sel = select i1 %cond, float -4.0, float 3.0736 %bo = frem float 5.0, %sel737 store float %bo, ptr addrspace(1) %p, align 4738 ret void739}740