28 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-misched -run-pass=machine-scheduler -o - %s | FileCheck %s3 4# Verify we maintain live-ins even if the first instruction in sched region is5# DBG_.6 7---8name: sched9tracksRegLiveness: true10body: |11 bb.0:12 ; CHECK-LABEL: name: sched13 ; CHECK: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF14 ; CHECK-NEXT: S_NOP 015 ; CHECK-NEXT: SCHED_BARRIER 016 ; CHECK-NEXT: DBG_VALUE17 ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:sgpr_32 = COPY [[DEF]]18 ; CHECK-NEXT: S_NOP 019 ; CHECK-NEXT: S_ENDPGM 020 %0:sgpr_32 = IMPLICIT_DEF21 S_NOP 022 SCHED_BARRIER 023 DBG_VALUE24 dead %1:sgpr_32 = COPY %025 S_NOP 026 S_ENDPGM 027...28