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1# RUN: llc -mtriple=amdgcn -run-pass detect-dead-lanes -o - %s | FileCheck %s2# RUN: llc -mtriple=amdgcn -passes detect-dead-lanes -o - %s | FileCheck %s3...4---5# Combined use/def transfer check, the basics.6# CHECK-LABEL: name: test07# CHECK: S_NOP 0, implicit-def %08# CHECK: S_NOP 0, implicit-def %19# CHECK: S_NOP 0, implicit-def dead %210# CHECK: %3:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, undef %2, %subreg.sub311# CHECK: S_NOP 0, implicit %3.sub012# CHECK: S_NOP 0, implicit %3.sub113# CHECK: S_NOP 0, implicit undef %3.sub214# CHECK: %4:sreg_64 = COPY %3.sub0_sub115# CHECK: %5:sreg_64 = COPY undef %3.sub2_sub316# CHECK: S_NOP 0, implicit %4.sub017# CHECK: S_NOP 0, implicit %4.sub118# CHECK: S_NOP 0, implicit undef %5.sub019name: test020registers:21 - { id: 0, class: sreg_32_xm0 }22 - { id: 1, class: sreg_32_xm0 }23 - { id: 2, class: sreg_32_xm0 }24 - { id: 3, class: sgpr_128 }25 - { id: 4, class: sreg_64 }26 - { id: 5, class: sreg_64 }27body: |28 bb.0:29 S_NOP 0, implicit-def %030 S_NOP 0, implicit-def %131 S_NOP 0, implicit-def %232 %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub333 S_NOP 0, implicit %3.sub034 S_NOP 0, implicit %3.sub135 S_NOP 0, implicit %3.sub236 %4 = COPY %3.sub0_sub137 %5 = COPY %3.sub2_sub338 S_NOP 0, implicit %4.sub039 S_NOP 0, implicit %4.sub140 S_NOP 0, implicit %5.sub041...42---43# Check defined lanes transfer; Includes checking for some special cases like44# undef operands or IMPLICIT_DEF definitions.45# CHECK-LABEL: name: test146# CHECK: %0:sgpr_128 = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr0, %subreg.sub247# CHECK: %1:sgpr_128 = INSERT_SUBREG %0, $sgpr1, %subreg.sub348# CHECK: %2:sreg_64 = INSERT_SUBREG %0.sub2_sub3, $sgpr42, %subreg.sub049# CHECK: S_NOP 0, implicit %1.sub050# CHECK: S_NOP 0, implicit undef %1.sub151# CHECK: S_NOP 0, implicit %1.sub252# CHECK: S_NOP 0, implicit %1.sub353# CHECK: S_NOP 0, implicit %2.sub054# CHECK: S_NOP 0, implicit undef %2.sub155 56# CHECK: %3:sreg_32_xm0 = IMPLICIT_DEF57# CHECK: %4:sgpr_128 = INSERT_SUBREG %0, undef %3, %subreg.sub058# CHECK: S_NOP 0, implicit undef %4.sub059# CHECK: S_NOP 0, implicit undef %4.sub160# CHECK: S_NOP 0, implicit %4.sub261# CHECK: S_NOP 0, implicit undef %4.sub362 63# CHECK: %5:sreg_64 = EXTRACT_SUBREG %0, %subreg.sub0_sub164# CHECK: %6:sreg_32_xm0 = EXTRACT_SUBREG %5, %subreg.sub065# CHECK: %7:sreg_32_xm0 = EXTRACT_SUBREG %5, %subreg.sub166# CHECK: S_NOP 0, implicit %567# CHECK: S_NOP 0, implicit %668# CHECK: S_NOP 0, implicit undef %769 70# CHECK: %8:sreg_64 = IMPLICIT_DEF71# CHECK: %9:sreg_32_xm0 = EXTRACT_SUBREG undef %8, %subreg.sub172# CHECK: S_NOP 0, implicit undef %973 74# CHECK: %10:sgpr_128 = EXTRACT_SUBREG undef %0, %subreg.sub2_sub375# CHECK: S_NOP 0, implicit undef %1076name: test177registers:78 - { id: 0, class: sgpr_128 }79 - { id: 1, class: sgpr_128 }80 - { id: 2, class: sreg_64 }81 - { id: 3, class: sreg_32_xm0 }82 - { id: 4, class: sgpr_128 }83 - { id: 5, class: sreg_64 }84 - { id: 6, class: sreg_32_xm0 }85 - { id: 7, class: sreg_32_xm0 }86 - { id: 8, class: sreg_64 }87 - { id: 9, class: sreg_32_xm0 }88 - { id: 10, class: sgpr_128 }89body: |90 bb.0:91 %0 = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr0, %subreg.sub292 %1 = INSERT_SUBREG %0, $sgpr1, %subreg.sub393 %2 = INSERT_SUBREG %0.sub2_sub3, $sgpr42, %subreg.sub094 S_NOP 0, implicit %1.sub095 S_NOP 0, implicit %1.sub196 S_NOP 0, implicit %1.sub297 S_NOP 0, implicit %1.sub398 S_NOP 0, implicit %2.sub099 S_NOP 0, implicit %2.sub1100 101 %3 = IMPLICIT_DEF102 %4 = INSERT_SUBREG %0, %3, %subreg.sub0103 S_NOP 0, implicit %4.sub0104 S_NOP 0, implicit %4.sub1105 S_NOP 0, implicit %4.sub2106 S_NOP 0, implicit %4.sub3107 108 %5 = EXTRACT_SUBREG %0, %subreg.sub0_sub1109 %6 = EXTRACT_SUBREG %5, %subreg.sub0110 %7 = EXTRACT_SUBREG %5, %subreg.sub1111 S_NOP 0, implicit %5112 S_NOP 0, implicit %6113 S_NOP 0, implicit %7114 115 %8 = IMPLICIT_DEF116 %9 = EXTRACT_SUBREG %8, %subreg.sub1117 S_NOP 0, implicit %9118 119 %10 = EXTRACT_SUBREG undef %0, %subreg.sub2_sub3120 S_NOP 0, implicit %10121...122---123# Check used lanes transfer; Includes checking for some special cases like124# undef operands.125# CHECK-LABEL: name: test2126# CHECK: S_NOP 0, implicit-def dead %0127# CHECK: S_NOP 0, implicit-def %1128# CHECK: S_NOP 0, implicit-def %2129# CHECK: %3:sgpr_128 = REG_SEQUENCE undef %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2_sub3130# CHECK: S_NOP 0, implicit %3.sub1131# CHECK: S_NOP 0, implicit %3.sub3132 133# CHECK: S_NOP 0, implicit-def %4134# CHECK: S_NOP 0, implicit-def dead %5135# CHECK: %6:sreg_64 = REG_SEQUENCE %4, %subreg.sub0, undef %5, %subreg.sub1136# CHECK: S_NOP 0, implicit %6137 138# CHECK: S_NOP 0, implicit-def dead %7139# CHECK: S_NOP 0, implicit-def %8140# CHECK: %9:sgpr_128 = INSERT_SUBREG undef %7, %8, %subreg.sub2_sub3141# CHECK: S_NOP 0, implicit %9.sub2142 143# CHECK: S_NOP 0, implicit-def %10144# CHECK: S_NOP 0, implicit-def dead %11145# CHECK: %12:sgpr_128 = INSERT_SUBREG %10, undef %11, %subreg.sub0_sub1146# CHECK: S_NOP 0, implicit %12.sub3147 148# CHECK: S_NOP 0, implicit-def %13149# CHECK: S_NOP 0, implicit-def dead %14150# CHECK: %15:sgpr_128 = REG_SEQUENCE %13, %subreg.sub0_sub1, undef %14, %subreg.sub2_sub3151# CHECK: %16:sreg_64 = EXTRACT_SUBREG %15, %subreg.sub0_sub1152# CHECK: S_NOP 0, implicit %16.sub1153 154name: test2155registers:156 - { id: 0, class: sreg_32_xm0 }157 - { id: 1, class: sreg_32_xm0 }158 - { id: 2, class: sreg_64 }159 - { id: 3, class: sgpr_128 }160 - { id: 4, class: sreg_32_xm0 }161 - { id: 5, class: sreg_32_xm0 }162 - { id: 6, class: sreg_64 }163 - { id: 7, class: sgpr_128 }164 - { id: 8, class: sreg_64 }165 - { id: 9, class: sgpr_128 }166 - { id: 10, class: sgpr_128 }167 - { id: 11, class: sreg_64 }168 - { id: 12, class: sgpr_128 }169 - { id: 13, class: sreg_64 }170 - { id: 14, class: sreg_64 }171 - { id: 15, class: sgpr_128 }172 - { id: 16, class: sreg_64 }173body: |174 bb.0:175 S_NOP 0, implicit-def %0176 S_NOP 0, implicit-def %1177 S_NOP 0, implicit-def %2178 %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2_sub3179 S_NOP 0, implicit %3.sub1180 S_NOP 0, implicit %3.sub3181 182 S_NOP 0, implicit-def %4183 S_NOP 0, implicit-def %5184 %6 = REG_SEQUENCE %4, %subreg.sub0, undef %5, %subreg.sub1185 S_NOP 0, implicit %6186 187 S_NOP 0, implicit-def %7188 S_NOP 0, implicit-def %8189 %9 = INSERT_SUBREG %7, %8, %subreg.sub2_sub3190 S_NOP 0, implicit %9.sub2191 192 S_NOP 0, implicit-def %10193 S_NOP 0, implicit-def %11194 %12 = INSERT_SUBREG %10, %11, %subreg.sub0_sub1195 S_NOP 0, implicit %12.sub3196 197 S_NOP 0, implicit-def %13198 S_NOP 0, implicit-def %14199 %15 = REG_SEQUENCE %13, %subreg.sub0_sub1, %14, %subreg.sub2_sub3200 %16 = EXTRACT_SUBREG %15, %subreg.sub0_sub1201 S_NOP 0, implicit %16.sub1202...203---204# Check that copies to physregs use all lanes, copies from physregs define all205# lanes. So we should not get a dead/undef flag here.206# CHECK-LABEL: name: test3207# CHECK: S_NOP 0, implicit-def %0208# CHECK: $vcc = COPY %0209# CHECK: %1:sreg_64 = COPY $vcc210# CHECK: S_NOP 0, implicit %1211name: test3212tracksRegLiveness: true213registers:214 - { id: 0, class: sreg_64 }215 - { id: 1, class: sreg_64 }216body: |217 bb.0:218 S_NOP 0, implicit-def %0219 $vcc = COPY %0220 221 %1 = COPY $vcc222 S_NOP 0, implicit %1223...224---225# Check that implicit-def/kill do not count as def/uses.226# CHECK-LABEL: name: test4227# CHECK: S_NOP 0, implicit-def dead %0228# CHECK: KILL undef %0229# CHECK: %1:sreg_64 = IMPLICIT_DEF230# CHECK: S_NOP 0, implicit undef %1231name: test4232tracksRegLiveness: true233registers:234 - { id: 0, class: sreg_64 }235 - { id: 1, class: sreg_64 }236body: |237 bb.0:238 S_NOP 0, implicit-def %0239 KILL %0240 241 %1 = IMPLICIT_DEF242 S_NOP 0, implicit %1243...244---245# Check that unused inputs are marked as undef, even if the vreg itself is246# used.247# CHECK-LABEL: name: test5248# CHECK: S_NOP 0, implicit-def %0249# CHECK: %1:sreg_64 = REG_SEQUENCE undef %0, %subreg.sub0, %0, %subreg.sub1250# CHECK: S_NOP 0, implicit %1.sub1251name: test5252tracksRegLiveness: true253registers:254 - { id: 0, class: sreg_32_xm0 }255 - { id: 1, class: sreg_64 }256body: |257 bb.0:258 S_NOP 0, implicit-def %0259 %1 = REG_SEQUENCE %0, %subreg.sub0, %0, %subreg.sub1260 S_NOP 0, implicit %1.sub1261...262---263# Check "optimistic" dataflow fixpoint in phi-loops.264# CHECK-LABEL: name: loop0265# CHECK: bb.0:266# CHECK: S_NOP 0, implicit-def %0267# CHECK: S_NOP 0, implicit-def dead %1268# CHECK: S_NOP 0, implicit-def dead %2269# CHECK: %3:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, undef %1, %subreg.sub1, undef %2, %subreg.sub2270 271# CHECK: bb.1:272# CHECK: %4:sgpr_128 = PHI %3, %bb.0, %5, %bb.1273 274# CHECK: bb.2:275# CHECK: S_NOP 0, implicit %4.sub0276# CHECK: S_NOP 0, implicit undef %4.sub3277name: loop0278tracksRegLiveness: true279registers:280 - { id: 0, class: sreg_32_xm0 }281 - { id: 1, class: sreg_32_xm0 }282 - { id: 2, class: sreg_32_xm0 }283 - { id: 3, class: sgpr_128 }284 - { id: 4, class: sgpr_128 }285 - { id: 5, class: sgpr_128 }286body: |287 bb.0:288 S_NOP 0, implicit-def %0289 S_NOP 0, implicit-def %1290 S_NOP 0, implicit-def %2291 %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2292 S_BRANCH %bb.1293 294 bb.1:295 %4 = PHI %3, %bb.0, %5, %bb.1296 297 ; let's swiffle some lanes around for fun...298 %5 = REG_SEQUENCE %4.sub0, %subreg.sub0, %4.sub2, %subreg.sub1, %4.sub1, %subreg.sub2, %4.sub3, %subreg.sub3299 300 S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc301 S_BRANCH %bb.2302 303 bb.2:304 S_NOP 0, implicit %4.sub0305 S_NOP 0, implicit %4.sub3306...307---308# Check a loop that needs to be traversed multiple times to reach the fixpoint309# for the used lanes. The example reads sub3 lane at the end, however with each310# loop iteration we should get 1 more lane marked as we cycles the sublanes311# along. Sublanes sub0, sub1 and sub3 are rotate in the loop so only sub2312# should be dead.313# CHECK-LABEL: name: loop1314# CHECK: bb.0:315# CHECK: S_NOP 0, implicit-def %0316# CHECK: S_NOP 0, implicit-def %1317# CHECK: S_NOP 0, implicit-def dead %2318# CHECK: S_NOP 0, implicit-def %3319# CHECK: %4:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, undef %2, %subreg.sub2, %3, %subreg.sub3320 321# CHECK: bb.1:322# CHECK: %5:sgpr_128 = PHI %4, %bb.0, %6, %bb.1323 324# CHECK: %6:sgpr_128 = REG_SEQUENCE %5.sub1, %subreg.sub0, %5.sub3, %subreg.sub1, undef %5.sub2, %subreg.sub2, %5.sub0, %subreg.sub3325 326# CHECK: bb.2:327# CHECK: S_NOP 0, implicit %6.sub3328name: loop1329tracksRegLiveness: true330registers:331 - { id: 0, class: sreg_32_xm0 }332 - { id: 1, class: sreg_32_xm0 }333 - { id: 2, class: sreg_32_xm0 }334 - { id: 3, class: sreg_32_xm0 }335 - { id: 4, class: sgpr_128 }336 - { id: 5, class: sgpr_128 }337 - { id: 6, class: sgpr_128 }338body: |339 bb.0:340 S_NOP 0, implicit-def %0341 S_NOP 0, implicit-def %1342 S_NOP 0, implicit-def dead %2343 S_NOP 0, implicit-def %3344 %4 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3345 S_BRANCH %bb.1346 347 bb.1:348 %5 = PHI %4, %bb.0, %6, %bb.1349 350 ; rotate lanes, but skip sub2 lane...351 %6 = REG_SEQUENCE %5.sub1, %subreg.sub0, %5.sub3, %subreg.sub1, %5.sub2, %subreg.sub2, %5.sub0, %subreg.sub3352 353 S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc354 S_BRANCH %bb.2355 356 bb.2:357 S_NOP 0, implicit %6.sub3358...359---360# Similar to loop1 test, but check for fixpoint of defined lanes.361# Lanes are rotate between sub0, sub2, sub3 so only sub1 should be dead/undef.362# CHECK-LABEL: name: loop2363# CHECK: bb.0:364# CHECK: S_NOP 0, implicit-def %0365# CHECK: %1:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0366 367# CHECK: bb.1:368# CHECK: %2:sgpr_128 = PHI %1, %bb.0, %3, %bb.1369 370# CHECK: %3:sgpr_128 = REG_SEQUENCE %2.sub3, %subreg.sub0, undef %2.sub1, %subreg.sub1, %2.sub0, %subreg.sub2, %2.sub2, %subreg.sub3371 372# CHECK: bb.2:373# CHECK: S_NOP 0, implicit %2.sub0374# CHECK: S_NOP 0, implicit undef %2.sub1375# CHECK: S_NOP 0, implicit %2.sub2376# CHECK: S_NOP 0, implicit %2.sub3377name: loop2378tracksRegLiveness: true379registers:380 - { id: 0, class: sreg_32_xm0 }381 - { id: 1, class: sgpr_128 }382 - { id: 2, class: sgpr_128 }383 - { id: 3, class: sgpr_128 }384body: |385 bb.0:386 S_NOP 0, implicit-def %0387 %1 = REG_SEQUENCE %0, %subreg.sub0388 S_BRANCH %bb.1389 390 bb.1:391 %2 = PHI %1, %bb.0, %3, %bb.1392 393 ; rotate subreg lanes, skipping sub1394 %3 = REG_SEQUENCE %2.sub3, %subreg.sub0, %2.sub1, %subreg.sub1, %2.sub0, %subreg.sub2, %2.sub2, %subreg.sub3395 396 S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc397 S_BRANCH %bb.2398 399 bb.2:400 S_NOP 0, implicit %2.sub0401 S_NOP 0, implicit undef %2.sub1402 S_NOP 0, implicit %2.sub2403 S_NOP 0, implicit %2.sub3404...405