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1; RUN: llc -mtriple=amdgcn -mcpu=gfx902 -stop-after=si-form-memory-clauses < %s | FileCheck -check-prefix=GCN %s2 3; GCN-LABEL: {{^}}name:{{[ ]*}}vector_clause4; GCN: S_LOAD_DWORDX45; GCN: GLOBAL_LOAD_DWORDX4_SADDR6; GCN: GLOBAL_LOAD_DWORDX4_SADDR7; GCN: GLOBAL_LOAD_DWORDX4_SADDR8; GCN: GLOBAL_LOAD_DWORDX4_SADDR9; GCN-NEXT: KILL10define amdgpu_kernel void @vector_clause(ptr addrspace(1) noalias nocapture readonly %arg, ptr addrspace(1) noalias nocapture %arg1) {11bb:12 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()13 %tmp2 = zext i32 %tmp to i6414 %tmp3 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp215 %tmp4 = load <4 x i32>, ptr addrspace(1) %tmp3, align 1616 %tmp5 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp217 %tmp6 = add nuw nsw i64 %tmp2, 118 %tmp7 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp619 %tmp8 = load <4 x i32>, ptr addrspace(1) %tmp7, align 1620 %tmp9 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp621 %tmp10 = add nuw nsw i64 %tmp2, 222 %tmp11 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp1023 %tmp12 = load <4 x i32>, ptr addrspace(1) %tmp11, align 1624 %tmp13 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp1025 %tmp14 = add nuw nsw i64 %tmp2, 326 %tmp15 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp1427 %tmp16 = load <4 x i32>, ptr addrspace(1) %tmp15, align 1628 %tmp17 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp1429 store <4 x i32> %tmp8, ptr addrspace(1) %tmp9, align 1630 store <4 x i32> %tmp4, ptr addrspace(1) %tmp5, align 1631 store <4 x i32> %tmp12, ptr addrspace(1) %tmp13, align 1632 store <4 x i32> %tmp16, ptr addrspace(1) %tmp17, align 1633 ret void34}35 36; GCN-LABEL: {{^}}name:{{[ ]*}}no_vector_clause37; GCN-NOT: BUNDLE38; GCN-NOT: KILL39define amdgpu_kernel void @no_vector_clause(ptr addrspace(1) noalias nocapture readonly %arg, ptr addrspace(1) noalias nocapture %arg1) #0 {40bb:41 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()42 %tmp2 = zext i32 %tmp to i6443 %tmp3 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp244 %tmp4 = load <4 x i32>, ptr addrspace(1) %tmp3, align 1645 %tmp5 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp246 %tmp6 = add nuw nsw i64 %tmp2, 147 %tmp7 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp648 %tmp8 = load <4 x i32>, ptr addrspace(1) %tmp7, align 1649 %tmp9 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp650 %tmp10 = add nuw nsw i64 %tmp2, 251 %tmp11 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp1052 %tmp12 = load <4 x i32>, ptr addrspace(1) %tmp11, align 1653 %tmp13 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp1054 %tmp14 = add nuw nsw i64 %tmp2, 355 %tmp15 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp1456 %tmp16 = load <4 x i32>, ptr addrspace(1) %tmp15, align 1657 %tmp17 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp1458 store <4 x i32> %tmp4, ptr addrspace(1) %tmp5, align 1659 store <4 x i32> %tmp8, ptr addrspace(1) %tmp9, align 1660 store <4 x i32> %tmp12, ptr addrspace(1) %tmp13, align 1661 store <4 x i32> %tmp16, ptr addrspace(1) %tmp17, align 1662 ret void63}64 65declare i32 @llvm.amdgcn.workitem.id.x()66 67attributes #0 = { "amdgpu-max-memory-clause"="1" }68 69