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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck -check-prefixes=GFX9 %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -o - %s | FileCheck -check-prefixes=GFX942 %s4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx9-4-generic --amdhsa-code-object-version=6 -o - %s | FileCheck -check-prefixes=GFX942 %s5; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -o - %s | FileCheck -check-prefixes=GFX1030 %s6 7; Sample test to check how we deal with division/modulos by 64 bit constants.8 9define noundef i64 @srem64_3(i64 noundef %i) {10; GFX9-LABEL: srem64_3:11; GFX9: ; %bb.0: ; %entry12; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; GFX9-NEXT: s_mov_b32 s6, 0x5555555614; GFX9-NEXT: v_mul_hi_u32 v2, v0, s615; GFX9-NEXT: v_mov_b32_e32 v3, 016; GFX9-NEXT: s_mov_b32 s7, 0x5555555517; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, s6, v[2:3]18; GFX9-NEXT: v_mov_b32_e32 v2, v419; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, s7, v[2:3]20; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v121; GFX9-NEXT: v_mul_lo_u32 v6, v4, s622; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v5, v323; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc24; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s7, v[2:3]25; GFX9-NEXT: v_mul_lo_u32 v5, v4, s726; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, s6, v[2:3]27; GFX9-NEXT: v_add3_u32 v3, v6, v3, v528; GFX9-NEXT: v_lshrrev_b32_e32 v4, 31, v329; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v430; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v3, vcc31; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, 3, 032; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v4, 3, v[3:4]33; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v234; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc35; GFX9-NEXT: s_setpc_b64 s[30:31]36;37; GFX942-LABEL: srem64_3:38; GFX942: ; %bb.0: ; %entry39; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)40; GFX942-NEXT: s_mov_b32 s2, 0x5555555641; GFX942-NEXT: v_mul_hi_u32 v2, v0, s242; GFX942-NEXT: v_mov_b32_e32 v3, 043; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v1, s2, v[2:3]44; GFX942-NEXT: v_mov_b32_e32 v2, v545; GFX942-NEXT: v_mov_b32_e32 v5, v346; GFX942-NEXT: s_mov_b32 s3, 0x5555555547; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v0, s3, v[4:5]48; GFX942-NEXT: v_mov_b32_e32 v4, v549; GFX942-NEXT: v_mov_b32_e32 v5, v350; GFX942-NEXT: v_lshl_add_u64 v[4:5], v[2:3], 0, v[4:5]51; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v1, s3, v[4:5]52; GFX942-NEXT: v_ashrrev_i32_e32 v2, 31, v153; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v2, s2, v[4:5]54; GFX942-NEXT: v_mul_lo_u32 v6, v2, s355; GFX942-NEXT: v_mul_lo_u32 v2, v2, s256; GFX942-NEXT: v_add3_u32 v5, v2, v5, v657; GFX942-NEXT: v_lshrrev_b32_e32 v2, 31, v558; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[4:5], 0, v[2:3]59; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v2, 3, 060; GFX942-NEXT: v_mov_b32_e32 v2, v561; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v3, 3, v[2:3]62; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v463; GFX942-NEXT: s_nop 164; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc65; GFX942-NEXT: s_setpc_b64 s[30:31]66;67; GFX1030-LABEL: srem64_3:68; GFX1030: ; %bb.0: ; %entry69; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)70; GFX1030-NEXT: v_mul_hi_u32 v2, 0x55555556, v071; GFX1030-NEXT: v_mov_b32_e32 v3, 072; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, 0x55555556, v1, v[2:3]73; GFX1030-NEXT: v_mov_b32_e32 v2, v474; GFX1030-NEXT: v_ashrrev_i32_e32 v4, 31, v175; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x55555555, v0, v[2:3]76; GFX1030-NEXT: v_add_co_u32 v2, s4, v5, v377; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s478; GFX1030-NEXT: v_mul_lo_u32 v5, 0x55555555, v479; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x55555555, v1, v[2:3]80; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x55555556, v4, v[2:3]81; GFX1030-NEXT: v_mul_lo_u32 v4, 0x55555556, v482; GFX1030-NEXT: v_add3_u32 v3, v4, v3, v583; GFX1030-NEXT: v_lshrrev_b32_e32 v4, 31, v384; GFX1030-NEXT: v_add_co_u32 v2, vcc_lo, v2, v485; GFX1030-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v3, vcc_lo86; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v2, 3, 087; GFX1030-NEXT: v_mad_u64_u32 v[3:4], null, v4, 3, v[3:4]88; GFX1030-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v289; GFX1030-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v3, vcc_lo90; GFX1030-NEXT: s_setpc_b64 s[30:31]91entry:92 %rem = srem i64 %i, 393 ret i64 %rem94}95 96define noundef i64 @srem64_6(i64 noundef %i) {97; GFX9-LABEL: srem64_6:98; GFX9: ; %bb.0: ; %entry99; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)100; GFX9-NEXT: s_mov_b32 s6, 0x55555556101; GFX9-NEXT: v_mul_hi_u32 v2, v0, s6102; GFX9-NEXT: v_mov_b32_e32 v3, 0103; GFX9-NEXT: s_mov_b32 s7, 0x55555555104; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, s6, v[2:3]105; GFX9-NEXT: v_mov_b32_e32 v2, v4106; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, s7, v[2:3]107; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v1108; GFX9-NEXT: v_mul_lo_u32 v6, v4, s6109; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v5, v3110; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc111; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s7, v[2:3]112; GFX9-NEXT: v_mul_lo_u32 v5, v4, s7113; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, s6, v[2:3]114; GFX9-NEXT: v_add3_u32 v3, v6, v3, v5115; GFX9-NEXT: v_lshrrev_b32_e32 v4, 31, v3116; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4117; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v3, vcc118; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, 3, 0119; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v4, 3, v[3:4]120; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2121; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc122; GFX9-NEXT: s_setpc_b64 s[30:31]123;124; GFX942-LABEL: srem64_6:125; GFX942: ; %bb.0: ; %entry126; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)127; GFX942-NEXT: s_mov_b32 s2, 0x55555556128; GFX942-NEXT: v_mul_hi_u32 v2, v0, s2129; GFX942-NEXT: v_mov_b32_e32 v3, 0130; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v1, s2, v[2:3]131; GFX942-NEXT: v_mov_b32_e32 v2, v5132; GFX942-NEXT: v_mov_b32_e32 v5, v3133; GFX942-NEXT: s_mov_b32 s3, 0x55555555134; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v0, s3, v[4:5]135; GFX942-NEXT: v_mov_b32_e32 v4, v5136; GFX942-NEXT: v_mov_b32_e32 v5, v3137; GFX942-NEXT: v_lshl_add_u64 v[4:5], v[2:3], 0, v[4:5]138; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v1, s3, v[4:5]139; GFX942-NEXT: v_ashrrev_i32_e32 v2, 31, v1140; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v2, s2, v[4:5]141; GFX942-NEXT: v_mul_lo_u32 v6, v2, s3142; GFX942-NEXT: v_mul_lo_u32 v2, v2, s2143; GFX942-NEXT: v_add3_u32 v5, v2, v5, v6144; GFX942-NEXT: v_lshrrev_b32_e32 v2, 31, v5145; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[4:5], 0, v[2:3]146; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v2, 3, 0147; GFX942-NEXT: v_mov_b32_e32 v2, v5148; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v3, 3, v[2:3]149; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v4150; GFX942-NEXT: s_nop 1151; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc152; GFX942-NEXT: s_setpc_b64 s[30:31]153;154; GFX1030-LABEL: srem64_6:155; GFX1030: ; %bb.0: ; %entry156; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)157; GFX1030-NEXT: v_mul_hi_u32 v2, 0x55555556, v0158; GFX1030-NEXT: v_mov_b32_e32 v3, 0159; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, 0x55555556, v1, v[2:3]160; GFX1030-NEXT: v_mov_b32_e32 v2, v4161; GFX1030-NEXT: v_ashrrev_i32_e32 v4, 31, v1162; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x55555555, v0, v[2:3]163; GFX1030-NEXT: v_add_co_u32 v2, s4, v5, v3164; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s4165; GFX1030-NEXT: v_mul_lo_u32 v5, 0x55555555, v4166; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x55555555, v1, v[2:3]167; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x55555556, v4, v[2:3]168; GFX1030-NEXT: v_mul_lo_u32 v4, 0x55555556, v4169; GFX1030-NEXT: v_add3_u32 v3, v4, v3, v5170; GFX1030-NEXT: v_lshrrev_b32_e32 v4, 31, v3171; GFX1030-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4172; GFX1030-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v3, vcc_lo173; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v2, 3, 0174; GFX1030-NEXT: v_mad_u64_u32 v[3:4], null, v4, 3, v[3:4]175; GFX1030-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v2176; GFX1030-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v3, vcc_lo177; GFX1030-NEXT: s_setpc_b64 s[30:31]178entry:179 %rem = srem i64 %i, 3180 ret i64 %rem181}182 183define noundef i64 @urem64_3(i64 noundef %i) {184; GFX9-LABEL: urem64_3:185; GFX9: ; %bb.0: ; %entry186; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)187; GFX9-NEXT: s_mov_b32 s4, 0xaaaaaaab188; GFX9-NEXT: v_mul_hi_u32 v2, v0, s4189; GFX9-NEXT: v_mov_b32_e32 v3, 0190; GFX9-NEXT: s_mov_b32 s6, 0xaaaaaaaa191; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, s4, v[2:3]192; GFX9-NEXT: v_mov_b32_e32 v2, v4193; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, s6, v[2:3]194; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v5, v3195; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc196; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v1, s6, v[2:3]197; GFX9-NEXT: v_alignbit_b32 v2, v4, v3, 1198; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, 3, 0199; GFX9-NEXT: v_lshrrev_b32_e32 v4, 1, v4200; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v4, 3, v[3:4]201; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2202; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc203; GFX9-NEXT: s_setpc_b64 s[30:31]204;205; GFX942-LABEL: urem64_3:206; GFX942: ; %bb.0: ; %entry207; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)208; GFX942-NEXT: s_mov_b32 s0, 0xaaaaaaab209; GFX942-NEXT: v_mul_hi_u32 v2, v0, s0210; GFX942-NEXT: v_mov_b32_e32 v3, 0211; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v1, s0, v[2:3]212; GFX942-NEXT: v_mov_b32_e32 v2, v5213; GFX942-NEXT: v_mov_b32_e32 v5, v3214; GFX942-NEXT: s_mov_b32 s2, 0xaaaaaaaa215; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v0, s2, v[4:5]216; GFX942-NEXT: v_mov_b32_e32 v4, v5217; GFX942-NEXT: v_mov_b32_e32 v5, v3218; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 0, v[4:5]219; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v1, s2, v[2:3]220; GFX942-NEXT: v_alignbit_b32 v2, v3, v2, 1221; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v2, 3, 0222; GFX942-NEXT: v_mov_b32_e32 v2, v5223; GFX942-NEXT: v_lshrrev_b32_e32 v3, 1, v3224; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v3, 3, v[2:3]225; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v4226; GFX942-NEXT: s_nop 1227; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc228; GFX942-NEXT: s_setpc_b64 s[30:31]229;230; GFX1030-LABEL: urem64_3:231; GFX1030: ; %bb.0: ; %entry232; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)233; GFX1030-NEXT: v_mul_hi_u32 v2, 0xaaaaaaab, v0234; GFX1030-NEXT: v_mov_b32_e32 v3, 0235; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, 0xaaaaaaab, v1, v[2:3]236; GFX1030-NEXT: v_mov_b32_e32 v2, v4237; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0xaaaaaaaa, v0, v[2:3]238; GFX1030-NEXT: v_add_co_u32 v2, s4, v5, v3239; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s4240; GFX1030-NEXT: v_mad_u64_u32 v[3:4], null, 0xaaaaaaaa, v1, v[2:3]241; GFX1030-NEXT: v_alignbit_b32 v2, v4, v3, 1242; GFX1030-NEXT: v_lshrrev_b32_e32 v4, 1, v4243; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v2, 3, 0244; GFX1030-NEXT: v_mad_u64_u32 v[3:4], null, v4, 3, v[3:4]245; GFX1030-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v2246; GFX1030-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v3, vcc_lo247; GFX1030-NEXT: s_setpc_b64 s[30:31]248entry:249 %rem = urem i64 %i, 3250 ret i64 %rem251}252 253define noundef i64 @urem64_6(i64 noundef %i) {254; GFX9-LABEL: urem64_6:255; GFX9: ; %bb.0: ; %entry256; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)257; GFX9-NEXT: s_mov_b32 s4, 0xaaaaaaab258; GFX9-NEXT: v_mul_hi_u32 v2, v0, s4259; GFX9-NEXT: v_mov_b32_e32 v3, 0260; GFX9-NEXT: s_mov_b32 s6, 0xaaaaaaaa261; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, s4, v[2:3]262; GFX9-NEXT: v_mov_b32_e32 v2, v4263; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, s6, v[2:3]264; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v5, v3265; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc266; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v1, s6, v[2:3]267; GFX9-NEXT: v_alignbit_b32 v2, v4, v3, 2268; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, 6, 0269; GFX9-NEXT: v_lshrrev_b32_e32 v4, 2, v4270; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v4, 6, v[3:4]271; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2272; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc273; GFX9-NEXT: s_setpc_b64 s[30:31]274;275; GFX942-LABEL: urem64_6:276; GFX942: ; %bb.0: ; %entry277; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)278; GFX942-NEXT: s_mov_b32 s0, 0xaaaaaaab279; GFX942-NEXT: v_mul_hi_u32 v2, v0, s0280; GFX942-NEXT: v_mov_b32_e32 v3, 0281; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v1, s0, v[2:3]282; GFX942-NEXT: v_mov_b32_e32 v2, v5283; GFX942-NEXT: v_mov_b32_e32 v5, v3284; GFX942-NEXT: s_mov_b32 s2, 0xaaaaaaaa285; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v0, s2, v[4:5]286; GFX942-NEXT: v_mov_b32_e32 v4, v5287; GFX942-NEXT: v_mov_b32_e32 v5, v3288; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 0, v[4:5]289; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v1, s2, v[2:3]290; GFX942-NEXT: v_alignbit_b32 v2, v3, v2, 2291; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v2, 6, 0292; GFX942-NEXT: v_mov_b32_e32 v2, v5293; GFX942-NEXT: v_lshrrev_b32_e32 v3, 2, v3294; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v3, 6, v[2:3]295; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v4296; GFX942-NEXT: s_nop 1297; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc298; GFX942-NEXT: s_setpc_b64 s[30:31]299;300; GFX1030-LABEL: urem64_6:301; GFX1030: ; %bb.0: ; %entry302; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)303; GFX1030-NEXT: v_mul_hi_u32 v2, 0xaaaaaaab, v0304; GFX1030-NEXT: v_mov_b32_e32 v3, 0305; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, 0xaaaaaaab, v1, v[2:3]306; GFX1030-NEXT: v_mov_b32_e32 v2, v4307; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0xaaaaaaaa, v0, v[2:3]308; GFX1030-NEXT: v_add_co_u32 v2, s4, v5, v3309; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s4310; GFX1030-NEXT: v_mad_u64_u32 v[3:4], null, 0xaaaaaaaa, v1, v[2:3]311; GFX1030-NEXT: v_alignbit_b32 v2, v4, v3, 2312; GFX1030-NEXT: v_lshrrev_b32_e32 v4, 2, v4313; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v2, 6, 0314; GFX1030-NEXT: v_mad_u64_u32 v[3:4], null, v4, 6, v[3:4]315; GFX1030-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v2316; GFX1030-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v3, vcc_lo317; GFX1030-NEXT: s_setpc_b64 s[30:31]318entry:319 %rem = urem i64 %i, 6320 ret i64 %rem321}322 323define noundef i64 @sdiv64_3(i64 noundef %i) {324; GFX9-LABEL: sdiv64_3:325; GFX9: ; %bb.0: ; %entry326; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)327; GFX9-NEXT: s_mov_b32 s6, 0x55555556328; GFX9-NEXT: v_mul_hi_u32 v2, v0, s6329; GFX9-NEXT: v_mov_b32_e32 v3, 0330; GFX9-NEXT: s_mov_b32 s7, 0x55555555331; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, s6, v[2:3]332; GFX9-NEXT: v_mov_b32_e32 v2, v4333; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, s7, v[2:3]334; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v1335; GFX9-NEXT: v_mul_lo_u32 v4, v0, s7336; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v5, v3337; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc338; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s7, v[2:3]339; GFX9-NEXT: v_mul_lo_u32 v5, v0, s6340; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, s6, v[2:3]341; GFX9-NEXT: v_add3_u32 v1, v5, v1, v4342; GFX9-NEXT: v_lshrrev_b32_e32 v2, 31, v1343; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2344; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc345; GFX9-NEXT: s_setpc_b64 s[30:31]346;347; GFX942-LABEL: sdiv64_3:348; GFX942: ; %bb.0: ; %entry349; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)350; GFX942-NEXT: s_mov_b32 s2, 0x55555556351; GFX942-NEXT: v_mul_hi_u32 v2, v0, s2352; GFX942-NEXT: v_mov_b32_e32 v3, 0353; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v1, s2, v[2:3]354; GFX942-NEXT: v_mov_b32_e32 v2, v5355; GFX942-NEXT: v_mov_b32_e32 v5, v3356; GFX942-NEXT: s_mov_b32 s3, 0x55555555357; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v0, s3, v[4:5]358; GFX942-NEXT: v_mov_b32_e32 v4, v5359; GFX942-NEXT: v_mov_b32_e32 v5, v3360; GFX942-NEXT: v_lshl_add_u64 v[4:5], v[2:3], 0, v[4:5]361; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v1, s3, v[4:5]362; GFX942-NEXT: v_ashrrev_i32_e32 v2, 31, v1363; GFX942-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, s2, v[4:5]364; GFX942-NEXT: v_mul_lo_u32 v4, v2, s3365; GFX942-NEXT: v_mul_lo_u32 v2, v2, s2366; GFX942-NEXT: v_add3_u32 v1, v2, v1, v4367; GFX942-NEXT: v_lshrrev_b32_e32 v2, 31, v1368; GFX942-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3]369; GFX942-NEXT: s_setpc_b64 s[30:31]370;371; GFX1030-LABEL: sdiv64_3:372; GFX1030: ; %bb.0: ; %entry373; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)374; GFX1030-NEXT: v_mul_hi_u32 v2, 0x55555556, v0375; GFX1030-NEXT: v_mov_b32_e32 v3, 0376; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, 0x55555556, v1, v[2:3]377; GFX1030-NEXT: v_mov_b32_e32 v2, v4378; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x55555555, v0, v[2:3]379; GFX1030-NEXT: v_ashrrev_i32_e32 v0, 31, v1380; GFX1030-NEXT: v_mul_lo_u32 v4, 0x55555555, v0381; GFX1030-NEXT: v_add_co_u32 v2, s4, v5, v3382; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s4383; GFX1030-NEXT: v_mul_lo_u32 v5, 0x55555556, v0384; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x55555555, v1, v[2:3]385; GFX1030-NEXT: v_mad_u64_u32 v[0:1], null, 0x55555556, v0, v[2:3]386; GFX1030-NEXT: v_add3_u32 v1, v5, v1, v4387; GFX1030-NEXT: v_lshrrev_b32_e32 v2, 31, v1388; GFX1030-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2389; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo390; GFX1030-NEXT: s_setpc_b64 s[30:31]391entry:392 %div = sdiv i64 %i, 3393 ret i64 %div394}395 396define noundef i64 @sdiv64_6(i64 noundef %i) {397; GFX9-LABEL: sdiv64_6:398; GFX9: ; %bb.0: ; %entry399; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)400; GFX9-NEXT: s_mov_b32 s6, 0x55555556401; GFX9-NEXT: v_mul_hi_u32 v2, v0, s6402; GFX9-NEXT: v_mov_b32_e32 v3, 0403; GFX9-NEXT: s_mov_b32 s7, 0x55555555404; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, s6, v[2:3]405; GFX9-NEXT: v_mov_b32_e32 v2, v4406; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, s7, v[2:3]407; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v1408; GFX9-NEXT: v_mul_lo_u32 v4, v0, s7409; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v5, v3410; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc411; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s7, v[2:3]412; GFX9-NEXT: v_mul_lo_u32 v5, v0, s6413; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, s6, v[2:3]414; GFX9-NEXT: v_add3_u32 v1, v5, v1, v4415; GFX9-NEXT: v_lshrrev_b32_e32 v2, 31, v1416; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2417; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc418; GFX9-NEXT: s_setpc_b64 s[30:31]419;420; GFX942-LABEL: sdiv64_6:421; GFX942: ; %bb.0: ; %entry422; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)423; GFX942-NEXT: s_mov_b32 s2, 0x55555556424; GFX942-NEXT: v_mul_hi_u32 v2, v0, s2425; GFX942-NEXT: v_mov_b32_e32 v3, 0426; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v1, s2, v[2:3]427; GFX942-NEXT: v_mov_b32_e32 v2, v5428; GFX942-NEXT: v_mov_b32_e32 v5, v3429; GFX942-NEXT: s_mov_b32 s3, 0x55555555430; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v0, s3, v[4:5]431; GFX942-NEXT: v_mov_b32_e32 v4, v5432; GFX942-NEXT: v_mov_b32_e32 v5, v3433; GFX942-NEXT: v_lshl_add_u64 v[4:5], v[2:3], 0, v[4:5]434; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v1, s3, v[4:5]435; GFX942-NEXT: v_ashrrev_i32_e32 v2, 31, v1436; GFX942-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, s2, v[4:5]437; GFX942-NEXT: v_mul_lo_u32 v4, v2, s3438; GFX942-NEXT: v_mul_lo_u32 v2, v2, s2439; GFX942-NEXT: v_add3_u32 v1, v2, v1, v4440; GFX942-NEXT: v_lshrrev_b32_e32 v2, 31, v1441; GFX942-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3]442; GFX942-NEXT: s_setpc_b64 s[30:31]443;444; GFX1030-LABEL: sdiv64_6:445; GFX1030: ; %bb.0: ; %entry446; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)447; GFX1030-NEXT: v_mul_hi_u32 v2, 0x55555556, v0448; GFX1030-NEXT: v_mov_b32_e32 v3, 0449; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, 0x55555556, v1, v[2:3]450; GFX1030-NEXT: v_mov_b32_e32 v2, v4451; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x55555555, v0, v[2:3]452; GFX1030-NEXT: v_ashrrev_i32_e32 v0, 31, v1453; GFX1030-NEXT: v_mul_lo_u32 v4, 0x55555555, v0454; GFX1030-NEXT: v_add_co_u32 v2, s4, v5, v3455; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s4456; GFX1030-NEXT: v_mul_lo_u32 v5, 0x55555556, v0457; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x55555555, v1, v[2:3]458; GFX1030-NEXT: v_mad_u64_u32 v[0:1], null, 0x55555556, v0, v[2:3]459; GFX1030-NEXT: v_add3_u32 v1, v5, v1, v4460; GFX1030-NEXT: v_lshrrev_b32_e32 v2, 31, v1461; GFX1030-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2462; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo463; GFX1030-NEXT: s_setpc_b64 s[30:31]464entry:465 %div = sdiv i64 %i, 3466 ret i64 %div467}468 469define noundef i64 @udiv64_3(i64 noundef %i) {470; GFX9-LABEL: udiv64_3:471; GFX9: ; %bb.0: ; %entry472; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)473; GFX9-NEXT: s_mov_b32 s4, 0xaaaaaaab474; GFX9-NEXT: v_mul_hi_u32 v2, v0, s4475; GFX9-NEXT: v_mov_b32_e32 v3, 0476; GFX9-NEXT: s_mov_b32 s6, 0xaaaaaaaa477; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, s4, v[2:3]478; GFX9-NEXT: v_mov_b32_e32 v2, v4479; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, s6, v[2:3]480; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v5, v3481; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc482; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v1, s6, v[2:3]483; GFX9-NEXT: v_alignbit_b32 v0, v1, v0, 1484; GFX9-NEXT: v_lshrrev_b32_e32 v1, 1, v1485; GFX9-NEXT: s_setpc_b64 s[30:31]486;487; GFX942-LABEL: udiv64_3:488; GFX942: ; %bb.0: ; %entry489; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)490; GFX942-NEXT: s_mov_b32 s0, 0xaaaaaaab491; GFX942-NEXT: v_mul_hi_u32 v2, v0, s0492; GFX942-NEXT: v_mov_b32_e32 v3, 0493; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v1, s0, v[2:3]494; GFX942-NEXT: v_mov_b32_e32 v2, v5495; GFX942-NEXT: v_mov_b32_e32 v5, v3496; GFX942-NEXT: s_mov_b32 s2, 0xaaaaaaaa497; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v0, s2, v[4:5]498; GFX942-NEXT: v_mov_b32_e32 v4, v5499; GFX942-NEXT: v_mov_b32_e32 v5, v3500; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 0, v[4:5]501; GFX942-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v1, s2, v[2:3]502; GFX942-NEXT: v_alignbit_b32 v0, v1, v0, 1503; GFX942-NEXT: v_lshrrev_b32_e32 v1, 1, v1504; GFX942-NEXT: s_setpc_b64 s[30:31]505;506; GFX1030-LABEL: udiv64_3:507; GFX1030: ; %bb.0: ; %entry508; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)509; GFX1030-NEXT: v_mul_hi_u32 v2, 0xaaaaaaab, v0510; GFX1030-NEXT: v_mov_b32_e32 v3, 0511; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, 0xaaaaaaab, v1, v[2:3]512; GFX1030-NEXT: v_mov_b32_e32 v2, v4513; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0xaaaaaaaa, v0, v[2:3]514; GFX1030-NEXT: v_add_co_u32 v2, s4, v5, v3515; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s4516; GFX1030-NEXT: v_mad_u64_u32 v[0:1], null, 0xaaaaaaaa, v1, v[2:3]517; GFX1030-NEXT: v_alignbit_b32 v0, v1, v0, 1518; GFX1030-NEXT: v_lshrrev_b32_e32 v1, 1, v1519; GFX1030-NEXT: s_setpc_b64 s[30:31]520entry:521 %div = udiv i64 %i, 3522 ret i64 %div523}524 525define noundef i64 @udiv64_6(i64 noundef %i) {526; GFX9-LABEL: udiv64_6:527; GFX9: ; %bb.0: ; %entry528; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)529; GFX9-NEXT: s_mov_b32 s4, 0xaaaaaaab530; GFX9-NEXT: v_mul_hi_u32 v2, v0, s4531; GFX9-NEXT: v_mov_b32_e32 v3, 0532; GFX9-NEXT: s_mov_b32 s6, 0xaaaaaaaa533; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, s4, v[2:3]534; GFX9-NEXT: v_mov_b32_e32 v2, v4535; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, s6, v[2:3]536; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v5, v3537; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc538; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v1, s6, v[2:3]539; GFX9-NEXT: v_alignbit_b32 v0, v1, v0, 2540; GFX9-NEXT: v_lshrrev_b32_e32 v1, 2, v1541; GFX9-NEXT: s_setpc_b64 s[30:31]542;543; GFX942-LABEL: udiv64_6:544; GFX942: ; %bb.0: ; %entry545; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)546; GFX942-NEXT: s_mov_b32 s0, 0xaaaaaaab547; GFX942-NEXT: v_mul_hi_u32 v2, v0, s0548; GFX942-NEXT: v_mov_b32_e32 v3, 0549; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v1, s0, v[2:3]550; GFX942-NEXT: v_mov_b32_e32 v2, v5551; GFX942-NEXT: v_mov_b32_e32 v5, v3552; GFX942-NEXT: s_mov_b32 s2, 0xaaaaaaaa553; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v0, s2, v[4:5]554; GFX942-NEXT: v_mov_b32_e32 v4, v5555; GFX942-NEXT: v_mov_b32_e32 v5, v3556; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 0, v[4:5]557; GFX942-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v1, s2, v[2:3]558; GFX942-NEXT: v_alignbit_b32 v0, v1, v0, 2559; GFX942-NEXT: v_lshrrev_b32_e32 v1, 2, v1560; GFX942-NEXT: s_setpc_b64 s[30:31]561;562; GFX1030-LABEL: udiv64_6:563; GFX1030: ; %bb.0: ; %entry564; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)565; GFX1030-NEXT: v_mul_hi_u32 v2, 0xaaaaaaab, v0566; GFX1030-NEXT: v_mov_b32_e32 v3, 0567; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, 0xaaaaaaab, v1, v[2:3]568; GFX1030-NEXT: v_mov_b32_e32 v2, v4569; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0xaaaaaaaa, v0, v[2:3]570; GFX1030-NEXT: v_add_co_u32 v2, s4, v5, v3571; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s4572; GFX1030-NEXT: v_mad_u64_u32 v[0:1], null, 0xaaaaaaaa, v1, v[2:3]573; GFX1030-NEXT: v_alignbit_b32 v0, v1, v0, 2574; GFX1030-NEXT: v_lshrrev_b32_e32 v1, 2, v1575; GFX1030-NEXT: s_setpc_b64 s[30:31]576entry:577 %div = udiv i64 %i, 6578 ret i64 %div579}580 581define noundef i64 @srem64_2(i64 noundef %i) {582; GFX9-LABEL: srem64_2:583; GFX9: ; %bb.0: ; %entry584; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)585; GFX9-NEXT: v_lshrrev_b32_e32 v2, 31, v1586; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v0, v2587; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc588; GFX9-NEXT: v_and_b32_e32 v2, -2, v2589; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2590; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc591; GFX9-NEXT: s_setpc_b64 s[30:31]592;593; GFX942-LABEL: srem64_2:594; GFX942: ; %bb.0: ; %entry595; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)596; GFX942-NEXT: v_lshrrev_b32_e32 v2, 31, v1597; GFX942-NEXT: v_mov_b32_e32 v3, 0598; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[0:1], 0, v[2:3]599; GFX942-NEXT: v_and_b32_e32 v2, -2, v2600; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2601; GFX942-NEXT: s_nop 1602; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc603; GFX942-NEXT: s_setpc_b64 s[30:31]604;605; GFX1030-LABEL: srem64_2:606; GFX1030: ; %bb.0: ; %entry607; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)608; GFX1030-NEXT: v_lshrrev_b32_e32 v2, 31, v1609; GFX1030-NEXT: v_add_co_u32 v2, vcc_lo, v0, v2610; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v1, vcc_lo611; GFX1030-NEXT: v_and_b32_e32 v2, -2, v2612; GFX1030-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v2613; GFX1030-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v3, vcc_lo614; GFX1030-NEXT: s_setpc_b64 s[30:31]615entry:616 %rem = srem i64 %i, 2617 ret i64 %rem618}619 620define noundef i64 @sdiv64_2(i64 noundef %i) {621; GFX9-LABEL: sdiv64_2:622; GFX9: ; %bb.0: ; %entry623; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)624; GFX9-NEXT: v_lshrrev_b32_e32 v2, 31, v1625; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2626; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc627; GFX9-NEXT: v_ashrrev_i64 v[0:1], 1, v[0:1]628; GFX9-NEXT: s_setpc_b64 s[30:31]629;630; GFX942-LABEL: sdiv64_2:631; GFX942: ; %bb.0: ; %entry632; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)633; GFX942-NEXT: v_lshrrev_b32_e32 v2, 31, v1634; GFX942-NEXT: v_mov_b32_e32 v3, 0635; GFX942-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3]636; GFX942-NEXT: v_ashrrev_i64 v[0:1], 1, v[0:1]637; GFX942-NEXT: s_setpc_b64 s[30:31]638;639; GFX1030-LABEL: sdiv64_2:640; GFX1030: ; %bb.0: ; %entry641; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)642; GFX1030-NEXT: v_lshrrev_b32_e32 v2, 31, v1643; GFX1030-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2644; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo645; GFX1030-NEXT: v_ashrrev_i64 v[0:1], 1, v[0:1]646; GFX1030-NEXT: s_setpc_b64 s[30:31]647entry:648 %div = sdiv i64 %i, 2649 ret i64 %div650}651 652define noundef i64 @urem64_2(i64 noundef %i) {653; GFX9-LABEL: urem64_2:654; GFX9: ; %bb.0: ; %entry655; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)656; GFX9-NEXT: v_and_b32_e32 v0, 1, v0657; GFX9-NEXT: v_mov_b32_e32 v1, 0658; GFX9-NEXT: s_setpc_b64 s[30:31]659;660; GFX942-LABEL: urem64_2:661; GFX942: ; %bb.0: ; %entry662; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)663; GFX942-NEXT: v_and_b32_e32 v0, 1, v0664; GFX942-NEXT: v_mov_b32_e32 v1, 0665; GFX942-NEXT: s_setpc_b64 s[30:31]666;667; GFX1030-LABEL: urem64_2:668; GFX1030: ; %bb.0: ; %entry669; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)670; GFX1030-NEXT: v_and_b32_e32 v0, 1, v0671; GFX1030-NEXT: v_mov_b32_e32 v1, 0672; GFX1030-NEXT: s_setpc_b64 s[30:31]673entry:674 %rem = urem i64 %i, 2675 ret i64 %rem676}677 678define noundef i64 @udiv64_2(i64 noundef %i) {679; GFX9-LABEL: udiv64_2:680; GFX9: ; %bb.0: ; %entry681; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)682; GFX9-NEXT: v_alignbit_b32 v0, v1, v0, 1683; GFX9-NEXT: v_lshrrev_b32_e32 v1, 1, v1684; GFX9-NEXT: s_setpc_b64 s[30:31]685;686; GFX942-LABEL: udiv64_2:687; GFX942: ; %bb.0: ; %entry688; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)689; GFX942-NEXT: v_alignbit_b32 v0, v1, v0, 1690; GFX942-NEXT: v_lshrrev_b32_e32 v1, 1, v1691; GFX942-NEXT: s_setpc_b64 s[30:31]692;693; GFX1030-LABEL: udiv64_2:694; GFX1030: ; %bb.0: ; %entry695; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)696; GFX1030-NEXT: v_alignbit_b32 v0, v1, v0, 1697; GFX1030-NEXT: v_lshrrev_b32_e32 v1, 1, v1698; GFX1030-NEXT: s_setpc_b64 s[30:31]699entry:700 %div = udiv i64 %i, 2701 ret i64 %div702}703 704define noundef i64 @srem64_64(i64 noundef %i) {705; GFX9-LABEL: srem64_64:706; GFX9: ; %bb.0: ; %entry707; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)708; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v1709; GFX9-NEXT: v_lshrrev_b32_e32 v2, 26, v2710; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v0, v2711; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc712; GFX9-NEXT: v_and_b32_e32 v2, 0xffffffc0, v2713; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2714; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc715; GFX9-NEXT: s_setpc_b64 s[30:31]716;717; GFX942-LABEL: srem64_64:718; GFX942: ; %bb.0: ; %entry719; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)720; GFX942-NEXT: v_ashrrev_i32_e32 v2, 31, v1721; GFX942-NEXT: v_lshrrev_b32_e32 v2, 26, v2722; GFX942-NEXT: v_mov_b32_e32 v3, 0723; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[0:1], 0, v[2:3]724; GFX942-NEXT: v_and_b32_e32 v2, 0xffffffc0, v2725; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2726; GFX942-NEXT: s_nop 1727; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc728; GFX942-NEXT: s_setpc_b64 s[30:31]729;730; GFX1030-LABEL: srem64_64:731; GFX1030: ; %bb.0: ; %entry732; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)733; GFX1030-NEXT: v_ashrrev_i32_e32 v2, 31, v1734; GFX1030-NEXT: v_lshrrev_b32_e32 v2, 26, v2735; GFX1030-NEXT: v_add_co_u32 v2, vcc_lo, v0, v2736; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v1, vcc_lo737; GFX1030-NEXT: v_and_b32_e32 v2, 0xffffffc0, v2738; GFX1030-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v2739; GFX1030-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v3, vcc_lo740; GFX1030-NEXT: s_setpc_b64 s[30:31]741entry:742 %rem = srem i64 %i, 64743 ret i64 %rem744}745 746define noundef i64 @sdiv64_64(i64 noundef %i) {747; GFX9-LABEL: sdiv64_64:748; GFX9: ; %bb.0: ; %entry749; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)750; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v1751; GFX9-NEXT: v_lshrrev_b32_e32 v2, 26, v2752; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2753; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc754; GFX9-NEXT: v_ashrrev_i64 v[0:1], 6, v[0:1]755; GFX9-NEXT: s_setpc_b64 s[30:31]756;757; GFX942-LABEL: sdiv64_64:758; GFX942: ; %bb.0: ; %entry759; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)760; GFX942-NEXT: v_ashrrev_i32_e32 v2, 31, v1761; GFX942-NEXT: v_lshrrev_b32_e32 v2, 26, v2762; GFX942-NEXT: v_mov_b32_e32 v3, 0763; GFX942-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3]764; GFX942-NEXT: v_ashrrev_i64 v[0:1], 6, v[0:1]765; GFX942-NEXT: s_setpc_b64 s[30:31]766;767; GFX1030-LABEL: sdiv64_64:768; GFX1030: ; %bb.0: ; %entry769; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)770; GFX1030-NEXT: v_ashrrev_i32_e32 v2, 31, v1771; GFX1030-NEXT: v_lshrrev_b32_e32 v2, 26, v2772; GFX1030-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2773; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo774; GFX1030-NEXT: v_ashrrev_i64 v[0:1], 6, v[0:1]775; GFX1030-NEXT: s_setpc_b64 s[30:31]776entry:777 %div = sdiv i64 %i, 64778 ret i64 %div779}780 781define noundef i64 @urem64_64(i64 noundef %i) {782; GFX9-LABEL: urem64_64:783; GFX9: ; %bb.0: ; %entry784; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)785; GFX9-NEXT: v_and_b32_e32 v0, 63, v0786; GFX9-NEXT: v_mov_b32_e32 v1, 0787; GFX9-NEXT: s_setpc_b64 s[30:31]788;789; GFX942-LABEL: urem64_64:790; GFX942: ; %bb.0: ; %entry791; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)792; GFX942-NEXT: v_and_b32_e32 v0, 63, v0793; GFX942-NEXT: v_mov_b32_e32 v1, 0794; GFX942-NEXT: s_setpc_b64 s[30:31]795;796; GFX1030-LABEL: urem64_64:797; GFX1030: ; %bb.0: ; %entry798; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)799; GFX1030-NEXT: v_and_b32_e32 v0, 63, v0800; GFX1030-NEXT: v_mov_b32_e32 v1, 0801; GFX1030-NEXT: s_setpc_b64 s[30:31]802entry:803 %rem = urem i64 %i, 64804 ret i64 %rem805}806 807define noundef i64 @udiv64_64(i64 noundef %i) {808; GFX9-LABEL: udiv64_64:809; GFX9: ; %bb.0: ; %entry810; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)811; GFX9-NEXT: v_alignbit_b32 v0, v1, v0, 6812; GFX9-NEXT: v_lshrrev_b32_e32 v1, 6, v1813; GFX9-NEXT: s_setpc_b64 s[30:31]814;815; GFX942-LABEL: udiv64_64:816; GFX942: ; %bb.0: ; %entry817; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)818; GFX942-NEXT: v_alignbit_b32 v0, v1, v0, 6819; GFX942-NEXT: v_lshrrev_b32_e32 v1, 6, v1820; GFX942-NEXT: s_setpc_b64 s[30:31]821;822; GFX1030-LABEL: udiv64_64:823; GFX1030: ; %bb.0: ; %entry824; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)825; GFX1030-NEXT: v_alignbit_b32 v0, v1, v0, 6826; GFX1030-NEXT: v_lshrrev_b32_e32 v1, 6, v1827; GFX1030-NEXT: s_setpc_b64 s[30:31]828entry:829 %div = udiv i64 %i, 64830 ret i64 %div831}832 833define noundef i64 @srem64_i32min(i64 noundef %i) {834; GFX9-LABEL: srem64_i32min:835; GFX9: ; %bb.0: ; %entry836; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)837; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v1838; GFX9-NEXT: v_lshrrev_b32_e32 v2, 1, v2839; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v0, v2840; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc841; GFX9-NEXT: v_and_b32_e32 v2, 0x80000000, v2842; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2843; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc844; GFX9-NEXT: s_setpc_b64 s[30:31]845;846; GFX942-LABEL: srem64_i32min:847; GFX942: ; %bb.0: ; %entry848; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)849; GFX942-NEXT: v_ashrrev_i32_e32 v2, 31, v1850; GFX942-NEXT: v_lshrrev_b32_e32 v2, 1, v2851; GFX942-NEXT: v_mov_b32_e32 v3, 0852; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[0:1], 0, v[2:3]853; GFX942-NEXT: v_and_b32_e32 v2, 0x80000000, v2854; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2855; GFX942-NEXT: s_nop 1856; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc857; GFX942-NEXT: s_setpc_b64 s[30:31]858;859; GFX1030-LABEL: srem64_i32min:860; GFX1030: ; %bb.0: ; %entry861; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)862; GFX1030-NEXT: v_ashrrev_i32_e32 v2, 31, v1863; GFX1030-NEXT: v_lshrrev_b32_e32 v2, 1, v2864; GFX1030-NEXT: v_add_co_u32 v2, vcc_lo, v0, v2865; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v1, vcc_lo866; GFX1030-NEXT: v_and_b32_e32 v2, 0x80000000, v2867; GFX1030-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v2868; GFX1030-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v3, vcc_lo869; GFX1030-NEXT: s_setpc_b64 s[30:31]870entry:871 %rem = srem i64 %i, -2147483648872 ret i64 %rem873}874 875define noundef i64 @sdiv64_i32min(i64 noundef %i) {876; GFX9-LABEL: sdiv64_i32min:877; GFX9: ; %bb.0: ; %entry878; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)879; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v1880; GFX9-NEXT: v_lshrrev_b32_e32 v2, 1, v2881; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2882; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc883; GFX9-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1]884; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, 0, v0885; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, 0, v1, vcc886; GFX9-NEXT: s_setpc_b64 s[30:31]887;888; GFX942-LABEL: sdiv64_i32min:889; GFX942: ; %bb.0: ; %entry890; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)891; GFX942-NEXT: v_ashrrev_i32_e32 v2, 31, v1892; GFX942-NEXT: v_lshrrev_b32_e32 v2, 1, v2893; GFX942-NEXT: v_mov_b32_e32 v3, 0894; GFX942-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3]895; GFX942-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1]896; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, 0, v0897; GFX942-NEXT: s_nop 1898; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, 0, v1, vcc899; GFX942-NEXT: s_setpc_b64 s[30:31]900;901; GFX1030-LABEL: sdiv64_i32min:902; GFX1030: ; %bb.0: ; %entry903; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)904; GFX1030-NEXT: v_ashrrev_i32_e32 v2, 31, v1905; GFX1030-NEXT: v_lshrrev_b32_e32 v2, 1, v2906; GFX1030-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2907; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo908; GFX1030-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1]909; GFX1030-NEXT: v_sub_co_u32 v0, vcc_lo, 0, v0910; GFX1030-NEXT: v_sub_co_ci_u32_e64 v1, null, 0, v1, vcc_lo911; GFX1030-NEXT: s_setpc_b64 s[30:31]912entry:913 %div = sdiv i64 %i, -2147483648914 ret i64 %div915}916 917define noundef i64 @urem64_i32min(i64 noundef %i) {918; GFX9-LABEL: urem64_i32min:919; GFX9: ; %bb.0: ; %entry920; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)921; GFX9-NEXT: v_alignbit_b32 v4, v1, v0, 31922; GFX9-NEXT: v_lshrrev_b32_e32 v2, 31, v1923; GFX9-NEXT: v_mov_b32_e32 v3, 0924; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v4, 1, v[2:3]925; GFX9-NEXT: v_add_lshl_u32 v2, v2, v4, 30926; GFX9-NEXT: v_and_b32_e32 v2, 0x80000000, v2927; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2928; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc929; GFX9-NEXT: s_setpc_b64 s[30:31]930;931; GFX942-LABEL: urem64_i32min:932; GFX942: ; %bb.0: ; %entry933; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)934; GFX942-NEXT: v_alignbit_b32 v4, v1, v0, 31935; GFX942-NEXT: v_lshrrev_b32_e32 v2, 31, v1936; GFX942-NEXT: v_mov_b32_e32 v3, 0937; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v4, 1, v[2:3]938; GFX942-NEXT: v_add_lshl_u32 v2, v2, v5, 30939; GFX942-NEXT: v_and_b32_e32 v2, 0x80000000, v2940; GFX942-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3]941; GFX942-NEXT: s_setpc_b64 s[30:31]942;943; GFX1030-LABEL: urem64_i32min:944; GFX1030: ; %bb.0: ; %entry945; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)946; GFX1030-NEXT: v_mov_b32_e32 v3, 0947; GFX1030-NEXT: v_alignbit_b32 v4, v1, v0, 31948; GFX1030-NEXT: v_lshrrev_b32_e32 v2, 31, v1949; GFX1030-NEXT: v_mad_u64_u32 v[3:4], null, v4, 1, v[2:3]950; GFX1030-NEXT: v_add_lshl_u32 v2, v2, v4, 30951; GFX1030-NEXT: v_and_b32_e32 v2, 0x80000000, v2952; GFX1030-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2953; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo954; GFX1030-NEXT: s_setpc_b64 s[30:31]955entry:956 %rem = urem i64 %i, -2147483648957 ret i64 %rem958}959 960define noundef i64 @udiv64_i32min(i64 noundef %i) {961; GFX9-LABEL: udiv64_i32min:962; GFX9: ; %bb.0: ; %entry963; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)964; GFX9-NEXT: v_alignbit_b32 v2, v1, v0, 31965; GFX9-NEXT: v_lshrrev_b32_e32 v0, 31, v1966; GFX9-NEXT: v_mov_b32_e32 v1, 0967; GFX9-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v2, 1, v[0:1]968; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2969; GFX9-NEXT: v_addc_co_u32_e64 v1, s[4:5], 0, 0, vcc970; GFX9-NEXT: v_alignbit_b32 v0, v1, v0, 1971; GFX9-NEXT: v_mov_b32_e32 v1, 0972; GFX9-NEXT: s_setpc_b64 s[30:31]973;974; GFX942-LABEL: udiv64_i32min:975; GFX942: ; %bb.0: ; %entry976; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)977; GFX942-NEXT: v_alignbit_b32 v2, v1, v0, 31978; GFX942-NEXT: v_lshrrev_b32_e32 v0, 31, v1979; GFX942-NEXT: v_mov_b32_e32 v1, 0980; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v2, 1, v[0:1]981; GFX942-NEXT: v_mov_b32_e32 v2, v3982; GFX942-NEXT: v_mov_b32_e32 v3, v1983; GFX942-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3]984; GFX942-NEXT: v_alignbit_b32 v0, v1, v0, 1985; GFX942-NEXT: v_mov_b32_e32 v1, 0986; GFX942-NEXT: s_setpc_b64 s[30:31]987;988; GFX1030-LABEL: udiv64_i32min:989; GFX1030: ; %bb.0: ; %entry990; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)991; GFX1030-NEXT: v_mov_b32_e32 v2, 0992; GFX1030-NEXT: v_alignbit_b32 v0, v1, v0, 31993; GFX1030-NEXT: v_lshrrev_b32_e32 v1, 31, v1994; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v0, 1, v[1:2]995; GFX1030-NEXT: v_add_co_u32 v0, s4, v1, v3996; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, 0, 0, s4997; GFX1030-NEXT: v_alignbit_b32 v0, v1, v0, 1998; GFX1030-NEXT: v_mov_b32_e32 v1, 0999; GFX1030-NEXT: s_setpc_b64 s[30:31]1000entry:1001 %div = udiv i64 %i, -21474836481002 ret i64 %div1003}1004 1005define noundef i64 @srem64_i32max(i64 noundef %i) {1006; GFX9-LABEL: srem64_i32max:1007; GFX9: ; %bb.0: ; %entry1008; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1009; GFX9-NEXT: v_mul_hi_u32 v2, v0, 31010; GFX9-NEXT: v_ashrrev_i32_e32 v8, 31, v11011; GFX9-NEXT: v_mov_b32_e32 v3, 01012; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v8, 3, 01013; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v1, 3, v[2:3]1014; GFX9-NEXT: v_lshl_add_u32 v2, v8, 31, v81015; GFX9-NEXT: v_add3_u32 v5, v5, v2, v41016; GFX9-NEXT: v_mov_b32_e32 v2, v61017; GFX9-NEXT: s_mov_b32 s6, 0x800000011018; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, s6, v[2:3]1019; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, -1, v[4:5]1020; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v7, v31021; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc1022; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s6, v[2:3]1023; GFX9-NEXT: v_sub_u32_e32 v5, v5, v11024; GFX9-NEXT: v_sub_u32_e32 v5, v5, v01025; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v41026; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v5, vcc1027; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, 1, v[2:3]1028; GFX9-NEXT: s_brev_b32 s6, -21029; GFX9-NEXT: v_add_u32_e32 v3, v1, v31030; GFX9-NEXT: v_ashrrev_i64 v[4:5], 30, v[2:3]1031; GFX9-NEXT: v_lshrrev_b32_e32 v2, 31, v31032; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v21033; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, s6, 01034; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc1035; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v4, s6, v[3:4]1036; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v21037; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc1038; GFX9-NEXT: s_setpc_b64 s[30:31]1039;1040; GFX942-LABEL: srem64_i32max:1041; GFX942: ; %bb.0: ; %entry1042; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1043; GFX942-NEXT: v_ashrrev_i32_e32 v2, 31, v11044; GFX942-NEXT: v_lshl_add_u32 v4, v2, 31, v21045; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v2, 3, 01046; GFX942-NEXT: v_add3_u32 v3, v3, v4, v21047; GFX942-NEXT: v_mul_hi_u32 v4, v0, 31048; GFX942-NEXT: v_mov_b32_e32 v5, 01049; GFX942-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v1, 3, v[4:5]1050; GFX942-NEXT: v_mov_b32_e32 v4, v71051; GFX942-NEXT: v_mov_b32_e32 v7, v51052; GFX942-NEXT: s_mov_b32 s2, 0x800000011053; GFX942-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v0, s2, v[6:7]1054; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v0, -1, v[2:3]1055; GFX942-NEXT: v_mov_b32_e32 v6, v71056; GFX942-NEXT: v_mov_b32_e32 v7, v51057; GFX942-NEXT: v_sub_u32_e32 v3, v3, v11058; GFX942-NEXT: v_lshl_add_u64 v[6:7], v[4:5], 0, v[6:7]1059; GFX942-NEXT: v_sub_u32_e32 v3, v3, v01060; GFX942-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v1, s2, v[6:7]1061; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[6:7], 0, v[2:3]1062; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v0, 1, v[2:3]1063; GFX942-NEXT: v_add_u32_e32 v3, v1, v31064; GFX942-NEXT: v_ashrrev_i64 v[6:7], 30, v[2:3]1065; GFX942-NEXT: v_lshrrev_b32_e32 v4, 31, v31066; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[6:7], 0, v[4:5]1067; GFX942-NEXT: s_brev_b32 s2, -21068; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v2, s2, 01069; GFX942-NEXT: v_mov_b32_e32 v2, v51070; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v3, s2, v[2:3]1071; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v41072; GFX942-NEXT: s_nop 11073; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc1074; GFX942-NEXT: s_setpc_b64 s[30:31]1075;1076; GFX1030-LABEL: srem64_i32max:1077; GFX1030: ; %bb.0: ; %entry1078; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1079; GFX1030-NEXT: v_mul_hi_u32 v2, v0, 31080; GFX1030-NEXT: v_mov_b32_e32 v3, 01081; GFX1030-NEXT: v_ashrrev_i32_e32 v8, 31, v11082; GFX1030-NEXT: v_mad_u64_u32 v[6:7], null, v8, 3, 01083; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, v1, 3, v[2:3]1084; GFX1030-NEXT: v_lshl_add_u32 v8, v8, 31, v81085; GFX1030-NEXT: v_add3_u32 v7, v7, v8, v61086; GFX1030-NEXT: v_mov_b32_e32 v2, v41087; GFX1030-NEXT: v_mad_u64_u32 v[6:7], null, v0, -1, v[6:7]1088; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x80000001, v0, v[2:3]1089; GFX1030-NEXT: v_sub_nc_u32_e32 v4, v7, v11090; GFX1030-NEXT: v_add_co_u32 v2, s4, v5, v31091; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s41092; GFX1030-NEXT: v_sub_nc_u32_e32 v4, v4, v01093; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x80000001, v1, v[2:3]1094; GFX1030-NEXT: v_add_co_u32 v2, vcc_lo, v2, v61095; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v4, vcc_lo1096; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v0, 1, v[2:3]1097; GFX1030-NEXT: v_add_nc_u32_e32 v3, v1, v31098; GFX1030-NEXT: v_ashrrev_i64 v[4:5], 30, v[2:3]1099; GFX1030-NEXT: v_lshrrev_b32_e32 v2, 31, v31100; GFX1030-NEXT: v_add_co_u32 v2, vcc_lo, v4, v21101; GFX1030-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v5, vcc_lo1102; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x7fffffff, v2, 01103; GFX1030-NEXT: v_mad_u64_u32 v[3:4], null, 0x7fffffff, v4, v[3:4]1104; GFX1030-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v21105; GFX1030-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v3, vcc_lo1106; GFX1030-NEXT: s_setpc_b64 s[30:31]1107entry:1108 %rem = srem i64 %i, 21474836471109 ret i64 %rem1110}1111 1112define noundef i64 @sdiv64_i32max(i64 noundef %i) {1113; GFX9-LABEL: sdiv64_i32max:1114; GFX9: ; %bb.0: ; %entry1115; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1116; GFX9-NEXT: v_mul_hi_u32 v2, v0, 31117; GFX9-NEXT: v_ashrrev_i32_e32 v8, 31, v11118; GFX9-NEXT: v_mov_b32_e32 v3, 01119; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v8, 3, 01120; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v1, 3, v[2:3]1121; GFX9-NEXT: v_lshl_add_u32 v2, v8, 31, v81122; GFX9-NEXT: v_add3_u32 v5, v5, v2, v41123; GFX9-NEXT: v_mov_b32_e32 v2, v61124; GFX9-NEXT: s_mov_b32 s6, 0x800000011125; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, s6, v[2:3]1126; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, -1, v[4:5]1127; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v7, v31128; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc1129; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s6, v[2:3]1130; GFX9-NEXT: v_sub_u32_e32 v5, v5, v11131; GFX9-NEXT: v_sub_u32_e32 v5, v5, v01132; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v41133; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v5, vcc1134; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, 1, v[2:3]1135; GFX9-NEXT: v_add_u32_e32 v3, v1, v31136; GFX9-NEXT: v_ashrrev_i64 v[0:1], 30, v[2:3]1137; GFX9-NEXT: v_lshrrev_b32_e32 v2, 31, v31138; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v21139; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc1140; GFX9-NEXT: s_setpc_b64 s[30:31]1141;1142; GFX942-LABEL: sdiv64_i32max:1143; GFX942: ; %bb.0: ; %entry1144; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1145; GFX942-NEXT: v_ashrrev_i32_e32 v2, 31, v11146; GFX942-NEXT: v_lshl_add_u32 v4, v2, 31, v21147; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v2, 3, 01148; GFX942-NEXT: v_add3_u32 v3, v3, v4, v21149; GFX942-NEXT: v_mul_hi_u32 v4, v0, 31150; GFX942-NEXT: v_mov_b32_e32 v5, 01151; GFX942-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v1, 3, v[4:5]1152; GFX942-NEXT: v_mov_b32_e32 v4, v71153; GFX942-NEXT: v_mov_b32_e32 v7, v51154; GFX942-NEXT: s_mov_b32 s2, 0x800000011155; GFX942-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v0, s2, v[6:7]1156; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v0, -1, v[2:3]1157; GFX942-NEXT: v_mov_b32_e32 v6, v71158; GFX942-NEXT: v_mov_b32_e32 v7, v51159; GFX942-NEXT: v_sub_u32_e32 v3, v3, v11160; GFX942-NEXT: v_lshl_add_u64 v[6:7], v[4:5], 0, v[6:7]1161; GFX942-NEXT: v_sub_u32_e32 v3, v3, v01162; GFX942-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v1, s2, v[6:7]1163; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[6:7], 0, v[2:3]1164; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v0, 1, v[2:3]1165; GFX942-NEXT: v_add_u32_e32 v3, v1, v31166; GFX942-NEXT: v_ashrrev_i64 v[0:1], 30, v[2:3]1167; GFX942-NEXT: v_lshrrev_b32_e32 v4, 31, v31168; GFX942-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[4:5]1169; GFX942-NEXT: s_setpc_b64 s[30:31]1170;1171; GFX1030-LABEL: sdiv64_i32max:1172; GFX1030: ; %bb.0: ; %entry1173; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1174; GFX1030-NEXT: v_mul_hi_u32 v2, v0, 31175; GFX1030-NEXT: v_mov_b32_e32 v3, 01176; GFX1030-NEXT: v_ashrrev_i32_e32 v8, 31, v11177; GFX1030-NEXT: v_mad_u64_u32 v[6:7], null, v8, 3, 01178; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, v1, 3, v[2:3]1179; GFX1030-NEXT: v_lshl_add_u32 v8, v8, 31, v81180; GFX1030-NEXT: v_add3_u32 v7, v7, v8, v61181; GFX1030-NEXT: v_mov_b32_e32 v2, v41182; GFX1030-NEXT: v_mad_u64_u32 v[6:7], null, v0, -1, v[6:7]1183; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x80000001, v0, v[2:3]1184; GFX1030-NEXT: v_sub_nc_u32_e32 v4, v7, v11185; GFX1030-NEXT: v_add_co_u32 v2, s4, v5, v31186; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s41187; GFX1030-NEXT: v_sub_nc_u32_e32 v4, v4, v01188; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x80000001, v1, v[2:3]1189; GFX1030-NEXT: v_add_co_u32 v2, vcc_lo, v2, v61190; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v4, vcc_lo1191; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v0, 1, v[2:3]1192; GFX1030-NEXT: v_add_nc_u32_e32 v3, v1, v31193; GFX1030-NEXT: v_ashrrev_i64 v[0:1], 30, v[2:3]1194; GFX1030-NEXT: v_lshrrev_b32_e32 v2, 31, v31195; GFX1030-NEXT: v_add_co_u32 v0, vcc_lo, v0, v21196; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo1197; GFX1030-NEXT: s_setpc_b64 s[30:31]1198entry:1199 %div = sdiv i64 %i, 21474836471200 ret i64 %div1201}1202 1203define noundef i64 @urem64_i32max(i64 noundef %i) {1204; GFX9-LABEL: urem64_i32max:1205; GFX9: ; %bb.0: ; %entry1206; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1207; GFX9-NEXT: v_mul_hi_u32 v2, v0, 51208; GFX9-NEXT: v_mov_b32_e32 v3, 01209; GFX9-NEXT: s_brev_b32 s6, -21210; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, 5, v[2:3]1211; GFX9-NEXT: v_mov_b32_e32 v2, v41212; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, 2, v[2:3]1213; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v5, v31214; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc1215; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, 2, v[2:3]1216; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v0, v21217; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v3, vcc1218; GFX9-NEXT: v_lshrrev_b64 v[4:5], 1, v[4:5]1219; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v21220; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v5, v3, vcc1221; GFX9-NEXT: v_alignbit_b32 v2, v4, v2, 301222; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, s6, 01223; GFX9-NEXT: v_lshrrev_b32_e32 v4, 30, v41224; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v4, s6, v[3:4]1225; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v21226; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc1227; GFX9-NEXT: s_setpc_b64 s[30:31]1228;1229; GFX942-LABEL: urem64_i32max:1230; GFX942: ; %bb.0: ; %entry1231; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1232; GFX942-NEXT: v_mul_hi_u32 v2, v0, 51233; GFX942-NEXT: v_mov_b32_e32 v3, 01234; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v1, 5, v[2:3]1235; GFX942-NEXT: v_mov_b32_e32 v2, v51236; GFX942-NEXT: v_mov_b32_e32 v5, v31237; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v0, 2, v[4:5]1238; GFX942-NEXT: v_mov_b32_e32 v4, v51239; GFX942-NEXT: v_mov_b32_e32 v5, v31240; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 0, v[4:5]1241; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v1, 2, v[2:3]1242; GFX942-NEXT: v_sub_co_u32_e32 v4, vcc, v0, v21243; GFX942-NEXT: s_brev_b32 s2, -21244; GFX942-NEXT: s_nop 01245; GFX942-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v3, vcc1246; GFX942-NEXT: v_lshrrev_b64 v[4:5], 1, v[4:5]1247; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[4:5], 0, v[2:3]1248; GFX942-NEXT: v_alignbit_b32 v2, v3, v2, 301249; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v2, s2, 01250; GFX942-NEXT: v_mov_b32_e32 v2, v51251; GFX942-NEXT: v_lshrrev_b32_e32 v3, 30, v31252; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v3, s2, v[2:3]1253; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v41254; GFX942-NEXT: s_nop 11255; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc1256; GFX942-NEXT: s_setpc_b64 s[30:31]1257;1258; GFX1030-LABEL: urem64_i32max:1259; GFX1030: ; %bb.0: ; %entry1260; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1261; GFX1030-NEXT: v_mul_hi_u32 v2, v0, 51262; GFX1030-NEXT: v_mov_b32_e32 v3, 01263; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, v1, 5, v[2:3]1264; GFX1030-NEXT: v_mov_b32_e32 v2, v41265; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v0, 2, v[2:3]1266; GFX1030-NEXT: v_add_co_u32 v2, s4, v5, v31267; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s41268; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v1, 2, v[2:3]1269; GFX1030-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v21270; GFX1030-NEXT: v_sub_co_ci_u32_e64 v5, null, v1, v3, vcc_lo1271; GFX1030-NEXT: v_lshrrev_b64 v[4:5], 1, v[4:5]1272; GFX1030-NEXT: v_add_co_u32 v2, vcc_lo, v4, v21273; GFX1030-NEXT: v_add_co_ci_u32_e64 v4, null, v5, v3, vcc_lo1274; GFX1030-NEXT: v_alignbit_b32 v2, v4, v2, 301275; GFX1030-NEXT: v_lshrrev_b32_e32 v4, 30, v41276; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x7fffffff, v2, 01277; GFX1030-NEXT: v_mad_u64_u32 v[3:4], null, 0x7fffffff, v4, v[3:4]1278; GFX1030-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v21279; GFX1030-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v3, vcc_lo1280; GFX1030-NEXT: s_setpc_b64 s[30:31]1281entry:1282 %rem = urem i64 %i, 21474836471283 ret i64 %rem1284}1285 1286define noundef i64 @udiv64_i32max(i64 noundef %i) {1287; GFX9-LABEL: udiv64_i32max:1288; GFX9: ; %bb.0: ; %entry1289; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1290; GFX9-NEXT: v_mul_hi_u32 v2, v0, 51291; GFX9-NEXT: v_mov_b32_e32 v3, 01292; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, 5, v[2:3]1293; GFX9-NEXT: v_mov_b32_e32 v2, v41294; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, 2, v[2:3]1295; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v5, v31296; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc1297; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, 2, v[2:3]1298; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v21299; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc1300; GFX9-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]1301; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v21302; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc1303; GFX9-NEXT: v_alignbit_b32 v0, v1, v0, 301304; GFX9-NEXT: v_lshrrev_b32_e32 v1, 30, v11305; GFX9-NEXT: s_setpc_b64 s[30:31]1306;1307; GFX942-LABEL: udiv64_i32max:1308; GFX942: ; %bb.0: ; %entry1309; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1310; GFX942-NEXT: v_mul_hi_u32 v2, v0, 51311; GFX942-NEXT: v_mov_b32_e32 v3, 01312; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v1, 5, v[2:3]1313; GFX942-NEXT: v_mov_b32_e32 v2, v51314; GFX942-NEXT: v_mov_b32_e32 v5, v31315; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v0, 2, v[4:5]1316; GFX942-NEXT: v_mov_b32_e32 v4, v51317; GFX942-NEXT: v_mov_b32_e32 v5, v31318; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 0, v[4:5]1319; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v1, 2, v[2:3]1320; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v21321; GFX942-NEXT: s_nop 11322; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc1323; GFX942-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]1324; GFX942-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3]1325; GFX942-NEXT: v_alignbit_b32 v0, v1, v0, 301326; GFX942-NEXT: v_lshrrev_b32_e32 v1, 30, v11327; GFX942-NEXT: s_setpc_b64 s[30:31]1328;1329; GFX1030-LABEL: udiv64_i32max:1330; GFX1030: ; %bb.0: ; %entry1331; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1332; GFX1030-NEXT: v_mul_hi_u32 v2, v0, 51333; GFX1030-NEXT: v_mov_b32_e32 v3, 01334; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, v1, 5, v[2:3]1335; GFX1030-NEXT: v_mov_b32_e32 v2, v41336; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v0, 2, v[2:3]1337; GFX1030-NEXT: v_add_co_u32 v2, s4, v5, v31338; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s41339; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v1, 2, v[2:3]1340; GFX1030-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v21341; GFX1030-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v3, vcc_lo1342; GFX1030-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]1343; GFX1030-NEXT: v_add_co_u32 v0, vcc_lo, v0, v21344; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo1345; GFX1030-NEXT: v_alignbit_b32 v0, v1, v0, 301346; GFX1030-NEXT: v_lshrrev_b32_e32 v1, 30, v11347; GFX1030-NEXT: s_setpc_b64 s[30:31]1348entry:1349 %div = udiv i64 %i, 21474836471350 ret i64 %div1351}1352