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1; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=tonga | FileCheck --check-prefix=GCN %s2; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=gfx810 | FileCheck --check-prefix=GCN %s3; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=gfx900 | FileCheck -check-prefixes=GCN,GFX9 %s4 5; Testing for failures in divergence calculations when divergent intrinsic is lowered during instruction selection6 7@0 = external dso_local addrspace(4) constant [4 x <4 x float>]8 9; GCN-LABEL: {{^}}_amdgpu_ps_main:10; GCN-NOT: v_readfirstlane11; PRE-GFX9: flat_load_dword12; GFX9: global_load13define dllexport amdgpu_ps void @_amdgpu_ps_main(i32 inreg %arg) local_unnamed_addr #0 {14.entry:15 %tmp = call float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %arg) #116 %tmp1 = bitcast float %tmp to i3217 %tmp2 = srem i32 %tmp1, 418 %tmp3 = select i1 false, i32 poison, i32 %tmp219 %tmp4 = sext i32 %tmp3 to i6420 %tmp5 = getelementptr [4 x <4 x float>], ptr addrspace(4) @0, i64 0, i64 %tmp421 %tmp6 = load <4 x float>, ptr addrspace(4) %tmp5, align 1622 %tmp7 = extractelement <4 x float> %tmp6, i32 323 %tmp8 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float poison, float %tmp7) #124 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> poison, <2 x half> %tmp8, i1 true, i1 true) #225 ret void26}27 28declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #129declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #130declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #231 32attributes #0 = { nounwind "InitialPSInputAddr"="0" }33attributes #1 = { nounwind readnone speculatable }34attributes #2 = { nounwind }35