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1; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -print-after=si-annotate-control-flow %s -filetype=null 2>&1 | FileCheck %s2 3; CHECK-LABEL: @switch_unreachable_default4 5define amdgpu_kernel void @switch_unreachable_default(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #0 {6centry:7 %tid = call i32 @llvm.amdgcn.workitem.id.x()8 switch i32 %tid, label %sw.default [9 i32 0, label %sw.bb010 i32 1, label %sw.bb111 ]12 13sw.bb0:14 br label %sw.epilog15 16sw.bb1:17 br label %sw.epilog18 19sw.default:20 unreachable21 22sw.epilog:23 %ptr = phi ptr addrspace(1) [%in0, %sw.bb0], [%in1, %sw.bb1]24 br label %sw.while25 26; The loop below is necessary to preserve the effect of the27; unreachable default on divergence analysis in the presence of other28; optimizations. The loop consists of a single block where the loop29; exit is divergent because it depends on the divergent phi at the30; start of the block. The checks below ensure that the loop exit is31; handled correctly as divergent. But the data-flow within the block32; is sensitive to optimizations; so we just ensure that the relevant33; operations in the block body are indeed in the same block.34 35; CHECK: [[PHI:%[a-zA-Z0-9._]+]] = phi i6436; CHECK-NOT: {{ br }}37; CHECK: load i838; CHECK-NOT: {{ br }}39; CHECK: [[ICMP:%[a-zA-Z0-9._]+]] = icmp eq40; CHECK: [[IF:%[a-zA-Z0-9._]+]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[ICMP]], i64 [[PHI]])41; CHECK: [[LOOP:%[a-zA-Z0-9._]+]] = call i1 @llvm.amdgcn.loop.i64(i64 [[IF]])42; CHECK: br i1 [[LOOP]]43 44sw.while:45 %p = phi ptr addrspace(1) [ %ptr, %sw.epilog ], [ %incdec.ptr, %sw.while ]46 %count = phi i32 [ 0, %sw.epilog ], [ %count.inc, %sw.while ]47 %char = load i8, ptr addrspace(1) %p, align 148 %tobool = icmp eq i8 %char, 049 %incdec.ptr = getelementptr inbounds i8, ptr addrspace(1) %p, i64 150 %count.inc = add i32 %count, 151 br i1 %tobool, label %sw.exit, label %sw.while52 53sw.exit:54 %tid64 = zext i32 %tid to i6455 %gep_out = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %tid6456 store i32 %count, ptr addrspace(1) %gep_out, align 457 ret void58}59 60declare i32 @llvm.amdgcn.workitem.id.x() #061 62attributes #0 = { nounwind readnone }63attributes #1 = { convergent noinline optnone }64