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1; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s2; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX900 %s3; RUN: llc -mtriple=amdgcn -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX900 %s5 6; GCN-LABEL: name: s_abs_i327; GCN: S_ABS_I328define amdgpu_kernel void @s_abs_i32(ptr addrspace(1) %out, i32 %val) nounwind {9 %neg = sub i32 0, %val10 %cond = icmp sgt i32 %val, %neg11 %res = select i1 %cond, i32 %val, i32 %neg12 %res2 = add i32 %res, 213 store i32 %res2, ptr addrspace(1) %out, align 414 ret void15}16 17; GCN-LABEL: name: v_abs_i3218; SI: V_SUB_CO_U32_e6419; GFX900: V_SUB_U32_e6420; GCN: V_MAX_I32_e6421define amdgpu_kernel void @v_abs_i32(ptr addrspace(1) %out, ptr addrspace(1) %src) nounwind {22 %tid = call i32 @llvm.amdgcn.workitem.id.x()23 %gep.in = getelementptr inbounds i32, ptr addrspace(1) %src, i32 %tid24 %val = load i32, ptr addrspace(1) %gep.in, align 425 %neg = sub i32 0, %val26 %cond = icmp sgt i32 %val, %neg27 %res = select i1 %cond, i32 %val, i32 %neg28 %res2 = add i32 %res, 229 store i32 %res2, ptr addrspace(1) %out, align 430 ret void31}32 33; GCN-LABEL: name: s_abs_v2i3234; GCN: S_ABS_I3235; GCN: S_ABS_I3236define amdgpu_kernel void @s_abs_v2i32(ptr addrspace(1) %out, <2 x i32> %val) nounwind {37 %z0 = insertelement <2 x i32> poison, i32 0, i32 038 %z1 = insertelement <2 x i32> %z0, i32 0, i32 139 %t0 = insertelement <2 x i32> poison, i32 2, i32 040 %t1 = insertelement <2 x i32> %t0, i32 2, i32 141 %neg = sub <2 x i32> %z1, %val42 %cond = icmp sgt <2 x i32> %val, %neg43 %res = select <2 x i1> %cond, <2 x i32> %val, <2 x i32> %neg44 %res2 = add <2 x i32> %res, %t145 store <2 x i32> %res2, ptr addrspace(1) %out, align 446 ret void47}48 49; GCN-LABEL: name: v_abs_v2i3250; SI: V_SUB_CO_U32_e6451; GFX900: V_SUB_U32_e6452; GCN: V_MAX_I32_e6453; GCN: V_MAX_I32_e6454define amdgpu_kernel void @v_abs_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %src) nounwind {55 %z0 = insertelement <2 x i32> poison, i32 0, i32 056 %z1 = insertelement <2 x i32> %z0, i32 0, i32 157 %t0 = insertelement <2 x i32> poison, i32 2, i32 058 %t1 = insertelement <2 x i32> %t0, i32 2, i32 159 %tid = call i32 @llvm.amdgcn.workitem.id.x()60 %gep.in = getelementptr inbounds <2 x i32>, ptr addrspace(1) %src, i32 %tid61 %val = load <2 x i32>, ptr addrspace(1) %gep.in, align 462 %neg = sub <2 x i32> %z1, %val63 %cond = icmp sgt <2 x i32> %val, %neg64 %res = select <2 x i1> %cond, <2 x i32> %val, <2 x i32> %neg65 %res2 = add <2 x i32> %res, %t166 store <2 x i32> %res2, ptr addrspace(1) %out, align 467 ret void68}69 70declare i32 @llvm.amdgcn.workitem.id.x() #071 72attributes #0 = { nounwind readnone }73attributes #1 = { nounwind }74