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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope --check-prefixes=GCN %s3 4define amdgpu_kernel void @uniform_sext_in_reg_i8_to_i32(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {5; GCN-LABEL: uniform_sext_in_reg_i8_to_i32:6; GCN: ; %bb.0:7; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x98; GCN-NEXT: s_waitcnt lgkmcnt(0)9; GCN-NEXT: s_mov_b64 s[4:5], s[2:3]10; GCN-NEXT: s_mov_b32 s3, 0xf00011; GCN-NEXT: s_add_i32 s2, s4, s512; GCN-NEXT: s_sext_i32_i8 s4, s213; GCN-NEXT: s_mov_b32 s2, -114; GCN-NEXT: v_mov_b32_e32 v0, s415; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 016; GCN-NEXT: s_endpgm17 %c = add i32 %a, %b ; add to prevent folding into extload18 %shl = shl i32 %c, 2419 %ashr = ashr i32 %shl, 2420 store i32 %ashr, ptr addrspace(1) %out, align 421 ret void22}23 24define amdgpu_kernel void @divergent_sext_in_reg_i8_to_i32(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {25; GCN-LABEL: divergent_sext_in_reg_i8_to_i32:26; GCN: ; %bb.0:27; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x928; GCN-NEXT: s_waitcnt lgkmcnt(0)29; GCN-NEXT: s_mov_b64 s[4:5], s[2:3]30; GCN-NEXT: s_mov_b32 s3, 0xf00031; GCN-NEXT: s_mov_b32 s2, -132; GCN-NEXT: s_add_i32 s4, s4, s533; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v034; GCN-NEXT: v_bfe_i32 v0, v0, 0, 835; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 036; GCN-NEXT: s_endpgm37 %tid = call i32 @llvm.amdgcn.workitem.id.x()38 %c = add i32 %a, %b ; add to prevent folding into extload39 %c.divergent = add i32 %c, %tid40 %shl = shl i32 %c.divergent, 2441 %ashr = ashr i32 %shl, 2442 store i32 %ashr, ptr addrspace(1) %out, align 443 ret void44}45 46define amdgpu_kernel void @uniform_sext_in_reg_i16_to_i32(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {47; GCN-LABEL: uniform_sext_in_reg_i16_to_i32:48; GCN: ; %bb.0:49; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x950; GCN-NEXT: s_waitcnt lgkmcnt(0)51; GCN-NEXT: s_mov_b64 s[4:5], s[2:3]52; GCN-NEXT: s_mov_b32 s3, 0xf00053; GCN-NEXT: s_add_i32 s2, s4, s554; GCN-NEXT: s_sext_i32_i16 s4, s255; GCN-NEXT: s_mov_b32 s2, -156; GCN-NEXT: v_mov_b32_e32 v0, s457; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 058; GCN-NEXT: s_endpgm59 %c = add i32 %a, %b ; add to prevent folding into extload60 %shl = shl i32 %c, 1661 %ashr = ashr i32 %shl, 1662 store i32 %ashr, ptr addrspace(1) %out, align 463 ret void64}65 66define amdgpu_kernel void @divergent_sext_in_reg_i16_to_i32(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {67; GCN-LABEL: divergent_sext_in_reg_i16_to_i32:68; GCN: ; %bb.0:69; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x970; GCN-NEXT: s_waitcnt lgkmcnt(0)71; GCN-NEXT: s_mov_b64 s[4:5], s[2:3]72; GCN-NEXT: s_mov_b32 s3, 0xf00073; GCN-NEXT: s_mov_b32 s2, -174; GCN-NEXT: s_add_i32 s4, s4, s575; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v076; GCN-NEXT: v_bfe_i32 v0, v0, 0, 1677; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 078; GCN-NEXT: s_endpgm79 %tid = call i32 @llvm.amdgcn.workitem.id.x()80 %c = add i32 %a, %b ; add to prevent folding into extload81 %c.divergent = add i32 %c, %tid82 %shl = shl i32 %c.divergent, 1683 %ashr = ashr i32 %shl, 1684 store i32 %ashr, ptr addrspace(1) %out, align 485 ret void86}87 88declare i32 @llvm.amdgcn.workitem.id.x() #189 90attributes #0 = { nounwind }91attributes #1 = { nounwind readnone speculatable }92