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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -mtriple=amdgcn-- -mcpu=tonga -amdgpu-codegenprepare %s | FileCheck %s3 4define amdgpu_kernel void @divrem24_assume(ptr addrspace(1) %arg, i32 %arg1) {5; CHECK-LABEL: @divrem24_assume(6; CHECK-NEXT: bb:7; CHECK-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !08; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[ARG1:%.*]], 429; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP2]])10; CHECK-NEXT: [[TMP0:%.*]] = uitofp i32 [[TMP]] to float11; CHECK-NEXT: [[TMP1:%.*]] = uitofp i32 [[ARG1]] to float12; CHECK-NEXT: [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]])13; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP0]], [[TMP2]]14; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.trunc.f32(float [[TMP3]])15; CHECK-NEXT: [[TMP5:%.*]] = fneg fast float [[TMP4]]16; CHECK-NEXT: [[TMP6:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP5]], float [[TMP1]], float [[TMP0]])17; CHECK-NEXT: [[TMP7:%.*]] = fptoui float [[TMP4]] to i3218; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])19; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.fabs.f32(float [[TMP1]])20; CHECK-NEXT: [[TMP10:%.*]] = fcmp fast oge float [[TMP8]], [[TMP9]]21; CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i32 1, i32 022; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP7]], [[TMP11]]23; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[TMP12]], 102324; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP13]] to i6425; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG:%.*]], i64 [[TMP4]]26; CHECK-NEXT: store i32 0, ptr addrspace(1) [[TMP5]], align 427; CHECK-NEXT: ret void28;29bb:30 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !031 %tmp2 = icmp ult i32 %arg1, 4232 tail call void @llvm.assume(i1 %tmp2)33 %tmp3 = udiv i32 %tmp, %arg134 %tmp4 = zext i32 %tmp3 to i6435 %tmp5 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp436 store i32 0, ptr addrspace(1) %tmp5, align 437 ret void38}39 40declare void @llvm.assume(i1)41declare i32 @llvm.amdgcn.workitem.id.x()42 43!0 = !{i32 0, i32 1024}44