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1# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=GCN2# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=GCN3# RUN: llc -mtriple=amdgcn -mcpu=gfx1251 -run-pass=gcn-dpp-combine -o - %s | FileCheck %s --check-prefix=GCN4 5---6# GCN-LABEL: name: dpp64_old_impdef7# GCN: %3:vreg_64_align2 = V_CEIL_F64_dpp %1, 0, %0, 337, 15, 15, 1, implicit $mode, implicit $exec8---9name: dpp64_old_impdef10tracksRegLiveness: true11body: |12 bb.0:13 %0:vreg_64_align2 = IMPLICIT_DEF14 %1:vreg_64_align2 = IMPLICIT_DEF15 %2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO %1, %0, 337, 15, 15, 1, implicit $exec16 %3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec17...18 19# GCN-LABEL: name: dpp64_old_undef20# GCN: %3:vreg_64_align2 = V_CEIL_F64_dpp undef %1:vreg_64_align2, 0, undef %2:vreg_64_align2, 337, 15, 15, 1, implicit $mode, implicit $exec21---22name: dpp64_old_undef23tracksRegLiveness: true24body: |25 bb.0:26 %2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64_align2, undef %0:vreg_64_align2, 337, 15, 15, 1, implicit $exec27 %3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec28...29 30# GCN-LABEL: name: dpp64_old_is_031# GCN: %3:vreg_64_align2 = V_CEIL_F64_dpp %4, 0, undef %2:vreg_64_align2, 337, 15, 15, 1, implicit $mode, implicit $exec32name: dpp64_old_is_033tracksRegLiveness: true34body: |35 bb.0:36 %1:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec37 %2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO undef %1, undef %0:vreg_64_align2, 337, 15, 15, 1, implicit $exec38 %3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec39...40 41# DPP64 does not support all control values and must be split to become legal42# GCN-LABEL: name: dpp64_illegal_ctrl43# GCN: %4:vgpr_32 = V_MOV_B32_dpp undef %1.sub0:vreg_64_align2, undef %2.sub0:vreg_64_align2, 1, 15, 15, 1, implicit $exec44# GCN: %5:vgpr_32 = V_MOV_B32_dpp undef %1.sub1:vreg_64_align2, undef %2.sub1:vreg_64_align2, 1, 15, 15, 1, implicit $exec45# GCN: %0:vreg_64_align2 = REG_SEQUENCE %4, %subreg.sub0, %5, %subreg.sub146# GCN: %3:vreg_64_align2 = V_CEIL_F64_e32 %0, implicit $mode, implicit $exec47name: dpp64_illegal_ctrl48tracksRegLiveness: true49body: |50 bb.0:51 %2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64_align2, undef %0:vreg_64_align2, 1, 15, 15, 1, implicit $exec52 %3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec53...54