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1; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefixes=GCN,GFX9GFX102; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s -check-prefixes=GCN,GFX9GFX103; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-TRUE164; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-FAKE165; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-TRUE166; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-FAKE167; RUN: llc -mtriple=amdgcn -mcpu=gfx1251 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-TRUE168; RUN: llc -mtriple=amdgcn -mcpu=gfx1251 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-FAKE169 10; GCN-LABEL: {{^}}dpp_add:11; GCN: global_load_{{dword|b32}} [[V:v[0-9]+]],12; GCN: v_add_{{(nc_)?}}u32_dpp [[V]], [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}13define amdgpu_kernel void @dpp_add(ptr addrspace(1) %arg) {14 %id = tail call i32 @llvm.amdgcn.workitem.id.x()15 %gep = getelementptr inbounds i32, ptr addrspace(1) %arg, i32 %id16 %load = load i32, ptr addrspace(1) %gep17 %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %load, i32 %load, i32 1, i32 15, i32 15, i1 1) #018 %add = add i32 %tmp0, %load19 store i32 %add, ptr addrspace(1) %gep20 ret void21}22 23; GCN-LABEL: {{^}}dpp_ceil:24; GCN: global_load_{{dword|b32}} [[V:v[0-9]+]],25; GCN: v_ceil_f32_dpp [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}26define amdgpu_kernel void @dpp_ceil(ptr addrspace(1) %arg) {27 %id = tail call i32 @llvm.amdgcn.workitem.id.x()28 %gep = getelementptr inbounds i32, ptr addrspace(1) %arg, i32 %id29 %load = load i32, ptr addrspace(1) %gep30 %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %load, i32 %load, i32 1, i32 15, i32 15, i1 1) #031 %tmp1 = bitcast i32 %tmp0 to float32 %round = tail call float @llvm.ceil.f32(float %tmp1)33 %tmp2 = bitcast float %round to i3234 store i32 %tmp2, ptr addrspace(1) %gep35 ret void36}37 38; GCN-LABEL: {{^}}dpp_fadd:39; GCN: global_load_{{dword|b32}} [[V:v[0-9]+]],40; GCN: v_add_f32_dpp [[V]], [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}41define amdgpu_kernel void @dpp_fadd(ptr addrspace(1) %arg) {42 %id = tail call i32 @llvm.amdgcn.workitem.id.x()43 %gep = getelementptr inbounds i32, ptr addrspace(1) %arg, i32 %id44 %load = load i32, ptr addrspace(1) %gep45 %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %load, i32 %load, i32 1, i32 15, i32 15, i1 1) #046 %tmp1 = bitcast i32 %tmp0 to float47 %t = bitcast i32 %load to float48 %add = fadd float %tmp1, %t49 %tmp2 = bitcast float %add to i3250 store i32 %tmp2, ptr addrspace(1) %gep51 ret void52}53 54; Fails to combine prior to gfx1251 because v_mul_lo_u32 has no e32 or dpp form.55; Fails to combine on gfx1251 because DPP control value is invalid for DP DPP and v_mul_lo_u32 is56; classified as DP DPP.57; GCN-LABEL: {{^}}dpp_mul:58; GCN: global_load_{{dword|b32}} [[V:v[0-9]+]],59; GCN: v_mov_b32_e32 [[V2:v[0-9]+]], [[V]]60; GCN: v_mov_b32_dpp [[V2]], [[V2]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}61; GCN: v_mul_lo_u32 [[V]], [[V2]], [[V]]{{$}}62define amdgpu_kernel void @dpp_mul(ptr addrspace(1) %arg) {63 %id = tail call i32 @llvm.amdgcn.workitem.id.x()64 %gep = getelementptr inbounds i32, ptr addrspace(1) %arg, i32 %id65 %load = load i32, ptr addrspace(1) %gep66 %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %load, i32 %load, i32 1, i32 15, i32 15, i1 1)67 %mul = mul i32 %tmp0, %load68 store i32 %mul, ptr addrspace(1) %gep69 ret void70}71 72; It is not expected to see a sequence of v_mov_b32_dpp feeding into a 16 bit instruction73; GCN-LABEL: {{^}}dpp_fadd_f16:74; GFX9GFX10: global_load_{{dword|b32}} [[V:v[0-9]+]],75; GFX9GFX10: v_add_f16_dpp [[V]], [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}76; GFX11-TRUE16: v_mov_b32_dpp {{v[0-9]+}}, {{v[0-9]+}} quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:177; GFX11-TRUE16: v_add_f16_e3278; GFX11-FAKE16: global_load_{{dword|b32}} [[V:v[0-9]+]],79; GFX11-FAKE16: v_add_f16_e64_dpp [[V]], [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:180define amdgpu_kernel void @dpp_fadd_f16(ptr addrspace(1) %arg) {81 %id = tail call i32 @llvm.amdgcn.workitem.id.x()82 %gep = getelementptr inbounds i32, ptr addrspace(1) %arg, i32 %id83 %load = load i32, ptr addrspace(1) %gep84 %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %load, i32 %load, i32 1, i32 15, i32 15, i1 1) #085 %tmp01 = trunc i32 %tmp0 to i1686 %tmp1 = bitcast i16 %tmp01 to half87 %tt = trunc i32 %load to i1688 %t = bitcast i16 %tt to half89 %add = fadd half %tmp1, %t90 %tmp2 = bitcast half %add to i1691 %tmp3 = zext i16 %tmp2 to i3292 store i32 %tmp3, ptr addrspace(1) %gep93 ret void94}95 96declare i32 @llvm.amdgcn.workitem.id.x()97declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) #098declare float @llvm.ceil.f32(float)99 100attributes #0 = { nounwind readnone convergent }101