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1# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN2# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN3 4---5# old is undefined: only combine when masks are fully enabled and6# bound_ctrl:1 is set, otherwise the result of DPP VALU op can be undefined.7# GCN-LABEL: name: old_is_undef8# GCN: %2:vgpr_32 = IMPLICIT_DEF9# VOP2:10# GCN: %4:vgpr_32 = V_ADD_U32_dpp %2, %0, %1, 1, 15, 15, 1, implicit $exec11# GCN: %6:vgpr_32 = V_ADD_U32_e32 %5, %1, implicit $exec12# GCN: %8:vgpr_32 = V_ADD_U32_e32 %7, %1, implicit $exec13# GCN: %10:vgpr_32 = V_ADD_U32_e32 %9, %1, implicit $exec14# VOP1:15# GCN: %12:vgpr_32 = V_NOT_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec16# GCN: %14:vgpr_32 = V_NOT_B32_e32 %13, implicit $exec17# GCN: %16:vgpr_32 = V_NOT_B32_e32 %15, implicit $exec18# GCN: %18:vgpr_32 = V_NOT_B32_e32 %17, implicit $exec19name: old_is_undef20tracksRegLiveness: true21body: |22 bb.0:23 liveins: $vgpr0, $vgpr124 %0:vgpr_32 = COPY $vgpr025 %1:vgpr_32 = COPY $vgpr126 %2:vgpr_32 = IMPLICIT_DEF27 28 ; VOP229 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec30 %4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec31 32 %5:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 0, implicit $exec33 %6:vgpr_32 = V_ADD_U32_e32 %5, %1, implicit $exec34 35 %7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 1, implicit $exec36 %8:vgpr_32 = V_ADD_U32_e32 %7, %1, implicit $exec37 38 %9:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec39 %10:vgpr_32 = V_ADD_U32_e32 %9, %1, implicit $exec40 41 ; VOP142 %11:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec43 %12:vgpr_32 = V_NOT_B32_e32 %11, implicit $exec44 45 %13:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 0, implicit $exec46 %14:vgpr_32 = V_NOT_B32_e32 %13, implicit $exec47 48 %15:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 1, implicit $exec49 %16:vgpr_32 = V_NOT_B32_e32 %15, implicit $exec50 51 %17:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec52 %18:vgpr_32 = V_NOT_B32_e32 %17, implicit $exec53...54 55# old is zero cases:56 57# GCN-LABEL: name: old_is_058 59# VOP2:60# case 1: old is zero, masks are fully enabled, bound_ctrl:1 is on:61# the DPP mov result would be either zero ({src lane disabled}|{src lane is62# out of range}) or active src lane result - can combine with old = undef.63# undef is preffered as it makes life easier for the regalloc.64# GCN: [[U1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF65# GCN: %4:vgpr_32 = V_ADD_U32_dpp [[U1]], %0, %1, 1, 15, 15, 1, implicit $exec66 67# case 2: old is zero, masks are fully enabled, bound_ctrl:1 is off:68# as the DPP mov old is zero this case is no different from case 1 - combine it69# setting bound_ctrl:1 on for the combined DPP VALU op to make old undefined70# GCN: [[U2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF71# GCN: %6:vgpr_32 = V_ADD_U32_dpp [[U2]], %0, %1, 1, 15, 15, 1, implicit $exec72 73# case 3: masks are partialy disabled, bound_ctrl:1 is on:74# the DPP mov result would be either zero ({src lane disabled}|{src lane is75# out of range} or {the DPP mov's dest VGPR write is disabled by masks}) or76# active src lane result - can combine with old = src1 of the VALU op.77# The VALU op should have the same masks as DPP mov as they select lanes78# with identity value.79# Special case: the bound_ctrl for the combined DPP VALU op isn't important80# here but let's make it off to keep the combiner's logic simpler.81# GCN: %8:vgpr_32 = V_ADD_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec82 83# case 4: masks are partialy disabled, bound_ctrl:1 is off:84# the DPP mov result would be either zero ({src lane disabled}|{src lane is85# out of range} or {the DPP mov's dest VGPR write is disabled by masks}) or86# active src lane result - can combine with old = src1 of the VALU op.87# The VALU op should have the same masks as DPP mov as they select88# lanes with identity value89# GCN: %10:vgpr_32 = V_ADD_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec90 91# VOP1:92# see case 193# GCN: [[U3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF94# GCN: %12:vgpr_32 = V_NOT_B32_dpp [[U3]], %0, 1, 15, 15, 1, implicit $exec95# see case 296# GCN: [[U4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF97# GCN: %14:vgpr_32 = V_NOT_B32_dpp [[U4]], %0, 1, 15, 15, 1, implicit $exec98# case 3 and 4 not appliable as there is no way to specify unchanged result99# for the unary VALU op100# GCN: %16:vgpr_32 = V_NOT_B32_e32 %15, implicit $exec101# GCN: %18:vgpr_32 = V_NOT_B32_e32 %17, implicit $exec102 103name: old_is_0104tracksRegLiveness: true105body: |106 bb.0:107 liveins: $vgpr0, $vgpr1108 %0:vgpr_32 = COPY $vgpr0109 %1:vgpr_32 = COPY $vgpr1110 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec111 112 ; VOP2113 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec114 %4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec115 116 %5:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 0, implicit $exec117 %6:vgpr_32 = V_ADD_U32_e32 %5, %1, implicit $exec118 119 %7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 1, implicit $exec120 %8:vgpr_32 = V_ADD_U32_e32 %7, %1, implicit $exec121 122 %9:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec123 %10:vgpr_32 = V_ADD_U32_e32 %9, %1, implicit $exec124 125 ; VOP1126 %11:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec127 %12:vgpr_32 = V_NOT_B32_e32 %11, implicit $exec128 129 %13:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 0, implicit $exec130 %14:vgpr_32 = V_NOT_B32_e32 %13, implicit $exec131 132 %15:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 1, implicit $exec133 %16:vgpr_32 = V_NOT_B32_e32 %15, implicit $exec134 135 %17:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec136 %18:vgpr_32 = V_NOT_B32_e32 %17, implicit $exec137...138 139# old is nonzero identity cases:140 141# old is nonzero identity, masks are fully enabled, bound_ctrl:1 is off:142# the DPP mov result would be either identity ({src lane disabled}|{out of143# range}) or src lane result - can combine with old = src1 of the VALU op144# The DPP VALU op should have the same masks (and bctrl) as DPP mov as they145# select lanes with identity value146 147# GCN-LABEL: name: nonzero_old_is_identity_masks_enabled_bctl_off148# GCN: %4:vgpr_32 = V_MUL_U32_U24_dpp %1, %0, %1, 1, 15, 15, 0, implicit $exec149# GCN: %7:vgpr_32 = V_AND_B32_dpp %1, %0, %1, 1, 15, 15, 0, implicit $exec150# GCN: %10:vgpr_32 = V_MAX_I32_dpp %1, %0, %1, 1, 15, 15, 0, implicit $exec151# GCN: %13:vgpr_32 = V_MIN_I32_dpp %1, %0, %1, 1, 15, 15, 0, implicit $exec152 153name: nonzero_old_is_identity_masks_enabled_bctl_off154tracksRegLiveness: true155body: |156 bb.0:157 liveins: $vgpr0, $vgpr1158 %0:vgpr_32 = COPY $vgpr0159 %1:vgpr_32 = COPY $vgpr1160 161 %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec162 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 0, implicit $exec163 %4:vgpr_32 = V_MUL_U32_U24_e32 %3, %1, implicit $exec164 165 %5:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec166 %6:vgpr_32 = V_MOV_B32_dpp %5, %0, 1, 15, 15, 0, implicit $exec167 %7:vgpr_32 = V_AND_B32_e32 %6, %1, implicit $exec168 169 %8:vgpr_32 = V_MOV_B32_e32 -2147483648, implicit $exec170 %9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 15, 15, 0, implicit $exec171 %10:vgpr_32 = V_MAX_I32_e32 %9, %1, implicit $exec172 173 %11:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec174 %12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 15, 15, 0, implicit $exec175 %13:vgpr_32 = V_MIN_I32_e32 %12, %1, implicit $exec176...177 178# old is nonzero identity, masks are partially enabled, bound_ctrl:1 is off:179# the DPP mov result would be either identity ({src lane disabled}|{src lane is180# out of range} or {the DPP mov's dest VGPR write is disabled by masks}) or181# active src lane result - can combine with old = src1 of the VALU op.182# The DPP VALU op should have the same masks (and bctrl) as DPP mov as they183# select lanes with identity value184 185# GCN-LABEL: name: nonzero_old_is_identity_masks_partially_disabled_bctl_off186# GCN: %4:vgpr_32 = V_MUL_U32_U24_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec187# GCN: %7:vgpr_32 = V_AND_B32_dpp %1, %0, %1, 1, 15, 14, 0, implicit $exec188# GCN: %10:vgpr_32 = V_MAX_I32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec189# GCN: %13:vgpr_32 = V_MIN_I32_dpp %1, %0, %1, 1, 15, 14, 0, implicit $exec190 191name: nonzero_old_is_identity_masks_partially_disabled_bctl_off192tracksRegLiveness: true193body: |194 bb.0:195 liveins: $vgpr0, $vgpr1196 %0:vgpr_32 = COPY $vgpr0197 %1:vgpr_32 = COPY $vgpr1198 199 %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec200 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec201 %4:vgpr_32 = V_MUL_U32_U24_e32 %3, %1, implicit $exec202 203 %5:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec204 %6:vgpr_32 = V_MOV_B32_dpp %5, %0, 1, 15, 14, 0, implicit $exec205 %7:vgpr_32 = V_AND_B32_e32 %6, %1, implicit $exec206 207 %8:vgpr_32 = V_MOV_B32_e32 -2147483648, implicit $exec208 %9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 14, 15, 0, implicit $exec209 %10:vgpr_32 = V_MAX_I32_e32 %9, %1, implicit $exec210 211 %11:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec212 %12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 15, 14, 0, implicit $exec213 %13:vgpr_32 = V_MIN_I32_e32 %12, %1, implicit $exec214...215 216# old is nonzero identity, masks are partially enabled, bound_ctrl:1 is on:217# the DPP mov result may have 3 different values:218# 1. the active src lane result219# 2. 0 if the src lane is disabled|out of range220# 3. DPP mov's old value if the mov's dest VGPR write is disabled by masks221# can't combine222 223# GCN-LABEL: name: nonzero_old_is_identity_masks_partially_disabled_bctl0224# GCN: %4:vgpr_32 = V_MUL_U32_U24_e32 %3, %1, implicit $exec225# GCN: %7:vgpr_32 = V_AND_B32_e32 %6, %1, implicit $exec226# GCN: %10:vgpr_32 = V_MAX_I32_e32 %9, %1, implicit $exec227# GCN: %13:vgpr_32 = V_MIN_I32_e32 %12, %1, implicit $exec228 229name: nonzero_old_is_identity_masks_partially_disabled_bctl0230tracksRegLiveness: true231body: |232 bb.0:233 liveins: $vgpr0, $vgpr1234 %0:vgpr_32 = COPY $vgpr0235 %1:vgpr_32 = COPY $vgpr1236 237 %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec238 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 1, implicit $exec239 %4:vgpr_32 = V_MUL_U32_U24_e32 %3, %1, implicit $exec240 241 %5:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec242 %6:vgpr_32 = V_MOV_B32_dpp %5, %0, 1, 15, 14, 1, implicit $exec243 %7:vgpr_32 = V_AND_B32_e32 %6, %1, implicit $exec244 245 %8:vgpr_32 = V_MOV_B32_e32 -2147483648, implicit $exec246 %9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 14, 15, 1, implicit $exec247 %10:vgpr_32 = V_MAX_I32_e32 %9, %1, implicit $exec248 249 %11:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec250 %12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 15, 14, 1, implicit $exec251 %13:vgpr_32 = V_MIN_I32_e32 %12, %1, implicit $exec252...253 254# when the DPP source isn't a src0 operand the operation should be commuted if possible255# GCN-LABEL: name: dpp_commute256# GCN: %4:vgpr_32 = V_MUL_U32_U24_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec257# GCN: %7:vgpr_32 = V_AND_B32_dpp %1, %0, %1, 1, 15, 14, 0, implicit $exec258# GCN: %10:vgpr_32 = V_MAX_I32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec259# GCN: %13:vgpr_32 = V_MIN_I32_dpp %1, %0, %1, 1, 15, 14, 0, implicit $exec260# GCN: %16:vgpr_32 = V_SUBREV_CO_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit-def $vcc, implicit $exec261# GCN: %19:vgpr_32 = V_ADD_CO_U32_e32 5, %18, implicit-def $vcc, implicit $exec262name: dpp_commute263tracksRegLiveness: true264body: |265 bb.0:266 liveins: $vgpr0, $vgpr1267 268 %0:vgpr_32 = COPY $vgpr0269 %1:vgpr_32 = COPY $vgpr1270 271 %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec272 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec273 %4:vgpr_32 = V_MUL_U32_U24_e32 %1, %3, implicit $exec274 275 %5:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec276 %6:vgpr_32 = V_MOV_B32_dpp %5, %0, 1, 15, 14, 0, implicit $exec277 %7:vgpr_32 = V_AND_B32_e32 %1, %6, implicit $exec278 279 %8:vgpr_32 = V_MOV_B32_e32 -2147483648, implicit $exec280 %9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 14, 15, 0, implicit $exec281 %10:vgpr_32 = V_MAX_I32_e32 %1, %9, implicit $exec282 283 %11:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec284 %12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 15, 14, 0, implicit $exec285 %13:vgpr_32 = V_MIN_I32_e32 %1, %12, implicit $exec286 287 %14:vgpr_32 = V_MOV_B32_e32 0, implicit $exec288 %15:vgpr_32 = V_MOV_B32_dpp %14, %0, 1, 14, 15, 0, implicit $exec289 %16:vgpr_32 = V_SUB_CO_U32_e32 %1, %15, implicit-def $vcc, implicit $exec290 291 ; this cannot be combined because immediate as src0 isn't commutable292 %17:vgpr_32 = V_MOV_B32_e32 0, implicit $exec293 %18:vgpr_32 = V_MOV_B32_dpp %17, %0, 1, 14, 15, 0, implicit $exec294 %19:vgpr_32 = V_ADD_CO_U32_e32 5, %18, implicit-def $vcc, implicit $exec295...296 297---298 299# check for floating point modifiers300# GCN-LABEL: name: add_f32_e64301# GCN: %3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec302# GCN: %4:vgpr_32 = V_ADD_F32_e64 0, %3, 0, %0, 0, 1, implicit $mode, implicit $exec303# GCN: %6:vgpr_32 = V_ADD_F32_dpp %2, 0, %1, 0, %0, 1, 15, 15, 1, implicit $mode, implicit $exec304# GCN: %8:vgpr_32 = V_ADD_F32_dpp %2, 1, %1, 2, %0, 1, 15, 15, 1, implicit $mode, implicit $exec305# GCN: %10:vgpr_32 = V_ADD_F32_e64 4, %9, 8, %0, 0, 0, implicit $mode, implicit $exec306 307name: add_f32_e64308tracksRegLiveness: true309body: |310 bb.0:311 liveins: $vgpr0, $vgpr1312 313 %0:vgpr_32 = COPY $vgpr0314 %1:vgpr_32 = COPY $vgpr1315 %2:vgpr_32 = IMPLICIT_DEF316 317 ; this shouldn't be combined as omod is set318 %3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec319 %4:vgpr_32 = V_ADD_F32_e64 0, %3, 0, %0, 0, 1, implicit $mode, implicit $exec320 321 ; this should be combined as all modifiers are default322 %5:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec323 %6:vgpr_32 = V_ADD_F32_e64 0, %5, 0, %0, 0, 0, implicit $mode, implicit $exec324 325 ; this should be combined as modifiers other than abs|neg are default326 %7:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec327 %8:vgpr_32 = V_ADD_F32_e64 1, %7, 2, %0, 0, 0, implicit $mode, implicit $exec328 329 ; this shouldn't be combined as modifiers aren't abs|neg330 %9:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec331 %10:vgpr_32 = V_ADD_F32_e64 4, %9, 8, %0, 0, 0, implicit $mode, implicit $exec332...333 334# check for e64 modifiers335# GCN-LABEL: name: add_u32_e64336# GCN: %4:vgpr_32 = V_ADD_U32_dpp %2, %0, %1, 1, 15, 15, 1, implicit $exec337# GCN: %6:vgpr_32 = V_ADD_U32_e64 %5, %1, 1, implicit $exec338 339name: add_u32_e64340tracksRegLiveness: true341body: |342 bb.0:343 liveins: $vgpr0, $vgpr1344 345 %0:vgpr_32 = COPY $vgpr0346 %1:vgpr_32 = COPY $vgpr1347 %2:vgpr_32 = IMPLICIT_DEF348 349 ; this should be combined as all modifiers are default350 %3:vgpr_32 = V_MOV_B32_dpp undef %2, %0, 1, 15, 15, 1, implicit $exec351 %4:vgpr_32 = V_ADD_U32_e64 %3, %1, 0, implicit $exec352 353 ; this shouldn't be combined as clamp is set354 %5:vgpr_32 = V_MOV_B32_dpp undef %2, %0, 1, 15, 15, 1, implicit $exec355 %6:vgpr_32 = V_ADD_U32_e64 %5, %1, 1, implicit $exec356...357 358# GCN-LABEL: name: add_co_u32_e64359# GCN: %4:vgpr_32, %5:sreg_64_xexec = V_ADD_CO_U32_e64 %3, %1, 0, implicit $exec360 361name: add_co_u32_e64362tracksRegLiveness: true363body: |364 bb.0:365 liveins: $vgpr0, $vgpr1366 367 %0:vgpr_32 = COPY $vgpr0368 %1:vgpr_32 = COPY $vgpr1369 %2:vgpr_32 = IMPLICIT_DEF370 371 ; this shouldn't be combined as the carry-out is used372 %3:vgpr_32 = V_MOV_B32_dpp undef %2, %0, 1, 15, 15, 1, implicit $exec373 %4:vgpr_32, %5:sreg_64_xexec = V_ADD_CO_U32_e64 %3, %1, 0, implicit $exec374 375 S_NOP 0, implicit %5376...377 378# tests on sequences of dpp consumers379# GCN-LABEL: name: dpp_seq380# GCN: %4:vgpr_32 = V_ADD_CO_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit-def $vcc, implicit $exec381# GCN: %5:vgpr_32 = V_SUBREV_CO_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit-def $vcc, implicit $exec382# GCN: %6:vgpr_32 = V_OR_B32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec383# broken sequence:384# GCN: %7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec385 386name: dpp_seq387tracksRegLiveness: true388body: |389 bb.0:390 liveins: $vgpr0, $vgpr1391 %0:vgpr_32 = COPY $vgpr0392 %1:vgpr_32 = COPY $vgpr1393 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec394 395 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec396 %4:vgpr_32 = V_ADD_CO_U32_e32 %3, %1, implicit-def $vcc, implicit $exec397 %5:vgpr_32 = V_SUB_CO_U32_e32 %1, %3, implicit-def $vcc, implicit $exec398 %6:vgpr_32 = V_OR_B32_e32 %3, %1, implicit $exec399 400 %7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec401 %8:vgpr_32 = V_ADD_CO_U32_e32 %7, %1, implicit-def $vcc, implicit $exec402 ; this breaks the sequence403 %9:vgpr_32 = V_SUB_CO_U32_e32 5, %7, implicit-def $vcc, implicit $exec404...405 406# tests on sequences of dpp consumers followed by control flow407# GCN-LABEL: name: dpp_seq_cf408# GCN: %4:vgpr_32 = V_ADD_CO_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit-def $vcc, implicit $exec409# GCN: %5:vgpr_32 = V_SUBREV_CO_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit-def $vcc, implicit $exec410# GCN: %6:vgpr_32 = V_OR_B32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec411 412name: dpp_seq_cf413tracksRegLiveness: true414body: |415 bb.0:416 successors: %bb.1, %bb.2417 liveins: $vgpr0, $vgpr1418 %0:vgpr_32 = COPY $vgpr0419 %1:vgpr_32 = COPY $vgpr1420 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec421 422 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec423 %4:vgpr_32 = V_ADD_CO_U32_e32 %3, %1, implicit-def $vcc, implicit $exec424 %5:vgpr_32 = V_SUB_CO_U32_e32 %1, %3, implicit-def $vcc, implicit $exec425 %6:vgpr_32 = V_OR_B32_e32 %3, %1, implicit $exec426 427 %7:sreg_64 = V_CMP_EQ_U32_e64 %5, %6, implicit $exec428 %8:sreg_64 = SI_IF %7, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec429 S_BRANCH %bb.1430 431 bb.1:432 successors: %bb.2433 434 bb.2:435 SI_END_CF %8, implicit-def dead $exec, implicit-def dead $scc, implicit $exec436...437 438# GCN-LABEL: name: old_in_diff_bb439# GCN: %4:vgpr_32 = V_ADD_U32_dpp %0, %1, %0, 1, 1, 1, 0, implicit $exec440 441name: old_in_diff_bb442tracksRegLiveness: true443body: |444 bb.0:445 successors: %bb.1446 liveins: $vgpr0, $vgpr1447 448 %0:vgpr_32 = COPY $vgpr0449 %1:vgpr_32 = COPY $vgpr1450 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec451 S_BRANCH %bb.1452 453 bb.1:454 %3:vgpr_32 = V_MOV_B32_dpp %2, %1, 1, 1, 1, 0, implicit $exec455 %4:vgpr_32 = V_ADD_U32_e32 %3, %0, implicit $exec456...457 458# old reg def is in diff BB but bound_ctrl:1 - can combine459# GCN-LABEL: name: old_in_diff_bb_bctrl_zero460# GCN: %4:vgpr_32 = V_ADD_U32_dpp {{%[0-9]}}, %0, %1, 1, 15, 15, 1, implicit $exec461 462name: old_in_diff_bb_bctrl_zero463tracksRegLiveness: true464body: |465 bb.0:466 successors: %bb.1467 liveins: $vgpr0, $vgpr1468 469 %0:vgpr_32 = COPY $vgpr0470 %1:vgpr_32 = COPY $vgpr1471 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec472 S_BRANCH %bb.1473 474 bb.1:475 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec476 %4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec477...478 479# EXEC mask changed between def and use - cannot combine480# GCN-LABEL: name: exec_changed481# GCN: %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec482 483name: exec_changed484tracksRegLiveness: true485body: |486 bb.0:487 liveins: $vgpr0, $vgpr1488 489 %0:vgpr_32 = COPY $vgpr0490 %1:vgpr_32 = COPY $vgpr1491 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec492 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec493 %4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec494 %5:sreg_64 = COPY $exec, implicit-def $exec495 %6:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec496...497 498# test if $old definition is correctly tracked through subreg manipulation pseudos499 500# GCN-LABEL: name: mul_old_subreg501# GCN: %7:vgpr_32 = V_MUL_I32_I24_dpp %0.sub1, %1, %0.sub1, 1, 1, 1, 0, implicit $exec502 503name: mul_old_subreg504tracksRegLiveness: true505body: |506 bb.0:507 liveins: $vgpr0, $vgpr1508 509 %0:vreg_64 = COPY $vgpr0510 %1:vgpr_32 = COPY $vgpr1511 %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec512 %3:vgpr_32 = V_MOV_B32_e32 42, implicit $exec513 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1514 %5:vreg_64 = INSERT_SUBREG %4, %1, %subreg.sub1 ; %5.sub0 is taken from %4515 %6:vgpr_32 = V_MOV_B32_dpp %5.sub0, %1, 1, 1, 1, 0, implicit $exec516 %7:vgpr_32 = V_MUL_I32_I24_e32 %6, %0.sub1, implicit $exec517...518 519# GCN-LABEL: name: add_old_subreg520# GCN: %5:vgpr_32 = V_ADD_U32_dpp %0.sub1, %1, %0.sub1, 1, 1, 1, 0, implicit $exec521 522name: add_old_subreg523tracksRegLiveness: true524body: |525 bb.0:526 liveins: $vgpr0, $vgpr1527 528 %0:vreg_64 = COPY $vgpr0529 %1:vgpr_32 = COPY $vgpr1530 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec531 %3:vreg_64 = INSERT_SUBREG %0, %2, %subreg.sub1 ; %3.sub1 is inserted532 %4:vgpr_32 = V_MOV_B32_dpp %3.sub1, %1, 1, 1, 1, 0, implicit $exec533 %5:vgpr_32 = V_ADD_U32_e32 %4, %0.sub1, implicit $exec534...535 536# GCN-LABEL: name: add_old_subreg_undef537# GCN: %5:vgpr_32 = V_ADD_U32_dpp undef %3.sub1, %1, %0.sub1, 1, 15, 15, 1, implicit $exec538 539name: add_old_subreg_undef540tracksRegLiveness: true541body: |542 bb.0:543 liveins: $vgpr0, $vgpr1544 545 %0:vreg_64 = COPY $vgpr0546 %1:vgpr_32 = COPY $vgpr1547 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec548 %3:vreg_64 = REG_SEQUENCE %2, %subreg.sub0 ; %3.sub1 is undef549 %4:vgpr_32 = V_MOV_B32_dpp %3.sub1, %1, 1, 15, 15, 1, implicit $exec550 %5:vgpr_32 = V_ADD_U32_e32 %4, %0.sub1, implicit $exec551...552 553# Test instruction which does not have modifiers in VOP1 form but does in DPP form.554# GCN-LABEL: name: dpp_vop1555# GCN: %3:vgpr_32 = V_CEIL_F32_dpp %0, 0, undef %2:vgpr_32, 1, 15, 15, 1, implicit $mode, implicit $exec556name: dpp_vop1557tracksRegLiveness: true558body: |559 bb.0:560 %1:vgpr_32 = IMPLICIT_DEF561 %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec562 %3:vgpr_32 = V_CEIL_F32_e32 %2, implicit $mode, implicit $exec563...564 565# Test instruction which does not have modifiers in VOP2 form but does in DPP form.566# GCN-LABEL: name: dpp_min567# GCN: %3:vgpr_32 = V_MIN_F32_dpp %0, 0, undef %2:vgpr_32, 0, undef %4:vgpr_32, 1, 15, 15, 1, implicit $mode, implicit $exec568name: dpp_min569tracksRegLiveness: true570body: |571 bb.0:572 %1:vgpr_32 = IMPLICIT_DEF573 %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec574 %4:vgpr_32 = V_MIN_F32_e32 %2, undef %3:vgpr_32, implicit $mode, implicit $exec575...576 577# Test an undef old operand578# GCN-LABEL: name: dpp_undef_old579# GCN: %3:vgpr_32 = V_CEIL_F32_dpp undef %1:vgpr_32, 0, undef %2:vgpr_32, 1, 15, 15, 1, implicit $mode, implicit $exec580name: dpp_undef_old581tracksRegLiveness: true582body: |583 bb.0:584 %2:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec585 %3:vgpr_32 = V_CEIL_F32_e32 %2, implicit $mode, implicit $exec586...587 588# Do not combine a dpp mov which writes a physreg.589# GCN-LABEL: name: phys_dpp_mov_dst590# GCN: $vgpr0 = V_MOV_B32_dpp undef %0:vgpr_32, undef %1:vgpr_32, 1, 15, 15, 1, implicit $exec591# GCN: %2:vgpr_32 = V_CEIL_F32_e32 $vgpr0, implicit $mode, implicit $exec592name: phys_dpp_mov_dst593tracksRegLiveness: true594body: |595 bb.0:596 $vgpr0 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec597 %2:vgpr_32 = V_CEIL_F32_e32 $vgpr0, implicit $mode, implicit $exec598...599 600# Do not combine a dpp mov which reads a physreg.601# GCN-LABEL: name: phys_dpp_mov_old_src602# GCN: %0:vgpr_32 = V_MOV_B32_dpp undef $vgpr0, undef %1:vgpr_32, 1, 15, 15, 1, implicit $exec603# GCN: %2:vgpr_32 = V_CEIL_F32_e32 %0, implicit $mode, implicit $exec604name: phys_dpp_mov_old_src605tracksRegLiveness: true606body: |607 bb.0:608 %1:vgpr_32 = V_MOV_B32_dpp undef $vgpr0, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec609 %2:vgpr_32 = V_CEIL_F32_e32 %1, implicit $mode, implicit $exec610...611 612# Do not combine a dpp mov which reads a physreg.613# GCN-LABEL: name: phys_dpp_mov_src614# GCN: %0:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef $vgpr0, 1, 15, 15, 1, implicit $exec615# GCN: %2:vgpr_32 = V_CEIL_F32_e32 %0, implicit $mode, implicit $exec616name: phys_dpp_mov_src617tracksRegLiveness: true618body: |619 bb.0:620 %1:vgpr_32 = V_MOV_B32_dpp undef %0:vgpr_32, undef $vgpr0, 1, 15, 15, 1, implicit $exec621 %2:vgpr_32 = V_CEIL_F32_e32 %1, implicit $mode, implicit $exec622...623 624# GCN-LABEL: name: dpp_reg_sequence_both_combined625# GCN: %0:vreg_64 = COPY $vgpr0_vgpr1626# GCN: %1:vreg_64 = COPY $vgpr2_vgpr3627# GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec628# GCN: %9:vgpr_32 = IMPLICIT_DEF629# GCN: %8:vgpr_32 = IMPLICIT_DEF630# GCN: %6:vgpr_32 = V_ADD_CO_U32_dpp %9, %1.sub0, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $exec631# GCN: %7:vgpr_32 = V_ADDC_U32_dpp %8, %1.sub1, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec632name: dpp_reg_sequence_both_combined633tracksRegLiveness: true634body: |635 bb.0:636 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3637 638 %0:vreg_64 = COPY $vgpr0_vgpr1639 %1:vreg_64 = COPY $vgpr2_vgpr3640 %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec641 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec642 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec643 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1644 %6:vgpr_32 = V_ADD_CO_U32_e32 %4.sub0, %5, implicit-def $vcc, implicit $exec645 %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec646...647 648# GCN-LABEL: name: dpp_reg_sequence_first_combined649# GCN: %0:vreg_64 = COPY $vgpr0_vgpr1650# GCN: %1:vreg_64 = COPY $vgpr2_vgpr3651# GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec652# GCN: %8:vgpr_32 = IMPLICIT_DEF653# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec654# GCN: %5:vreg_64 = REG_SEQUENCE undef %3:vgpr_32, %subreg.sub0, %4, %subreg.sub1655# GCN: %6:vgpr_32 = V_ADD_CO_U32_dpp %8, %1.sub0, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $exec656# GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec657name: dpp_reg_sequence_first_combined658tracksRegLiveness: true659body: |660 bb.0:661 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3662 663 %0:vreg_64 = COPY $vgpr0_vgpr1664 %1:vreg_64 = COPY $vgpr2_vgpr3665 %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec666 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec667 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec668 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1669 %6:vgpr_32 = V_ADD_CO_U32_e32 %4.sub0, %5, implicit-def $vcc, implicit $exec670 %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec671...672 673# GCN-LABEL: name: dpp_reg_sequence_second_combined674# GCN: %0:vreg_64 = COPY $vgpr0_vgpr1675# GCN: %1:vreg_64 = COPY $vgpr2_vgpr3676# GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec677# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec678# GCN: %8:vgpr_32 = IMPLICIT_DEF679# GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, undef %4:vgpr_32, %subreg.sub1680# GCN: %6:vgpr_32 = V_ADD_CO_U32_e32 %5.sub0, %2, implicit-def $vcc, implicit $exec681# GCN: %7:vgpr_32 = V_ADDC_U32_dpp %8, %1.sub1, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec682name: dpp_reg_sequence_second_combined683tracksRegLiveness: true684body: |685 bb.0:686 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3687 688 %0:vreg_64 = COPY $vgpr0_vgpr1689 %1:vreg_64 = COPY $vgpr2_vgpr3690 %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec691 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec692 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec693 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1694 %6:vgpr_32 = V_ADD_CO_U32_e32 %4.sub0, %5, implicit-def $vcc, implicit $exec695 %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec696...697 698# GCN-LABEL: name: dpp_reg_sequence_none_combined699# GCN: %0:vreg_64 = COPY $vgpr0_vgpr1700# GCN: %1:vreg_64 = COPY $vgpr2_vgpr3701# GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec702# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec703# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec704# GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1705# GCN: %6:vgpr_32 = V_ADD_CO_U32_e32 %5.sub0, %2, implicit-def $vcc, implicit $exec706# GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec707name: dpp_reg_sequence_none_combined708tracksRegLiveness: true709body: |710 bb.0:711 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3712 713 %0:vreg_64 = COPY $vgpr0_vgpr1714 %1:vreg_64 = COPY $vgpr2_vgpr3715 %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec716 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec717 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec718 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1719 %6:vgpr_32 = V_ADD_CO_U32_e32 %4.sub0, %5, implicit-def $vcc, implicit $exec720 %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec721...722 723# GCN-LABEL: name: dpp_reg_sequence_exec_changed724# GCN: %0:vreg_64 = COPY $vgpr0_vgpr1725# GCN: %1:vreg_64 = COPY $vgpr2_vgpr3726# GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec727# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec728# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec729# GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1730# GCN: S_BRANCH %bb.1731# GCN: bb.1:732# GCN: %6:vgpr_32 = V_ADD_CO_U32_e32 %5.sub0, %2, implicit-def $vcc, implicit $exec733# GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec734name: dpp_reg_sequence_exec_changed735tracksRegLiveness: true736body: |737 bb.0:738 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3739 740 %0:vreg_64 = COPY $vgpr0_vgpr1741 %1:vreg_64 = COPY $vgpr2_vgpr3742 %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec743 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec744 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec745 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1746 S_BRANCH %bb.1747 748 bb.1:749 %6:vgpr_32 = V_ADD_CO_U32_e32 %4.sub0, %5, implicit-def $vcc, implicit $exec750 %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec751...752 753# GCN-LABEL: name: dpp_reg_sequence_subreg754# GCN: %0:vreg_64 = COPY $vgpr0_vgpr1755# GCN: %1:vreg_64 = COPY $vgpr2_vgpr3756# GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec757# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec758# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec759# GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1760# GCN: %6:vreg_64 = REG_SEQUENCE %5.sub0, %subreg.sub0, %5.sub1, %subreg.sub1761# GCN: %7:vgpr_32 = V_ADD_CO_U32_e32 %6.sub0, %2, implicit-def $vcc, implicit $exec762# GCN: %8:vgpr_32 = V_ADDC_U32_e32 %6.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec763name: dpp_reg_sequence_subreg764tracksRegLiveness: true765body: |766 bb.0:767 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3768 769 %0:vreg_64 = COPY $vgpr0_vgpr1770 %1:vreg_64 = COPY $vgpr2_vgpr3771 %8:vgpr_32 = V_MOV_B32_e32 5, implicit $exec772 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec773 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec774 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1775 %5:vreg_64 = REG_SEQUENCE %4.sub0, %subreg.sub0, %4.sub1, %subreg.sub1776 %6:vgpr_32 = V_ADD_CO_U32_e32 %5.sub0, %8, implicit-def $vcc, implicit $exec777 %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %8, implicit-def $vcc, implicit $vcc, implicit $exec778...779 780# GCN-LABEL: name: dpp64_add64_impdef781# GCN: %3:vgpr_32 = V_ADD_CO_U32_dpp %1.sub0, %0.sub0, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $exec782# GCN: %5:vgpr_32 = V_ADDC_U32_dpp %1.sub1, %0.sub1, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec783name: dpp64_add64_impdef784tracksRegLiveness: true785body: |786 bb.0:787 %0:vreg_64 = IMPLICIT_DEF788 %1:vreg_64 = IMPLICIT_DEF789 %2:vreg_64 = V_MOV_B64_DPP_PSEUDO %1:vreg_64, %0:vreg_64, 1, 15, 15, 1, implicit $exec790 %5:vgpr_32 = V_ADD_CO_U32_e32 %2.sub0, undef %4:vgpr_32, implicit-def $vcc, implicit $exec791 %6:vgpr_32 = V_ADDC_U32_e32 %2.sub1, undef %4, implicit-def $vcc, implicit $vcc, implicit $exec792...793 794# GCN-LABEL: name: dpp64_add64_undef795# GCN: %3:vgpr_32 = V_ADD_CO_U32_dpp undef %1.sub0:vreg_64, undef %2.sub0:vreg_64, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $exec796# GCN: %5:vgpr_32 = V_ADDC_U32_dpp undef %1.sub1:vreg_64, undef %2.sub1:vreg_64, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec797name: dpp64_add64_undef798tracksRegLiveness: true799body: |800 bb.0:801 %2:vreg_64 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64, undef %0:vreg_64, 1, 15, 15, 1, implicit $exec802 %5:vgpr_32 = V_ADD_CO_U32_e32 %2.sub0, undef %4:vgpr_32, implicit-def $vcc, implicit $exec803 %6:vgpr_32 = V_ADDC_U32_e32 %2.sub1, undef %4, implicit-def $vcc, implicit $vcc, implicit $exec804...805 806# GCN-LABEL: name: dpp64_add64_first_combined807# GCN: %8:vgpr_32 = V_MOV_B32_dpp undef %1.sub1:vreg_64, undef %2.sub1:vreg_64, 1, 15, 15, 1, implicit $exec808# GCN: %0:vreg_64 = REG_SEQUENCE undef %7:vgpr_32, %subreg.sub0, %8, %subreg.sub1809# GCN: %3:vgpr_32 = V_ADD_CO_U32_dpp undef %1.sub0:vreg_64, undef %2.sub0:vreg_64, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $exec810# GCN: %5:vgpr_32, dead %6:sreg_64_xexec = V_ADDC_U32_e64 1, %0.sub1, undef $vcc, 0, implicit $exec811name: dpp64_add64_first_combined812tracksRegLiveness: true813body: |814 bb.0:815 %2:vreg_64 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64, undef %0:vreg_64, 1, 15, 15, 1, implicit $exec816 %4:vgpr_32 = V_ADD_CO_U32_e32 %2.sub0, undef %3:vgpr_32, implicit-def $vcc, implicit $exec817 %5:vgpr_32, dead %6:sreg_64_xexec = V_ADDC_U32_e64 1, %2.sub1, undef $vcc, 0, implicit $exec818...819 820# GCN-LABEL: name: dont_combine_cndmask_with_src2821# GCN: %5:vgpr_32 = V_CNDMASK_B32_e64 0, %3, 0, %1, %4, implicit $exec822name: dont_combine_cndmask_with_src2823tracksRegLiveness: true824body: |825 bb.0:826 liveins: $vgpr0, $vgpr1827 %0:vgpr_32 = COPY $vgpr0828 %1:vgpr_32 = COPY $vgpr1829 %2:vgpr_32 = IMPLICIT_DEF830 831 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec832 %4:sreg_64_xexec = IMPLICIT_DEF833 %5:vgpr_32 = V_CNDMASK_B32_e64 0, %3, 0, %1, %4, implicit $exec834...835 836---837 838# Make sure flags aren't dropped839# GCN-LABEL: name: flags_add_f32_e64840# GCN: %4:vgpr_32 = nnan nofpexcept V_ADD_F32_dpp %2, 0, %1, 0, %0, 1, 15, 15, 1, implicit $mode, implicit $exec841name: flags_add_f32_e64842tracksRegLiveness: true843body: |844 bb.0:845 liveins: $vgpr0, $vgpr1846 847 %0:vgpr_32 = COPY $vgpr0848 %1:vgpr_32 = COPY $vgpr1849 %2:vgpr_32 = IMPLICIT_DEF850 851 %3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec852 %4:vgpr_32 = nofpexcept nnan V_ADD_F32_e64 0, %3, 0, %0, 0, 0, implicit $mode, implicit $exec853 S_ENDPGM 0, implicit %4854 855...856 857# GCN-LABEL: name: dont_combine_more_than_one_operand858# GCN: %3:vgpr_32 = V_MAX_F32_e64 0, %2, 0, %2, 0, 0, implicit $mode, implicit $exec859name: dont_combine_more_than_one_operand860tracksRegLiveness: true861body: |862 bb.0:863 liveins: $vgpr0, $vgpr1864 %0:vgpr_32 = COPY $vgpr0865 %1:vgpr_32 = COPY $vgpr1866 %2:vgpr_32 = V_MOV_B32_dpp %0, %1, 1, 15, 15, 1, implicit $exec867 %3:vgpr_32 = V_MAX_F32_e64 0, %2, 0, %2, 0, 0, implicit $mode, implicit $exec868...869 870# GCN-LABEL: name: dont_combine_more_than_one_operand_dpp_reg_sequence871# GCN: %5:vgpr_32 = V_ADD_CO_U32_e32 %4.sub0, %4.sub0, implicit-def $vcc, implicit $exec872# GCN: %6:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %4.sub1, implicit-def $vcc, implicit $vcc, implicit $exec873name: dont_combine_more_than_one_operand_dpp_reg_sequence874tracksRegLiveness: true875body: |876 bb.0:877 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3878 %0:vreg_64 = COPY $vgpr0_vgpr1879 %1:vreg_64 = COPY $vgpr2_vgpr3880 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec881 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec882 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1883 %5:vgpr_32 = V_ADD_CO_U32_e32 %4.sub0, %4.sub0, implicit-def $vcc, implicit $exec884 %6:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %4.sub1, implicit-def $vcc, implicit $vcc, implicit $exec885...886 887# execMayBeModifiedBeforeAnyUse used to assert if the queried888# V_MOV_B32_dpp was the last instruction in the block.889---890name: mov_dpp_last_block_inst891tracksRegLiveness: true892body: |893 ; GCN-LABEL: name: mov_dpp_last_block_inst894 ; GCN: bb.0:895 ; GCN-NEXT: successors: %bb.1(0x80000000)896 ; GCN-NEXT: liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8897 ; GCN-NEXT: {{ $}}898 ; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr8899 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF900 ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF901 ; GCN-NEXT: [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF902 ; GCN-NEXT: {{ $}}903 ; GCN-NEXT: bb.1:904 ; GCN-NEXT: successors: %bb.2(0x80000000)905 ; GCN-NEXT: {{ $}}906 ; GCN-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[DEF]], %bb.0, %5, %bb.2907 ; GCN-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[PHI]], 323, 15, 15, 0, implicit $exec908 ; GCN-NEXT: {{ $}}909 ; GCN-NEXT: bb.2:910 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)911 ; GCN-NEXT: {{ $}}912 ; GCN-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[DEF2]], implicit $exec913 ; GCN-NEXT: V_CMP_NE_U32_e32 1, [[V_CNDMASK_B32_e64_]], implicit-def $vcc, implicit $exec914 ; GCN-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc915 ; GCN-NEXT: S_BRANCH %bb.3916 ; GCN-NEXT: {{ $}}917 ; GCN-NEXT: bb.3:918 ; GCN-NEXT: S_ENDPGM 0919 bb.0:920 liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8921 922 %0:sgpr_32 = COPY $sgpr8923 %1:vgpr_32 = IMPLICIT_DEF924 %2:sreg_32 = IMPLICIT_DEF925 %3:sreg_64_xexec = IMPLICIT_DEF926 927 bb.1:928 %4:vgpr_32 = PHI %1, %bb.0, %5, %bb.2929 %5:vgpr_32 = V_MOV_B32_dpp %1, %4, 323, 15, 15, 0, implicit $exec930 931 bb.2:932 %6:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %3, implicit $exec933 V_CMP_NE_U32_e32 1, %6, implicit-def $vcc, implicit $exec934 S_CBRANCH_VCCNZ %bb.1, implicit $vcc935 S_BRANCH %bb.3936 937 bb.3:938 S_ENDPGM 0939 940...941