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1# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN2# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -mattr=-real-true16 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN3# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN4 5---6 7# GCN-LABEL: name: vop38# GCN: %6:vgpr_32, %7:sreg_32_xm0_xexec = V_SUBBREV_U32_e64_dpp %3, %0, %1, %5, 1, 1, 15, 15, 1, implicit $exec9# GCN: %8:vgpr_32 = V_CVT_PK_U8_F32_e64_dpp %3, 4, %0, 2, %2, 2, %1, 1, 1, 15, 15, 1, implicit $mode, implicit $exec10# GCN: %10:vgpr_32 = V_MED3_F32_e64 0, %9, 0, %0, 0, 12345678, 0, 0, implicit $mode, implicit $exec11# GCN: %12:vgpr_32 = V_MED3_F32_e64_dpp %3, 0, %1, 0, 2, 0, %7, 0, 0, 1, 15, 15, 1, implicit $mode, implicit $exec12name: vop313tracksRegLiveness: true14body: |15 bb.0:16 liveins: $vgpr0, $vgpr1, $vgpr217 18 %0:vgpr_32 = COPY $vgpr019 %1:vgpr_32 = COPY $vgpr120 %2:vgpr_32 = COPY $vgpr221 %3:vgpr_32 = IMPLICIT_DEF22 %4:vgpr_32 = V_MOV_B32_dpp %3, %0, 1, 15, 15, 1, implicit $exec23 24 %5:sreg_32_xm0_xexec = IMPLICIT_DEF25 %6:vgpr_32, %7:sreg_32_xm0_xexec = V_SUBBREV_U32_e64 %4, %1, %5, 1, implicit $exec26 27 %8:vgpr_32 = V_CVT_PK_U8_F32_e64 4, %4, 2, %2, 2, %1, 1, implicit $mode, implicit $exec28 29 ; should not be combined because src2 literal is illegal30 %9:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec31 %10:vgpr_32 = V_MED3_F32_e64 0, %9, 0, %0, 0, 12345678, 0, 0, implicit $mode, implicit $exec32 33 ; should not be combined on subtargets where src1 imm is illegal34 %11:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec35 %12:vgpr_32 = V_MED3_F32_e64 0, %11, 0, 2, 0, %7, 0, 0, implicit $mode, implicit $exec36...37---38 39# GCN-LABEL: name: vop3_sgpr_src140# GCN: %6:vgpr_32 = V_MED3_F32_e64_dpp %4, 0, %0, 0, %1, 0, %2, 0, 0, 1, 15, 15, 1, implicit $mode, implicit $exec41# GCN: %8:vgpr_32 = V_MED3_F32_e64_dpp %4, 0, %0, 0, %2, 0, %1, 0, 0, 1, 15, 15, 1, implicit $mode, implicit $exec42# GCN: %10:vgpr_32 = V_MED3_F32_e64_dpp %4, 0, %0, 0, %2, 0, %3, 0, 0, 1, 15, 15, 1, implicit $mode, implicit $exec43# GCN: %12:vgpr_32 = V_MED3_F32_e64_dpp %4, 0, %0, 0, 42, 0, %2, 0, 0, 1, 15, 15, 1, implicit $mode, implicit $exec44# GCN: %14:vgpr_32 = V_MED3_F32_e64 0, %13, 0, 4242, 0, %2, 0, 0, implicit $mode, implicit $exec45name: vop3_sgpr_src146tracksRegLiveness: true47body: |48 bb.0:49 liveins: $vgpr0, $vgpr1, $sgpr0, $sgpr150 51 %0:vgpr_32 = COPY $vgpr052 %1:vgpr_32 = COPY $vgpr153 %2:sgpr_32 = COPY $sgpr054 %3:sgpr_32 = COPY $sgpr155 %4:vgpr_32 = IMPLICIT_DEF56 57 ; should be combined because src2 allows sgpr58 %5:vgpr_32 = V_MOV_B32_dpp %4, %0, 1, 15, 15, 1, implicit $exec59 %6:vgpr_32 = V_MED3_F32_e64 0, %5, 0, %1, 0, %2, 0, 0, implicit $mode, implicit $exec60 61 ; should be combined only on subtargets that allow sgpr for src162 %7:vgpr_32 = V_MOV_B32_dpp %4, %0, 1, 15, 15, 1, implicit $exec63 %8:vgpr_32 = V_MED3_F32_e64 0, %7, 0, %2, 0, %1, 0, 0, implicit $mode, implicit $exec64 65 ; should be combined only on subtargets that allow sgpr for src166 %9:vgpr_32 = V_MOV_B32_dpp %4, %0, 1, 15, 15, 1, implicit $exec67 %10:vgpr_32 = V_MED3_F32_e64 0, %9, 0, %2, 0, %3, 0, 0, implicit $mode, implicit $exec68 69 ; should be combined only on subtargets that allow inlinable constants for src170 %11:vgpr_32 = V_MOV_B32_dpp %4, %0, 1, 15, 15, 1, implicit $exec71 %12:vgpr_32 = V_MED3_F32_e64 0, %11, 0, 42, 0, %2, 0, 0, implicit $mode, implicit $exec72 73 ; should not be combined when literal constants are used74 %13:vgpr_32 = V_MOV_B32_dpp %4, %0, 1, 15, 15, 1, implicit $exec75 %14:vgpr_32 = V_MED3_F32_e64 0, %13, 0, 4242, 0, %2, 0, 0, implicit $mode, implicit $exec76...77---78 79# Regression test for src_modifiers on base u16 opcode80# GCN-LABEL: name: vop3_u1681# GCN: %5:vgpr_32 = V_ADD_NC_U16_fake16_e64_dpp %3, 0, %1, 0, %3, 0, 0, 1, 15, 15, 1, implicit $exec82# GCN: %7:vgpr_32 = V_ADD_NC_U16_fake16_e64_dpp %3, 1, %5, 2, %5, 0, 0, 1, 15, 15, 1, implicit $exec83# GCN: %9:vgpr_32 = V_ADD_NC_U16_fake16_e64 4, %8, 8, %7, 0, 0, implicit $exec84name: vop3_u1685tracksRegLiveness: true86body: |87 bb.0:88 liveins: $vgpr0, $vgpr1, $vgpr289 90 %0:vgpr_32 = COPY $vgpr091 %1:vgpr_32 = COPY $vgpr192 %2:vgpr_32 = COPY $vgpr293 %3:vgpr_32 = IMPLICIT_DEF94 %4:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec95 %5:vgpr_32 = V_ADD_NC_U16_fake16_e64 0, %4, 0, %3, 0, 0, implicit $exec96 %6:vgpr_32 = V_MOV_B32_dpp %3, %5, 1, 15, 15, 1, implicit $exec97 %7:vgpr_32 = V_ADD_NC_U16_fake16_e64 1, %6, 2, %5, 0, 0, implicit $exec98 %8:vgpr_32 = V_MOV_B32_dpp %3, %7, 1, 15, 15, 1, implicit $exec99 %9:vgpr_32 = V_ADD_NC_U16_fake16_e64 4, %8, 8, %7, 0, 0, implicit $exec100...101 102name: vop3p103tracksRegLiveness: true104body: |105 bb.0:106 liveins: $vgpr0, $vgpr1, $vgpr2107 108 ; GCN-LABEL: name: vop3p109 ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2110 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0111 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1112 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2113 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF114 ; GCN: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec115 ; GCN: [[V_DOT2_F32_F16_:%[0-9]+]]:vgpr_32 = V_DOT2_F32_F16 0, [[V_MOV_B32_dpp]], 0, [[COPY]], 0, [[COPY2]], 0, 5, 0, 0, 0, implicit $mode, implicit $exec116 ; GCN: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec117 ; GCN: [[V_DOT2_F32_F16_1:%[0-9]+]]:vgpr_32 = V_DOT2_F32_F16 0, [[V_MOV_B32_dpp1]], 0, [[COPY]], 0, [[COPY2]], 0, 0, 4, 0, 0, implicit $mode, implicit $exec118 ; GCN: [[V_DOT2_F32_F16_dpp:%[0-9]+]]:vgpr_32 = V_DOT2_F32_F16_dpp [[DEF]], 10, [[COPY1]], 8, [[COPY]], 9, [[COPY2]], 1, 0, 7, 4, 5, 1, 15, 15, 1, implicit $mode, implicit $exec119 ; GCN: [[V_FMA_MIX_F32_dpp:%[0-9]+]]:vgpr_32 = V_FMA_MIX_F32_dpp [[DEF]], 8, [[COPY1]], 8, [[COPY]], 8, [[COPY2]], 1, 0, 7, 1, 15, 15, 1, implicit $mode, implicit $exec120 ; GCN: [[V_FMA_MIXLO_F16_dpp:%[0-9]+]]:vgpr_32 = V_FMA_MIXLO_F16_dpp [[DEF]], 8, [[COPY1]], 8, [[COPY]], 8, [[COPY2]], 0, [[COPY2]], 0, 7, 1, 15, 15, 1, implicit $mode, implicit $exec121 ; GCN: [[V_FMA_MIXHI_F16_dpp:%[0-9]+]]:vgpr_32 = V_FMA_MIXHI_F16_dpp [[DEF]], 8, [[COPY1]], 8, [[COPY]], 8, [[COPY2]], 1, [[COPY]], 0, 7, 1, 15, 15, 1, implicit $mode, implicit $exec122 %0:vgpr_32 = COPY $vgpr0123 %1:vgpr_32 = COPY $vgpr1124 %2:vgpr_32 = COPY $vgpr2125 %3:vgpr_32 = IMPLICIT_DEF126 127 ; this should not be combined because op_sel is not zero128 %4:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec129 %5:vgpr_32 = V_DOT2_F32_F16 0, %4, 0, %0, 0, %2, 0, 5, 0, 0, 0, implicit $mode, implicit $exec130 131 ; this should not be combined because op_sel_hi is not all set132 %6:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec133 %7:vgpr_32 = V_DOT2_F32_F16 0, %6, 0, %0, 0, %2, 0, 0, 4, 0, 0, implicit $mode, implicit $exec134 135 %8:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec136 %9:vgpr_32 = V_DOT2_F32_F16 10, %8, 8, %0, 9, %2, 1, 0, 7, 4, 5, implicit $mode, implicit $exec137 138 %10:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec139 %11:vgpr_32 = V_FMA_MIX_F32 8, %10, 8, %0, 8, %2, 1, 0, 7, implicit $mode, implicit $exec140 141 %12:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec142 %13:vgpr_32 = V_FMA_MIXLO_F16 8, %12, 8, %0, 8, %2, 0, %2, 0, 7, implicit $mode, implicit $exec143 144 %14:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec145 %15:vgpr_32 = V_FMA_MIXHI_F16 8, %14, 8, %0, 8, %2, 1, %0, 0, 7, implicit $mode, implicit $exec146 147...148 149# GCN-LABEL: name: fmac_e64150# GCN: %5:vgpr_32 = V_FMAC_F32_e64_dpp %3, 2, %0, 2, %1, 2, %2, 1, 2, 1, 15, 15, 1, implicit $mode, implicit $exec151name: fmac_e64152tracksRegLiveness: true153body: |154 bb.0:155 liveins: $vgpr0, $vgpr1, $vgpr2156 157 %0:vgpr_32 = COPY $vgpr0158 %1:vgpr_32 = COPY $vgpr1159 %2:vgpr_32 = COPY $vgpr2160 %3:vgpr_32 = IMPLICIT_DEF161 %4:vgpr_32 = V_MOV_B32_dpp %3, %0, 1, 15, 15, 1, implicit $exec162 %6:vgpr_32 = V_FMAC_F32_e64 2, %4, 2, %1, 2, %2, 1, 2, implicit $mode, implicit $exec163...164 165# when the DPP source isn't a src0 operand the operation should be commuted if possible166# GCN-LABEL: name: dpp_commute_shrink167# GCN: %4:vgpr_32 = V_MUL_U32_U24_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec168# GCN: %7:vgpr_32 = V_AND_B32_dpp %1, %0, %1, 1, 15, 14, 0, implicit $exec169# GCN: %10:vgpr_32 = V_MAX_I32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec170# GCN: %13:vgpr_32 = V_MIN_I32_dpp %1, %0, %1, 1, 15, 14, 0, implicit $exec171# GCN: %16:vgpr_32 = V_SUBREV_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec172name: dpp_commute_shrink173tracksRegLiveness: true174body: |175 bb.0:176 liveins: $vgpr0, $vgpr1177 178 %0:vgpr_32 = COPY $vgpr0179 %1:vgpr_32 = COPY $vgpr1180 181 %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec182 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec183 %4:vgpr_32 = V_MUL_U32_U24_e64 %1, %3, 0, implicit $exec184 185 %5:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec186 %6:vgpr_32 = V_MOV_B32_dpp %5, %0, 1, 15, 14, 0, implicit $exec187 %7:vgpr_32 = V_AND_B32_e64 %1, %6, implicit $exec188 189 %8:vgpr_32 = V_MOV_B32_e32 -2147483648, implicit $exec190 %9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 14, 15, 0, implicit $exec191 %10:vgpr_32 = V_MAX_I32_e64 %1, %9, implicit $exec192 193 %11:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec194 %12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 15, 14, 0, implicit $exec195 %13:vgpr_32 = V_MIN_I32_e64 %1, %12, implicit $exec196 197 %14:vgpr_32 = V_MOV_B32_e32 0, implicit $exec198 %15:vgpr_32 = V_MOV_B32_dpp %14, %0, 1, 14, 15, 0, implicit $exec199 %16:vgpr_32 = V_SUB_U32_e64 %1, %15, 0, implicit $exec200 201...202 203# do not combine, dpp arg used twice204# GCN-LABEL: name: dpp_arg_twice205# GCN: %4:vgpr_32 = V_FMA_F32_e64 1, %1, 2, %3, 2, %3, 1, 2, implicit $mode, implicit $exec206# GCN: %6:vgpr_32 = V_FMA_F32_e64 2, %5, 2, %1, 2, %5, 1, 2, implicit $mode, implicit $exec207# GCN: %8:vgpr_32 = V_FMA_F32_e64 2, %7, 2, %7, 2, %1, 1, 2, implicit $mode, implicit $exec208name: dpp_arg_twice209tracksRegLiveness: true210body: |211 bb.0:212 liveins: $vgpr0, $vgpr1213 214 %0:vgpr_32 = COPY $vgpr0215 %1:vgpr_32 = COPY $vgpr1216 %2:vgpr_32 = IMPLICIT_DEF217 218 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec219 %4:vgpr_32 = V_FMA_F32_e64 1, %1, 2, %3, 2, %3, 1, 2, implicit $mode, implicit $exec220 221 %5:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec222 %6:vgpr_32 = V_FMA_F32_e64 2, %5, 2, %1, 2, %5, 1, 2, implicit $mode, implicit $exec223 224 %7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec225 %8:vgpr_32 = V_FMA_F32_e64 2, %7, 2, %7, 2, %1, 1, 2, implicit $mode, implicit $exec226 227...228 229# when the dpp source isn't a src0 operand the operation should be commuted if possible230# GCN-LABEL: name: dpp_commute_e64231# GCN: %4:vgpr_32 = V_MUL_U32_U24_e64_dpp %1, %0, %1, 1, 1, 14, 15, 0, implicit $exec232# GCN: %7:vgpr_32 = V_FMA_F32_e64_dpp %5, 2, %0, 1, %1, 2, %1, 1, 2, 1, 15, 15, 1, implicit $mode, implicit $exec233# GCN: %10:vgpr_32 = V_SUBREV_U32_e64_dpp %1, %0, %1, 1, 1, 14, 15, 0, implicit $exec234# GCN: %13:vgpr_32, %14:sreg_32_xm0_xexec = V_ADD_CO_U32_e64_dpp %1, %0, %1, 0, 1, 14, 15, 0, implicit $exec235# GCN: %17:vgpr_32, %18:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 5, %16, 0, implicit $exec236name: dpp_commute_e64237tracksRegLiveness: true238body: |239 bb.0:240 liveins: $vgpr0, $vgpr1241 242 %0:vgpr_32 = COPY $vgpr0243 %1:vgpr_32 = COPY $vgpr1244 245 %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec246 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec247 %4:vgpr_32 = V_MUL_U32_U24_e64 %1, %3, 1, implicit $exec248 249 %5:vgpr_32 = IMPLICIT_DEF250 %6:vgpr_32 = V_MOV_B32_dpp %5, %0, 1, 15, 15, 1, implicit $exec251 %7:vgpr_32 = V_FMA_F32_e64 1, %1, 2, %6, 2, %1, 1, 2, implicit $mode, implicit $exec252 253 %8:vgpr_32 = V_MOV_B32_e32 0, implicit $exec254 %9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 14, 15, 0, implicit $exec255 %10:vgpr_32 = V_SUB_U32_e64 %1, %9, 1, implicit $exec256 257 %11:vgpr_32 = V_MOV_B32_e32 0, implicit $exec258 %12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 14, 15, 0, implicit $exec259 %13:vgpr_32, %14:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %1, %12, 0, implicit $exec260 261 ; this cannot be combined because immediate as src0 isn't commutable262 %15:vgpr_32 = V_MOV_B32_e32 0, implicit $exec263 %16:vgpr_32 = V_MOV_B32_dpp %15, %0, 1, 14, 15, 0, implicit $exec264 %17:vgpr_32, %18:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 5, %16, 0, implicit $exec265...266 267---268 269# check for floating point modifiers270# GCN-LABEL: name: add_f32_e64271# GCN: %4:vgpr_32 = V_ADD_F32_e64_dpp %2, 0, %1, 0, %0, 0, 1, 1, 15, 15, 1, implicit $mode, implicit $exec272# GCN: %6:vgpr_32 = V_ADD_F32_dpp %2, 0, %1, 0, %0, 1, 15, 15, 1, implicit $mode, implicit $exec273# GCN: %8:vgpr_32 = V_ADD_F32_dpp %2, 1, %1, 2, %0, 1, 15, 15, 1, implicit $mode, implicit $exec274# GCN: %10:vgpr_32 = V_ADD_F32_e64_dpp %2, 4, %1, 8, %0, 0, 0, 1, 15, 15, 1, implicit $mode, implicit $exec275 276name: add_f32_e64277tracksRegLiveness: true278body: |279 bb.0:280 liveins: $vgpr0, $vgpr1281 282 %0:vgpr_32 = COPY $vgpr0283 %1:vgpr_32 = COPY $vgpr1284 %2:vgpr_32 = IMPLICIT_DEF285 286 ; this should be combined as e64287 %3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec288 %4:vgpr_32 = V_ADD_F32_e64 0, %3, 0, %0, 0, 1, implicit $mode, implicit $exec289 290 ; this should be combined and shrunk as all modifiers are default291 %5:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec292 %6:vgpr_32 = V_ADD_F32_e64 0, %5, 0, %0, 0, 0, implicit $mode, implicit $exec293 294 ; this should be combined and shrunk as modifiers other than abs|neg are default295 %7:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec296 %8:vgpr_32 = V_ADD_F32_e64 1, %7, 2, %0, 0, 0, implicit $mode, implicit $exec297 298 ; this should be combined as e64299 %9:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec300 %10:vgpr_32 = V_ADD_F32_e64 4, %9, 8, %0, 0, 0, implicit $mode, implicit $exec301...302 303# check for e64 modifiers304# GCN-LABEL: name: add_u32_e64305# GCN: %4:vgpr_32 = V_ADD_U32_dpp %2, %0, %1, 1, 15, 15, 1, implicit $exec306# GCN: %6:vgpr_32 = V_ADD_U32_e64_dpp %2, %0, %1, 1, 1, 15, 15, 1, implicit $exec307 308name: add_u32_e64309tracksRegLiveness: true310body: |311 bb.0:312 liveins: $vgpr0, $vgpr1313 314 %0:vgpr_32 = COPY $vgpr0315 %1:vgpr_32 = COPY $vgpr1316 %2:vgpr_32 = IMPLICIT_DEF317 318 ; this should be combined and shrunk as all modifiers are default319 %3:vgpr_32 = V_MOV_B32_dpp undef %2, %0, 1, 15, 15, 1, implicit $exec320 %4:vgpr_32 = V_ADD_U32_e64 %3, %1, 0, implicit $exec321 322 ; this should be combined as _e64323 %5:vgpr_32 = V_MOV_B32_dpp undef %2, %0, 1, 15, 15, 1, implicit $exec324 %6:vgpr_32 = V_ADD_U32_e64 %5, %1, 1, implicit $exec325...326 327# tests on sequences of dpp consumers328# GCN-LABEL: name: dpp_seq329# GCN: %4:vgpr_32 = V_ADD_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec330# GCN: %5:vgpr_32 = V_SUBREV_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec331# GCN: %6:vgpr_32 = V_OR_B32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec332# broken sequence:333# GCN: %7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec334 335name: dpp_seq336tracksRegLiveness: true337body: |338 bb.0:339 liveins: $vgpr0, $vgpr1340 %0:vgpr_32 = COPY $vgpr0341 %1:vgpr_32 = COPY $vgpr1342 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec343 344 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec345 %4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec346 %5:vgpr_32 = V_SUB_U32_e32 %1, %3, implicit $exec347 %6:vgpr_32 = V_OR_B32_e32 %3, %1, implicit $exec348 349 %7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec350 %8:vgpr_32 = V_ADD_U32_e32 %7, %1, implicit $exec351 ; this breaks the sequence352 %9:vgpr_32 = V_SUB_U32_e32 5, %7, implicit $exec353...354 355# tests on sequences of dpp consumers followed by control flow356# GCN-LABEL: name: dpp_seq_cf357# GCN: %4:vgpr_32 = V_ADD_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec358# GCN: %5:vgpr_32 = V_SUBREV_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec359# GCN: %6:vgpr_32 = V_OR_B32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec360 361name: dpp_seq_cf362tracksRegLiveness: true363body: |364 bb.0:365 successors: %bb.1, %bb.2366 liveins: $vgpr0, $vgpr1367 %0:vgpr_32 = COPY $vgpr0368 %1:vgpr_32 = COPY $vgpr1369 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec370 371 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec372 %4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec373 %5:vgpr_32 = V_SUB_U32_e32 %1, %3, implicit $exec374 %6:vgpr_32 = V_OR_B32_e32 %3, %1, implicit $exec375 376 %7:sreg_32 = V_CMP_EQ_U32_e64 %5, %6, implicit $exec377 %8:sreg_32 = SI_IF %7, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec378 S_BRANCH %bb.1379 380 bb.1:381 successors: %bb.2382 383 bb.2:384 SI_END_CF %8, implicit-def dead $exec, implicit-def dead $scc, implicit $exec385...386 387# GCN-LABEL: name: old_in_diff_bb388# GCN: %4:vgpr_32 = V_ADD_U32_dpp %0, %1, %0, 1, 1, 1, 0, implicit $exec389 390name: old_in_diff_bb391tracksRegLiveness: true392body: |393 bb.0:394 successors: %bb.1395 liveins: $vgpr0, $vgpr1396 397 %0:vgpr_32 = COPY $vgpr0398 %1:vgpr_32 = COPY $vgpr1399 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec400 S_BRANCH %bb.1401 402 bb.1:403 %3:vgpr_32 = V_MOV_B32_dpp %2, %1, 1, 1, 1, 0, implicit $exec404 %4:vgpr_32 = V_ADD_U32_e32 %3, %0, implicit $exec405...406 407# old reg def is in diff BB but bound_ctrl:1 - can combine408# GCN-LABEL: name: old_in_diff_bb_bctrl_zero409# GCN: %4:vgpr_32 = V_ADD_U32_dpp {{%[0-9]}}, %0, %1, 1, 15, 15, 1, implicit $exec410 411name: old_in_diff_bb_bctrl_zero412tracksRegLiveness: true413body: |414 bb.0:415 successors: %bb.1416 liveins: $vgpr0, $vgpr1417 418 %0:vgpr_32 = COPY $vgpr0419 %1:vgpr_32 = COPY $vgpr1420 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec421 S_BRANCH %bb.1422 423 bb.1:424 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec425 %4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec426...427 428# EXEC mask changed between def and use - cannot combine429# GCN-LABEL: name: exec_changed430# GCN: %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec431 432name: exec_changed433tracksRegLiveness: true434body: |435 bb.0:436 liveins: $vgpr0, $vgpr1437 438 %0:vgpr_32 = COPY $vgpr0439 %1:vgpr_32 = COPY $vgpr1440 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec441 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec442 %4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec443 %5:sreg_64 = COPY $exec, implicit-def $exec444 %6:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec445...446 447# test if $old definition is correctly tracked through subreg manipulation pseudos448 449# GCN-LABEL: name: mul_old_subreg450# GCN: %7:vgpr_32 = V_MUL_I32_I24_dpp %0.sub1, %1, %0.sub1, 1, 1, 1, 0, implicit $exec451 452name: mul_old_subreg453tracksRegLiveness: true454body: |455 bb.0:456 liveins: $vgpr0, $vgpr1457 458 %0:vreg_64 = COPY $vgpr0459 %1:vgpr_32 = COPY $vgpr1460 %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec461 %3:vgpr_32 = V_MOV_B32_e32 42, implicit $exec462 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1463 %5:vreg_64 = INSERT_SUBREG %4, %1, %subreg.sub1 ; %5.sub0 is taken from %4464 %6:vgpr_32 = V_MOV_B32_dpp %5.sub0, %1, 1, 1, 1, 0, implicit $exec465 %7:vgpr_32 = V_MUL_I32_I24_e32 %6, %0.sub1, implicit $exec466...467 468# GCN-LABEL: name: add_old_subreg469# GCN: %5:vgpr_32 = V_ADD_U32_dpp %0.sub1, %1, %0.sub1, 1, 1, 1, 0, implicit $exec470 471name: add_old_subreg472tracksRegLiveness: true473body: |474 bb.0:475 liveins: $vgpr0, $vgpr1476 477 %0:vreg_64 = COPY $vgpr0478 %1:vgpr_32 = COPY $vgpr1479 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec480 %3:vreg_64 = INSERT_SUBREG %0, %2, %subreg.sub1 ; %3.sub1 is inserted481 %4:vgpr_32 = V_MOV_B32_dpp %3.sub1, %1, 1, 1, 1, 0, implicit $exec482 %5:vgpr_32 = V_ADD_U32_e32 %4, %0.sub1, implicit $exec483...484 485# GCN-LABEL: name: add_old_subreg_undef486# GCN: %5:vgpr_32 = V_ADD_U32_dpp undef %3.sub1, %1, %0.sub1, 1, 15, 15, 1, implicit $exec487 488name: add_old_subreg_undef489tracksRegLiveness: true490body: |491 bb.0:492 liveins: $vgpr0, $vgpr1493 494 %0:vreg_64 = COPY $vgpr0495 %1:vgpr_32 = COPY $vgpr1496 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec497 %3:vreg_64 = REG_SEQUENCE %2, %subreg.sub0 ; %3.sub1 is undef498 %4:vgpr_32 = V_MOV_B32_dpp %3.sub1, %1, 1, 15, 15, 1, implicit $exec499 %5:vgpr_32 = V_ADD_U32_e32 %4, %0.sub1, implicit $exec500...501 502# Test instruction which does not have modifiers in VOP1 form but does in DPP form.503# GCN-LABEL: name: dpp_vop1504# GCN: %3:vgpr_32 = V_CEIL_F32_dpp %0, 0, undef %2:vgpr_32, 1, 15, 15, 1, implicit $mode, implicit $exec505name: dpp_vop1506tracksRegLiveness: true507body: |508 bb.0:509 %1:vgpr_32 = IMPLICIT_DEF510 %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec511 %3:vgpr_32 = V_CEIL_F32_e32 %2, implicit $mode, implicit $exec512...513 514# Test instruction which does not have modifiers in VOP2 form but does in DPP form.515# GCN-LABEL: name: dpp_min516# GCN: %3:vgpr_32 = V_MIN_F32_dpp %0, 0, undef %2:vgpr_32, 0, undef %4:vgpr_32, 1, 15, 15, 1, implicit $mode, implicit $exec517name: dpp_min518tracksRegLiveness: true519body: |520 bb.0:521 %1:vgpr_32 = IMPLICIT_DEF522 %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec523 %4:vgpr_32 = V_MIN_F32_e32 %2, undef %3:vgpr_32, implicit $mode, implicit $exec524...525 526# Test an undef old operand527# GCN-LABEL: name: dpp_undef_old528# GCN: %3:vgpr_32 = V_CEIL_F32_dpp undef %1:vgpr_32, 0, undef %2:vgpr_32, 1, 15, 15, 1, implicit $mode, implicit $exec529name: dpp_undef_old530tracksRegLiveness: true531body: |532 bb.0:533 %2:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec534 %3:vgpr_32 = V_CEIL_F32_e32 %2, implicit $mode, implicit $exec535...536 537# Do not combine a dpp mov which writes a physreg.538# GCN-LABEL: name: phys_dpp_mov_dst539# GCN: $vgpr0 = V_MOV_B32_dpp undef %0:vgpr_32, undef %1:vgpr_32, 1, 15, 15, 1, implicit $exec540# GCN: %2:vgpr_32 = V_CEIL_F32_e32 $vgpr0, implicit $mode, implicit $exec541name: phys_dpp_mov_dst542tracksRegLiveness: true543body: |544 bb.0:545 $vgpr0 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec546 %2:vgpr_32 = V_CEIL_F32_e32 $vgpr0, implicit $mode, implicit $exec547...548 549# Do not combine a dpp mov which reads a physreg.550# GCN-LABEL: name: phys_dpp_mov_old_src551# GCN: %0:vgpr_32 = V_MOV_B32_dpp undef $vgpr0, undef %1:vgpr_32, 1, 15, 15, 1, implicit $exec552# GCN: %2:vgpr_32 = V_CEIL_F32_e32 %0, implicit $mode, implicit $exec553name: phys_dpp_mov_old_src554tracksRegLiveness: true555body: |556 bb.0:557 %1:vgpr_32 = V_MOV_B32_dpp undef $vgpr0, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec558 %2:vgpr_32 = V_CEIL_F32_e32 %1, implicit $mode, implicit $exec559...560 561# Do not combine a dpp mov which reads a physreg.562# GCN-LABEL: name: phys_dpp_mov_src563# GCN: %0:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef $vgpr0, 1, 15, 15, 1, implicit $exec564# GCN: %2:vgpr_32 = V_CEIL_F32_e32 %0, implicit $mode, implicit $exec565name: phys_dpp_mov_src566tracksRegLiveness: true567body: |568 bb.0:569 %1:vgpr_32 = V_MOV_B32_dpp undef %0:vgpr_32, undef $vgpr0, 1, 15, 15, 1, implicit $exec570 %2:vgpr_32 = V_CEIL_F32_e32 %1, implicit $mode, implicit $exec571...572 573# GCN-LABEL: name: dpp_reg_sequence_both_combined574# GCN: %0:vreg_64 = COPY $vgpr0_vgpr1575# GCN: %1:vreg_64 = COPY $vgpr2_vgpr3576# GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec577# GCN: %9:vgpr_32 = IMPLICIT_DEF578# GCN: %8:vgpr_32 = IMPLICIT_DEF579# GCN: %6:vgpr_32 = V_ADD_U32_dpp %9, %1.sub0, %2, 1, 15, 15, 1, implicit $exec580# GCN: %7:vgpr_32 = V_ADDC_U32_dpp %8, %1.sub1, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec581name: dpp_reg_sequence_both_combined582tracksRegLiveness: true583body: |584 bb.0:585 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo586 587 %0:vreg_64 = COPY $vgpr0_vgpr1588 %1:vreg_64 = COPY $vgpr2_vgpr3589 %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec590 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec591 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec592 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1593 %6:vgpr_32 = V_ADD_U32_e32 %4.sub0, %5, implicit $exec594 %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec595...596 597# GCN-LABEL: name: dpp_reg_sequence_first_combined598# GCN: %0:vreg_64 = COPY $vgpr0_vgpr1599# GCN: %1:vreg_64 = COPY $vgpr2_vgpr3600# GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec601# GCN: %8:vgpr_32 = IMPLICIT_DEF602# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec603# GCN: %5:vreg_64 = REG_SEQUENCE undef %3:vgpr_32, %subreg.sub0, %4, %subreg.sub1604# GCN: %6:vgpr_32 = V_ADD_U32_dpp %8, %1.sub0, %2, 1, 15, 15, 1, implicit $exec605# GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec606name: dpp_reg_sequence_first_combined607tracksRegLiveness: true608body: |609 bb.0:610 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo611 612 %0:vreg_64 = COPY $vgpr0_vgpr1613 %1:vreg_64 = COPY $vgpr2_vgpr3614 %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec615 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec616 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec617 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1618 %6:vgpr_32 = V_ADD_U32_e32 %4.sub0, %5, implicit $exec619 %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec620...621 622# GCN-LABEL: name: dpp_reg_sequence_second_combined623# GCN: %0:vreg_64 = COPY $vgpr0_vgpr1624# GCN: %1:vreg_64 = COPY $vgpr2_vgpr3625# GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec626# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec627# GCN: %8:vgpr_32 = IMPLICIT_DEF628# GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, undef %4:vgpr_32, %subreg.sub1629# GCN: %6:vgpr_32 = V_ADD_U32_e32 %5.sub0, %2, implicit $exec630# GCN: %7:vgpr_32 = V_ADDC_U32_dpp %8, %1.sub1, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec631name: dpp_reg_sequence_second_combined632tracksRegLiveness: true633body: |634 bb.0:635 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo636 637 %0:vreg_64 = COPY $vgpr0_vgpr1638 %1:vreg_64 = COPY $vgpr2_vgpr3639 %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec640 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec641 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec642 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1643 %6:vgpr_32 = V_ADD_U32_e32 %4.sub0, %5, implicit $exec644 %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec645...646 647# GCN-LABEL: name: dpp_reg_sequence_none_combined648# GCN: %0:vreg_64 = COPY $vgpr0_vgpr1649# GCN: %1:vreg_64 = COPY $vgpr2_vgpr3650# GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec651# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec652# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec653# GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1654# GCN: %6:vgpr_32 = V_ADD_U32_e32 %5.sub0, %2, implicit $exec655# GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec656name: dpp_reg_sequence_none_combined657tracksRegLiveness: true658body: |659 bb.0:660 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo661 662 %0:vreg_64 = COPY $vgpr0_vgpr1663 %1:vreg_64 = COPY $vgpr2_vgpr3664 %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec665 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec666 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec667 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1668 %6:vgpr_32 = V_ADD_U32_e32 %4.sub0, %5, implicit $exec669 %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec670...671 672# GCN-LABEL: name: dpp_reg_sequence_exec_changed673# GCN: %0:vreg_64 = COPY $vgpr0_vgpr1674# GCN: %1:vreg_64 = COPY $vgpr2_vgpr3675# GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec676# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec677# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec678# GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1679# GCN: S_BRANCH %bb.1680# GCN: bb.1:681# GCN: %6:vgpr_32 = V_ADD_U32_e32 %5.sub0, %2, implicit $exec682# GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec683name: dpp_reg_sequence_exec_changed684tracksRegLiveness: true685body: |686 bb.0:687 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo688 689 %0:vreg_64 = COPY $vgpr0_vgpr1690 %1:vreg_64 = COPY $vgpr2_vgpr3691 %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec692 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec693 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec694 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1695 S_BRANCH %bb.1696 697 bb.1:698 liveins: $vcc_lo699 %6:vgpr_32 = V_ADD_U32_e32 %4.sub0, %5, implicit $exec700 %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec701...702 703# GCN-LABEL: name: dpp_reg_sequence_subreg704# GCN: %0:vreg_64 = COPY $vgpr0_vgpr1705# GCN: %1:vreg_64 = COPY $vgpr2_vgpr3706# GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec707# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec708# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec709# GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1710# GCN: %6:vreg_64 = REG_SEQUENCE %5.sub0, %subreg.sub0, %5.sub1, %subreg.sub1711# GCN: %7:vgpr_32 = V_ADD_U32_e32 %6.sub0, %2, implicit $exec712# GCN: %8:vgpr_32 = V_ADDC_U32_e32 %6.sub1, %2, implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec713name: dpp_reg_sequence_subreg714tracksRegLiveness: true715body: |716 bb.0:717 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo718 719 %0:vreg_64 = COPY $vgpr0_vgpr1720 %1:vreg_64 = COPY $vgpr2_vgpr3721 %8:vgpr_32 = V_MOV_B32_e32 5, implicit $exec722 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec723 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec724 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1725 %5:vreg_64 = REG_SEQUENCE %4.sub0, %subreg.sub0, %4.sub1, %subreg.sub1726 %6:vgpr_32 = V_ADD_U32_e32 %5.sub0, %8, implicit $exec727 %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %8, implicit-def $vcc, implicit $vcc, implicit $exec728...729 730# GCN-LABEL: name: dpp_reg_sequence_src2_reject731#GCN: %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec732#GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec733#GCN: %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1734#GCN: %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec735#GCN: %6:vgpr_32 = V_FMA_F32_e64 2, %4.sub0, 2, %5, 2, %4.sub0, 1, 2, implicit $mode, implicit $exec736#GCN: %7:vgpr_32 = V_FMA_F32_e64 2, %4.sub0, 2, %5, 2, %4.sub1, 1, 2, implicit $mode, implicit $exec737name: dpp_reg_sequence_src2_reject738tracksRegLiveness: true739body: |740 bb.0:741 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3742 743 %0:vreg_64 = COPY $vgpr0_vgpr1744 %1:vreg_64 = COPY $vgpr2_vgpr3745 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec746 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec747 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1748 %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec749 ; use of dpp arg as src2, reject750 %6:vgpr_32 = V_FMA_F32_e64 2, %4.sub0, 2, %5, 2, %4.sub0, 1, 2, implicit $mode, implicit $exec751 ; cannot commute src0 and src2, and %4.sub0 already rejected, reject752 %7:vgpr_32 = V_FMA_F32_e64 2, %4.sub0, 2, %5, 2, %4.sub1, 1, 2, implicit $mode, implicit $exec753...754 755# GCN-LABEL: name: dpp_reg_sequence_src2756#GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec757#GCN: %4:vreg_64 = REG_SEQUENCE undef %2:vgpr_32, %subreg.sub0, %3, %subreg.sub1758#GCN: %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec759#GCN: %6:vgpr_32 = V_FMA_F32_e64_dpp %8, 2, %1.sub0, 2, %5, 2, %4.sub1, 1, 2, 1, 15, 15, 1, implicit $mode, implicit $exec760name: dpp_reg_sequence_src2761tracksRegLiveness: true762body: |763 bb.0:764 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3765 766 %0:vreg_64 = COPY $vgpr0_vgpr1767 %1:vreg_64 = COPY $vgpr2_vgpr3768 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec769 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec770 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1771 %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec772 %6:vgpr_32 = V_FMA_F32_e64 2, %4.sub0, 2, %5, 2, %4.sub1, 1, 2, implicit $mode, implicit $exec773...774 775# GCN-LABEL: name: dpp64_add64_impdef776# GCN: %3:vgpr_32 = V_ADD_U32_dpp %1.sub0, %0.sub0, undef %4:vgpr_32, 1, 15, 15, 1, implicit $exec777# GCN: %5:vgpr_32 = V_ADDC_U32_dpp %1.sub1, %0.sub1, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec778name: dpp64_add64_impdef779tracksRegLiveness: true780body: |781 bb.0:782 liveins: $vcc_lo783 %0:vreg_64 = IMPLICIT_DEF784 %1:vreg_64 = IMPLICIT_DEF785 %2:vreg_64 = V_MOV_B64_DPP_PSEUDO %1:vreg_64, %0:vreg_64, 1, 15, 15, 1, implicit $exec786 %5:vgpr_32 = V_ADD_U32_e32 %2.sub0, undef %4:vgpr_32, implicit $exec787 %6:vgpr_32 = V_ADDC_U32_e32 %2.sub1, undef %4, implicit-def $vcc, implicit $vcc, implicit $exec788...789 790# GCN-LABEL: name: dpp64_add64_undef791# GCN: %3:vgpr_32 = V_ADD_U32_dpp undef %1.sub0:vreg_64, undef %2.sub0:vreg_64, undef %4:vgpr_32, 1, 15, 15, 1, implicit $exec792# GCN: %5:vgpr_32 = V_ADDC_U32_dpp undef %1.sub1:vreg_64, undef %2.sub1:vreg_64, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec793name: dpp64_add64_undef794tracksRegLiveness: true795body: |796 bb.0:797 liveins: $vcc_lo798 %2:vreg_64 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64, undef %0:vreg_64, 1, 15, 15, 1, implicit $exec799 %5:vgpr_32 = V_ADD_U32_e32 %2.sub0, undef %4:vgpr_32, implicit $exec800 %6:vgpr_32 = V_ADDC_U32_e32 %2.sub1, undef %4, implicit-def $vcc, implicit $vcc, implicit $exec801...802 803 804# GCN-LABEL: name: cndmask_with_src2805# GCN: %5:vgpr_32 = V_CNDMASK_B32_e64 0, %3, 0, %1, %4, implicit $exec806# GCN: %8:vgpr_32 = V_CNDMASK_B32_e64_dpp %2, 4, %1, 0, %1, %7, 1, 15, 15, 1, implicit $exec807name: cndmask_with_src2808tracksRegLiveness: true809body: |810 bb.0:811 liveins: $vgpr0, $vgpr1812 %0:vgpr_32 = COPY $vgpr0813 %1:vgpr_32 = COPY $vgpr1814 %2:vgpr_32 = IMPLICIT_DEF815 816 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec817 %4:sreg_32_xm0_xexec = IMPLICIT_DEF818 %5:vgpr_32 = V_CNDMASK_B32_e64 0, %3, 0, %1, %4, implicit $exec819 820 ; src2 is legal for _e64821 %6:vgpr_32 = V_MOV_B32_dpp %2, %1, 1, 15, 15, 1, implicit $exec822 %7:sreg_32_xm0_xexec = IMPLICIT_DEF823 %8:vgpr_32 = V_CNDMASK_B32_e64 4, %6, 0, %1, %7, implicit $exec824...825 826---827 828# Make sure flags aren't dropped829# GCN-LABEL: name: flags_add_f32_e64830# GCN: %4:vgpr_32 = nnan nofpexcept V_ADD_F32_dpp %2, 0, %1, 0, %0, 1, 15, 15, 1, implicit $mode, implicit $exec831name: flags_add_f32_e64832tracksRegLiveness: true833body: |834 bb.0:835 liveins: $vgpr0, $vgpr1836 837 %0:vgpr_32 = COPY $vgpr0838 %1:vgpr_32 = COPY $vgpr1839 %2:vgpr_32 = IMPLICIT_DEF840 841 %3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec842 %4:vgpr_32 = nofpexcept nnan V_ADD_F32_e64 0, %3, 0, %0, 0, 0, implicit $mode, implicit $exec843 S_ENDPGM 0, implicit %4844 845...846 847# GCN-LABEL: name: dont_combine_more_than_one_operand848# GCN: %3:vgpr_32 = V_MAX_F32_e64 0, %2, 0, %2, 0, 0, implicit $mode, implicit $exec849name: dont_combine_more_than_one_operand850tracksRegLiveness: true851body: |852 bb.0:853 liveins: $vgpr0, $vgpr1854 %0:vgpr_32 = COPY $vgpr0855 %1:vgpr_32 = COPY $vgpr1856 %2:vgpr_32 = V_MOV_B32_dpp %0, %1, 1, 15, 15, 1, implicit $exec857 %3:vgpr_32 = V_MAX_F32_e64 0, %2, 0, %2, 0, 0, implicit $mode, implicit $exec858...859 860# GCN-LABEL: name: dont_combine_more_than_one_operand_dpp_reg_sequence861# GCN: %5:vgpr_32 = V_ADD_U32_e32 %4.sub0, %4.sub0, implicit $exec862# GCN: %6:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %4.sub1, implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec863name: dont_combine_more_than_one_operand_dpp_reg_sequence864tracksRegLiveness: true865body: |866 bb.0:867 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo868 %0:vreg_64 = COPY $vgpr0_vgpr1869 %1:vreg_64 = COPY $vgpr2_vgpr3870 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec871 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec872 %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1873 %5:vgpr_32 = V_ADD_U32_e32 %4.sub0, %4.sub0, implicit $exec874 %6:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %4.sub1, implicit-def $vcc, implicit $vcc, implicit $exec875...876 877# Check op_sel is all 0s when combining878# GCN-LABEL: name: opsel_vop3879# GCN: %4:vgpr_32 = V_ADD_I16_fake16_e64_dpp %2, 0, %0, 0, %1, 0, 0, 1, 15, 15, 1, implicit $exec880# GCN: %6:vgpr_32 = V_ADD_I16_fake16_e64 4, %5, 0, %1, 0, 0, implicit $exec881# GCN: %8:vgpr_32 = V_ADD_I16_fake16_e64 0, %7, 4, %1, 0, 0, implicit $exec882# GCN: %10:vgpr_32 = V_ADD_I16_fake16_e64 4, %9, 4, %1, 0, 0, implicit $exec883# GCN: %12:vgpr_32 = V_ADD_I16_fake16_e64 8, %11, 0, %1, 0, 0, implicit $exec884name: opsel_vop3885tracksRegLiveness: true886body: |887 bb.0:888 liveins: $vgpr0, $vgpr1889 890 %0:vgpr_32 = COPY $vgpr0891 %1:vgpr_32 = COPY $vgpr1892 %2:vgpr_32 = IMPLICIT_DEF893 894 ; Combine for op_sel:[0,0,0]895 %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec896 %4:vgpr_32 = V_ADD_I16_fake16_e64 0, %3, 0, %1, 0, 0, implicit $exec897 898 ; Do not combine for op_sel:[1,0,0]899 %5:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec900 %6:vgpr_32 = V_ADD_I16_fake16_e64 4, %5, 0, %1, 0, 0, implicit $exec901 902 ; Do not combine for op_sel:[0,1,0]903 %7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec904 %8:vgpr_32 = V_ADD_I16_fake16_e64 0, %7, 4, %1, 0, 0, implicit $exec905 906 ; Do not combine for op_sel:[1,1,0]907 %9:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec908 %10:vgpr_32 = V_ADD_I16_fake16_e64 4, %9, 4, %1, 0, 0, implicit $exec909 910 ; Do not combine for op_sel:[0,0,1] (dst_op_sel only)911 %11:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec912 %12:vgpr_32 = V_ADD_I16_fake16_e64 8, %11, 0, %1, 0, 0, implicit $exec913...914 915# Check op_sel is all 0s and op_sel_hi is all 1s when combining916# GCN-LABEL: name: opsel_vop3p917# GCN: %5:vgpr_32 = V_FMA_MIX_F32 0, %4, 0, %1, 0, %2, 0, 0, 0, implicit $mode, implicit $exec918# GCN: %7:vgpr_32 = V_FMA_MIX_F32 4, %6, 4, %1, 4, %2, 0, 0, 0, implicit $mode, implicit $exec919# GCN: %9:vgpr_32 = V_FMA_MIX_F32_dpp %3, 8, %0, 8, %1, 8, %2, 0, 0, 7, 1, 15, 15, 1, implicit $mode, implicit $exec920# GCN: %11:vgpr_32 = V_FMA_MIX_F32 12, %10, 12, %1, 12, %2, 0, 0, 0, implicit $mode, implicit $exec921 922name: opsel_vop3p923tracksRegLiveness: true924body: |925 bb.0:926 liveins: $vgpr0, $vgpr1, $vgpr2927 928 %0:vgpr_32 = COPY $vgpr0929 %1:vgpr_32 = COPY $vgpr1930 %2:vgpr_32 = COPY $vgpr2931 %3:vgpr_32 = IMPLICIT_DEF932 933 ; Do not combine for op_sel:[0,0,0] op_sel_hi:[0,0,0]934 %4:vgpr_32 = V_MOV_B32_dpp %3, %0, 1, 15, 15, 1, implicit $exec935 %5:vgpr_32 = V_FMA_MIX_F32 0, %4, 0, %1, 0, %2, 0, 0, 0, implicit $mode, implicit $exec936 937 ; Do not combine for op_sel:[1,1,1] op_sel_hi:[0,0,0]938 %6:vgpr_32 = V_MOV_B32_dpp %3, %0, 1, 15, 15, 1, implicit $exec939 %7:vgpr_32 = V_FMA_MIX_F32 4, %6, 4, %1, 4, %2, 0, 0, 0, implicit $mode, implicit $exec940 941 ; Combine for op_sel:[0,0,0] op_sel_hi:[1,1,1]942 %8:vgpr_32 = V_MOV_B32_dpp %3, %0, 1, 15, 15, 1, implicit $exec943 %9:vgpr_32 = V_FMA_MIX_F32 8, %8, 8, %1, 8, %2, 0, 0, 0, implicit $mode, implicit $exec944 945 ; Do not combine for op_sel:[1,1,1] op_sel_hi:[1,1,1]946 %10:vgpr_32 = V_MOV_B32_dpp %3, %0, 1, 15, 15, 1, implicit $exec947 %11:vgpr_32 = V_FMA_MIX_F32 12, %10, 12, %1, 12, %2, 0, 0, 0, implicit $mode, implicit $exec948...949