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1; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s2; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s3 4; GCN-LABEL: ds_read32_combine_stride_400:5; GCN: s_load_dword [[ARG:s[0-9]+]], s[8:9], 0x06; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]7 8; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]9; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]10; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]11 12; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x200, [[BASE]]13; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x400, [[BASE]]14; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x800, [[BASE]]15 16; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:10017; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:72 offset1:17218; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset0:144 offset1:24419; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset0:88 offset1:18820define amdgpu_kernel void @ds_read32_combine_stride_400(ptr addrspace(3) nocapture readonly %arg, ptr nocapture %arg1) {21bb:22 %tmp = load float, ptr addrspace(3) %arg, align 423 %tmp2 = fadd float %tmp, 0.000000e+0024 %tmp3 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 10025 %tmp4 = load float, ptr addrspace(3) %tmp3, align 426 %tmp5 = fadd float %tmp2, %tmp427 %tmp6 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 20028 %tmp7 = load float, ptr addrspace(3) %tmp6, align 429 %tmp8 = fadd float %tmp5, %tmp730 %tmp9 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 30031 %tmp10 = load float, ptr addrspace(3) %tmp9, align 432 %tmp11 = fadd float %tmp8, %tmp1033 %tmp12 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 40034 %tmp13 = load float, ptr addrspace(3) %tmp12, align 435 %tmp14 = fadd float %tmp11, %tmp1336 %tmp15 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 50037 %tmp16 = load float, ptr addrspace(3) %tmp15, align 438 %tmp17 = fadd float %tmp14, %tmp1639 %tmp18 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 60040 %tmp19 = load float, ptr addrspace(3) %tmp18, align 441 %tmp20 = fadd float %tmp17, %tmp1942 %tmp21 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 70043 %tmp22 = load float, ptr addrspace(3) %tmp21, align 444 %tmp23 = fadd float %tmp20, %tmp2245 store float %tmp23, ptr %arg1, align 446 ret void47}48 49; GCN-LABEL: ds_read32_combine_stride_20:50; GCN: s_load_dword [[ARG:s[0-9]+]], s[8:9], 0x051; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]52 53; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]54; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]55 56; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x400, [[BASE]]57; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x800, [[BASE]]58 59; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:144 offset1:16460; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:184 offset1:20461; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:224 offset1:24462; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset0:8 offset1:2863define amdgpu_kernel void @ds_read32_combine_stride_20(ptr addrspace(3) nocapture readonly %arg, ptr nocapture %arg1) {64bb:65 %tmp = getelementptr inbounds float, ptr addrspace(3) %arg, i32 40066 %tmp1 = load float, ptr addrspace(3) %tmp, align 467 %tmp2 = fadd float %tmp1, 0.000000e+0068 %tmp3 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 42069 %tmp4 = load float, ptr addrspace(3) %tmp3, align 470 %tmp5 = fadd float %tmp2, %tmp471 %tmp6 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 44072 %tmp7 = load float, ptr addrspace(3) %tmp6, align 473 %tmp8 = fadd float %tmp5, %tmp774 %tmp9 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 46075 %tmp10 = load float, ptr addrspace(3) %tmp9, align 476 %tmp11 = fadd float %tmp8, %tmp1077 %tmp12 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 48078 %tmp13 = load float, ptr addrspace(3) %tmp12, align 479 %tmp14 = fadd float %tmp11, %tmp1380 %tmp15 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 50081 %tmp16 = load float, ptr addrspace(3) %tmp15, align 482 %tmp17 = fadd float %tmp14, %tmp1683 %tmp18 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 52084 %tmp19 = load float, ptr addrspace(3) %tmp18, align 485 %tmp20 = fadd float %tmp17, %tmp1986 %tmp21 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 54087 %tmp22 = load float, ptr addrspace(3) %tmp21, align 488 %tmp23 = fadd float %tmp20, %tmp2289 store float %tmp23, ptr %arg1, align 490 ret void91}92 93; GCN-LABEL: ds_read32_combine_stride_400_back:94; GCN: s_load_dword [[ARG:s[0-9]+]], s[8:9], 0x095; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]96 97; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]98; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]99; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]100 101; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x800, [[BASE]]102; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x400, [[BASE]]103; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x200, [[BASE]]104 105; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:100106; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:88 offset1:188107; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset0:144 offset1:244108; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset0:72 offset1:172109define amdgpu_kernel void @ds_read32_combine_stride_400_back(ptr addrspace(3) nocapture readonly %arg, ptr nocapture %arg1) {110bb:111 %tmp = getelementptr inbounds float, ptr addrspace(3) %arg, i32 700112 %tmp2 = load float, ptr addrspace(3) %tmp, align 4113 %tmp3 = fadd float %tmp2, 0.000000e+00114 %tmp4 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 600115 %tmp5 = load float, ptr addrspace(3) %tmp4, align 4116 %tmp6 = fadd float %tmp3, %tmp5117 %tmp7 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 500118 %tmp8 = load float, ptr addrspace(3) %tmp7, align 4119 %tmp9 = fadd float %tmp6, %tmp8120 %tmp10 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 400121 %tmp11 = load float, ptr addrspace(3) %tmp10, align 4122 %tmp12 = fadd float %tmp9, %tmp11123 %tmp13 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 300124 %tmp14 = load float, ptr addrspace(3) %tmp13, align 4125 %tmp15 = fadd float %tmp12, %tmp14126 %tmp16 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 200127 %tmp17 = load float, ptr addrspace(3) %tmp16, align 4128 %tmp18 = fadd float %tmp15, %tmp17129 %tmp19 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 100130 %tmp20 = load float, ptr addrspace(3) %tmp19, align 4131 %tmp21 = fadd float %tmp18, %tmp20132 %tmp22 = load float, ptr addrspace(3) %arg, align 4133 %tmp23 = fadd float %tmp21, %tmp22134 store float %tmp23, ptr %arg1, align 4135 ret void136}137 138; GCN-LABEL: ds_read32_combine_stride_8192:139; GCN: s_load_dword [[ARG:s[0-9]+]], s[8:9], 0x0140; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]141; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:32142; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:64 offset1:96143; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:128 offset1:160144; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:192 offset1:224145define amdgpu_kernel void @ds_read32_combine_stride_8192(ptr addrspace(3) nocapture readonly %arg, ptr nocapture %arg1) {146bb:147 %tmp = load float, ptr addrspace(3) %arg, align 4148 %tmp2 = fadd float %tmp, 0.000000e+00149 %tmp3 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 2048150 %tmp4 = load float, ptr addrspace(3) %tmp3, align 4151 %tmp5 = fadd float %tmp2, %tmp4152 %tmp6 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 4096153 %tmp7 = load float, ptr addrspace(3) %tmp6, align 4154 %tmp8 = fadd float %tmp5, %tmp7155 %tmp9 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 6144156 %tmp10 = load float, ptr addrspace(3) %tmp9, align 4157 %tmp11 = fadd float %tmp8, %tmp10158 %tmp12 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 8192159 %tmp13 = load float, ptr addrspace(3) %tmp12, align 4160 %tmp14 = fadd float %tmp11, %tmp13161 %tmp15 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 10240162 %tmp16 = load float, ptr addrspace(3) %tmp15, align 4163 %tmp17 = fadd float %tmp14, %tmp16164 %tmp18 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 12288165 %tmp19 = load float, ptr addrspace(3) %tmp18, align 4166 %tmp20 = fadd float %tmp17, %tmp19167 %tmp21 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 14336168 %tmp22 = load float, ptr addrspace(3) %tmp21, align 4169 %tmp23 = fadd float %tmp20, %tmp22170 store float %tmp23, ptr %arg1, align 4171 ret void172}173 174; GCN-LABEL: ds_read32_combine_stride_8192_shifted:175; GCN: s_load_dword [[ARG:s[0-9]+]], s[8:9], 0x0176; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]177 178; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]]179; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 8, [[BASE]]180 181; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:32182; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:64 offset1:96183; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:128 offset1:160184define amdgpu_kernel void @ds_read32_combine_stride_8192_shifted(ptr addrspace(3) nocapture readonly %arg, ptr nocapture %arg1) {185bb:186 %tmp = getelementptr inbounds float, ptr addrspace(3) %arg, i32 2187 %tmp2 = load float, ptr addrspace(3) %tmp, align 4188 %tmp3 = fadd float %tmp2, 0.000000e+00189 %tmp4 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 2050190 %tmp5 = load float, ptr addrspace(3) %tmp4, align 4191 %tmp6 = fadd float %tmp3, %tmp5192 %tmp7 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 4098193 %tmp8 = load float, ptr addrspace(3) %tmp7, align 4194 %tmp9 = fadd float %tmp6, %tmp8195 %tmp10 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 6146196 %tmp11 = load float, ptr addrspace(3) %tmp10, align 4197 %tmp12 = fadd float %tmp9, %tmp11198 %tmp13 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 8194199 %tmp14 = load float, ptr addrspace(3) %tmp13, align 4200 %tmp15 = fadd float %tmp12, %tmp14201 %tmp16 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 10242202 %tmp17 = load float, ptr addrspace(3) %tmp16, align 4203 %tmp18 = fadd float %tmp15, %tmp17204 store float %tmp18, ptr %arg1, align 4205 ret void206}207 208; GCN-LABEL: ds_read64_combine_stride_400:209; GCN: s_load_dword [[ARG:s[0-9]+]], s[8:9], 0x0210; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]211 212; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]213; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x800, [[BASE]]214 215; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:50216; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:100 offset1:150217; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:200 offset1:250218; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:44 offset1:94219define amdgpu_kernel void @ds_read64_combine_stride_400(ptr addrspace(3) nocapture readonly %arg, ptr nocapture %arg1) {220bb:221 %tmp = load double, ptr addrspace(3) %arg, align 8222 %tmp2 = fadd double %tmp, 0.000000e+00223 %tmp3 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 50224 %tmp4 = load double, ptr addrspace(3) %tmp3, align 8225 %tmp5 = fadd double %tmp2, %tmp4226 %tmp6 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 100227 %tmp7 = load double, ptr addrspace(3) %tmp6, align 8228 %tmp8 = fadd double %tmp5, %tmp7229 %tmp9 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 150230 %tmp10 = load double, ptr addrspace(3) %tmp9, align 8231 %tmp11 = fadd double %tmp8, %tmp10232 %tmp12 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 200233 %tmp13 = load double, ptr addrspace(3) %tmp12, align 8234 %tmp14 = fadd double %tmp11, %tmp13235 %tmp15 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 250236 %tmp16 = load double, ptr addrspace(3) %tmp15, align 8237 %tmp17 = fadd double %tmp14, %tmp16238 %tmp18 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 300239 %tmp19 = load double, ptr addrspace(3) %tmp18, align 8240 %tmp20 = fadd double %tmp17, %tmp19241 %tmp21 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 350242 %tmp22 = load double, ptr addrspace(3) %tmp21, align 8243 %tmp23 = fadd double %tmp20, %tmp22244 store double %tmp23, ptr %arg1, align 8245 ret void246}247 248; GCN-LABEL: ds_read64_combine_stride_8192_shifted:249; GCN: s_load_dword [[ARG:s[0-9]+]], s[8:9], 0x0250; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]251 252; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]]253; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 8, [[BASE]]254 255; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:16256; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:32 offset1:48257; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:64 offset1:80258define amdgpu_kernel void @ds_read64_combine_stride_8192_shifted(ptr addrspace(3) nocapture readonly %arg, ptr nocapture %arg1) {259bb:260 %tmp = getelementptr inbounds double, ptr addrspace(3) %arg, i32 1261 %tmp2 = load double, ptr addrspace(3) %tmp, align 8262 %tmp3 = fadd double %tmp2, 0.000000e+00263 %tmp4 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 1025264 %tmp5 = load double, ptr addrspace(3) %tmp4, align 8265 %tmp6 = fadd double %tmp3, %tmp5266 %tmp7 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 2049267 %tmp8 = load double, ptr addrspace(3) %tmp7, align 8268 %tmp9 = fadd double %tmp6, %tmp8269 %tmp10 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 3073270 %tmp11 = load double, ptr addrspace(3) %tmp10, align 8271 %tmp12 = fadd double %tmp9, %tmp11272 %tmp13 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 4097273 %tmp14 = load double, ptr addrspace(3) %tmp13, align 8274 %tmp15 = fadd double %tmp12, %tmp14275 %tmp16 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 5121276 %tmp17 = load double, ptr addrspace(3) %tmp16, align 8277 %tmp18 = fadd double %tmp15, %tmp17278 store double %tmp18, ptr %arg1, align 8279 ret void280}281 282; GCN-LABEL: ds_write32_combine_stride_400:283; GCN: s_load_dword [[ARG:s[0-9]+]], s[8:9], 0x0284; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]285 286; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]287; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]288; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]289 290; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x200, [[BASE]]291; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x400, [[BASE]]292; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x800, [[BASE]]293 294; GCN-DAG: ds_write2_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100295; GCN-DAG: ds_write2_b32 [[B1]], v{{[0-9]+}}, v{{[0-9]+}} offset0:72 offset1:172296; GCN-DAG: ds_write2_b32 [[B2]], v{{[0-9]+}}, v{{[0-9]+}} offset0:144 offset1:244297; GCN-DAG: ds_write2_b32 [[B3]], v{{[0-9]+}}, v{{[0-9]+}} offset0:88 offset1:188298define amdgpu_kernel void @ds_write32_combine_stride_400(ptr addrspace(3) nocapture %arg) {299bb:300 store float 1.000000e+00, ptr addrspace(3) %arg, align 4301 %tmp = getelementptr inbounds float, ptr addrspace(3) %arg, i32 100302 store float 1.000000e+00, ptr addrspace(3) %tmp, align 4303 %tmp1 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 200304 store float 1.000000e+00, ptr addrspace(3) %tmp1, align 4305 %tmp2 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 300306 store float 1.000000e+00, ptr addrspace(3) %tmp2, align 4307 %tmp3 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 400308 store float 1.000000e+00, ptr addrspace(3) %tmp3, align 4309 %tmp4 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 500310 store float 1.000000e+00, ptr addrspace(3) %tmp4, align 4311 %tmp5 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 600312 store float 1.000000e+00, ptr addrspace(3) %tmp5, align 4313 %tmp6 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 700314 store float 1.000000e+00, ptr addrspace(3) %tmp6, align 4315 ret void316}317 318; GCN-LABEL: ds_write32_combine_stride_400_back:319; GCN: s_load_dword [[ARG:s[0-9]+]], s[8:9], 0x0320; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]321 322; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]323; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]324; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]325 326; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x800, [[BASE]]327; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x400, [[BASE]]328; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x200, [[BASE]]329 330; GCN-DAG: ds_write2_b32 [[B1]], v{{[0-9]+}}, v{{[0-9]+}} offset0:88 offset1:188331; GCN-DAG: ds_write2_b32 [[B2]], v{{[0-9]+}}, v{{[0-9]+}} offset0:144 offset1:244332; GCN-DAG: ds_write2_b32 [[B3]], v{{[0-9]+}}, v{{[0-9]+}} offset0:72 offset1:172333; GCN-DAG: ds_write2_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100334define amdgpu_kernel void @ds_write32_combine_stride_400_back(ptr addrspace(3) nocapture %arg) {335bb:336 %tmp = getelementptr inbounds float, ptr addrspace(3) %arg, i32 700337 store float 1.000000e+00, ptr addrspace(3) %tmp, align 4338 %tmp1 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 600339 store float 1.000000e+00, ptr addrspace(3) %tmp1, align 4340 %tmp2 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 500341 store float 1.000000e+00, ptr addrspace(3) %tmp2, align 4342 %tmp3 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 400343 store float 1.000000e+00, ptr addrspace(3) %tmp3, align 4344 %tmp4 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 300345 store float 1.000000e+00, ptr addrspace(3) %tmp4, align 4346 %tmp5 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 200347 store float 1.000000e+00, ptr addrspace(3) %tmp5, align 4348 %tmp6 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 100349 store float 1.000000e+00, ptr addrspace(3) %tmp6, align 4350 store float 1.000000e+00, ptr addrspace(3) %arg, align 4351 ret void352}353 354; GCN-LABEL: ds_write32_combine_stride_8192:355; GCN: s_load_dword [[ARG:s[0-9]+]], s[8:9], 0x0356; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]357; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32358; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset0:64 offset1:96359; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset0:128 offset1:160360; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset0:192 offset1:224361define amdgpu_kernel void @ds_write32_combine_stride_8192(ptr addrspace(3) nocapture %arg) {362bb:363 store float 1.000000e+00, ptr addrspace(3) %arg, align 4364 %tmp = getelementptr inbounds float, ptr addrspace(3) %arg, i32 2048365 store float 1.000000e+00, ptr addrspace(3) %tmp, align 4366 %tmp1 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 4096367 store float 1.000000e+00, ptr addrspace(3) %tmp1, align 4368 %tmp2 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 6144369 store float 1.000000e+00, ptr addrspace(3) %tmp2, align 4370 %tmp3 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 8192371 store float 1.000000e+00, ptr addrspace(3) %tmp3, align 4372 %tmp4 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 10240373 store float 1.000000e+00, ptr addrspace(3) %tmp4, align 4374 %tmp5 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 12288375 store float 1.000000e+00, ptr addrspace(3) %tmp5, align 4376 %tmp6 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 14336377 store float 1.000000e+00, ptr addrspace(3) %tmp6, align 4378 ret void379}380 381; GCN-LABEL: ds_write32_combine_stride_8192_shifted:382; GCN: s_load_dword [[ARG:s[0-9]+]], s[8:9], 0x0383; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]384 385; VI-DAG: v_add_u32_e32 [[BASE:v[0-9]+]], vcc, 4, [[BASE]]386; GFX9-DAG: v_add_u32_e32 [[BASE:v[0-9]+]], 4, [[BASE]]387 388; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32389; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset0:64 offset1:96390; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset0:128 offset1:160391define amdgpu_kernel void @ds_write32_combine_stride_8192_shifted(ptr addrspace(3) nocapture %arg) {392bb:393 %tmp = getelementptr inbounds float, ptr addrspace(3) %arg, i32 1394 store float 1.000000e+00, ptr addrspace(3) %tmp, align 4395 %tmp1 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 2049396 store float 1.000000e+00, ptr addrspace(3) %tmp1, align 4397 %tmp2 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 4097398 store float 1.000000e+00, ptr addrspace(3) %tmp2, align 4399 %tmp3 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 6145400 store float 1.000000e+00, ptr addrspace(3) %tmp3, align 4401 %tmp4 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 8193402 store float 1.000000e+00, ptr addrspace(3) %tmp4, align 4403 %tmp5 = getelementptr inbounds float, ptr addrspace(3) %arg, i32 10241404 store float 1.000000e+00, ptr addrspace(3) %tmp5, align 4405 ret void406}407 408; GCN-LABEL: ds_write64_combine_stride_400:409; GCN: s_load_dword [[ARG:s[0-9]+]], s[8:9], 0x0410; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]411 412; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]413; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x800, [[BASE]]414 415; GCN-DAG: ds_write2_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:50416; GCN-DAG: ds_write2_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset0:100 offset1:150417; GCN-DAG: ds_write2_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset0:200 offset1:250418; GCN-DAG: ds_write2_b64 [[B1]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset0:44 offset1:94419define amdgpu_kernel void @ds_write64_combine_stride_400(ptr addrspace(3) nocapture %arg) {420bb:421 store double 1.000000e+00, ptr addrspace(3) %arg, align 8422 %tmp = getelementptr inbounds double, ptr addrspace(3) %arg, i32 50423 store double 1.000000e+00, ptr addrspace(3) %tmp, align 8424 %tmp1 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 100425 store double 1.000000e+00, ptr addrspace(3) %tmp1, align 8426 %tmp2 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 150427 store double 1.000000e+00, ptr addrspace(3) %tmp2, align 8428 %tmp3 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 200429 store double 1.000000e+00, ptr addrspace(3) %tmp3, align 8430 %tmp4 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 250431 store double 1.000000e+00, ptr addrspace(3) %tmp4, align 8432 %tmp5 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 300433 store double 1.000000e+00, ptr addrspace(3) %tmp5, align 8434 %tmp6 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 350435 store double 1.000000e+00, ptr addrspace(3) %tmp6, align 8436 ret void437}438 439; GCN-LABEL: ds_write64_combine_stride_8192_shifted:440; GCN: s_load_dword [[ARG:s[0-9]+]], s[8:9], 0x0441; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]442 443; VI-DAG: v_add_u32_e32 [[BASE]], vcc, 8, [[BASE]]444; GFX9-DAG: v_add_u32_e32 [[BASE]], 8, [[BASE]]445 446; GCN-DAG: ds_write2st64_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:16447; GCN-DAG: ds_write2st64_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset0:32 offset1:48448; GCN-DAG: ds_write2st64_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset0:64 offset1:80449define amdgpu_kernel void @ds_write64_combine_stride_8192_shifted(ptr addrspace(3) nocapture %arg) {450bb:451 %tmp = getelementptr inbounds double, ptr addrspace(3) %arg, i32 1452 store double 1.000000e+00, ptr addrspace(3) %tmp, align 8453 %tmp1 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 1025454 store double 1.000000e+00, ptr addrspace(3) %tmp1, align 8455 %tmp2 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 2049456 store double 1.000000e+00, ptr addrspace(3) %tmp2, align 8457 %tmp3 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 3073458 store double 1.000000e+00, ptr addrspace(3) %tmp3, align 8459 %tmp4 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 4097460 store double 1.000000e+00, ptr addrspace(3) %tmp4, align 8461 %tmp5 = getelementptr inbounds double, ptr addrspace(3) %arg, i32 5121462 store double 1.000000e+00, ptr addrspace(3) %tmp5, align 8463 ret void464}465