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1; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=GCN %s2 3 4; There is no dependence between the store and the two loads. So we can combine5; the loads and schedule it freely.6 7; GCN-LABEL: {{^}}ds_combine_nodep8 9; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:2710; GCN-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7 offset1:811; GCN: s_waitcnt lgkmcnt({{[0-9]+}})12define amdgpu_kernel void @ds_combine_nodep(ptr addrspace(1) %out, ptr addrspace(3) %inptr) #0 {13 14 %addr0 = getelementptr i8, ptr addrspace(3) %inptr, i32 2415 %load0 = load <3 x float>, ptr addrspace(3) %addr0, align 416 %v0 = extractelement <3 x float> %load0, i32 217 18 %tmp1 = insertelement <2 x float> poison, float 1.0, i32 019 %data = insertelement <2 x float> %tmp1, float 2.0, i32 120 21 %tmp2 = getelementptr float, ptr addrspace(3) %inptr, i32 2622 store <2 x float> %data, ptr addrspace(3) %tmp2, align 423 24 %vaddr1 = getelementptr float, ptr addrspace(3) %inptr, i32 725 %v1 = load float, ptr addrspace(3) %vaddr1, align 426 27 %sum = fadd float %v0, %v128 store float %sum, ptr addrspace(1) %out, align 429 ret void30}31 32 33; The store depends on the first load, so we could not move the first load down to combine with34; the second load directly. However, we can move the store after the combined load.35 36; GCN-LABEL: {{^}}ds_combine_WAR37 38; GCN: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7 offset1:2739; GCN-NEXT: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:2740define amdgpu_kernel void @ds_combine_WAR(ptr addrspace(1) %out, ptr addrspace(3) %inptr) #0 {41 42 %addr0 = getelementptr i8, ptr addrspace(3) %inptr, i32 10043 %load0 = load <3 x float>, ptr addrspace(3) %addr0, align 444 %v0 = extractelement <3 x float> %load0, i32 245 46 %tmp1 = insertelement <2 x float> poison, float 1.0, i32 047 %data = insertelement <2 x float> %tmp1, float 2.0, i32 148 49 %tmp2 = getelementptr float, ptr addrspace(3) %inptr, i32 2650 store <2 x float> %data, ptr addrspace(3) %tmp2, align 451 52 %vaddr1 = getelementptr float, ptr addrspace(3) %inptr, i32 753 %v1 = load float, ptr addrspace(3) %vaddr1, align 454 55 %sum = fadd float %v0, %v156 store float %sum, ptr addrspace(1) %out, align 457 ret void58}59 60 61; The second load depends on the store. We could combine the two loads, putting62; the combined load at the original place of the second load, but we prefer to63; leave the first load near the start of the function to hide its latency.64 65; GCN-LABEL: {{^}}ds_combine_RAW66 67; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:2768; GCN-NEXT: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:3269; GCN-NEXT: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:10470define amdgpu_kernel void @ds_combine_RAW(ptr addrspace(1) %out, ptr addrspace(3) %inptr) #0 {71 72 %addr0 = getelementptr i8, ptr addrspace(3) %inptr, i32 2473 %load0 = load <3 x float>, ptr addrspace(3) %addr0, align 474 %v0 = extractelement <3 x float> %load0, i32 275 76 %tmp1 = insertelement <2 x float> poison, float 1.0, i32 077 %data = insertelement <2 x float> %tmp1, float 2.0, i32 178 79 %tmp2 = getelementptr float, ptr addrspace(3) %inptr, i32 2680 store <2 x float> %data, ptr addrspace(3) %tmp2, align 481 82 %vaddr1 = getelementptr float, ptr addrspace(3) %inptr, i32 2683 %v1 = load float, ptr addrspace(3) %vaddr1, align 484 85 %sum = fadd float %v0, %v186 store float %sum, ptr addrspace(1) %out, align 487 ret void88}89 90 91; The store depends on the first load, also the second load depends on the store.92; So we can not combine the two loads.93 94; GCN-LABEL: {{^}}ds_combine_WAR_RAW95 96; GCN: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:10897; GCN-NEXT: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:2798; GCN-NEXT: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:10499define amdgpu_kernel void @ds_combine_WAR_RAW(ptr addrspace(1) %out, ptr addrspace(3) %inptr) #0 {100 101 %addr0 = getelementptr i8, ptr addrspace(3) %inptr, i32 100102 %load0 = load <3 x float>, ptr addrspace(3) %addr0, align 4103 %v0 = extractelement <3 x float> %load0, i32 2104 105 %tmp1 = insertelement <2 x float> poison, float 1.0, i32 0106 %data = insertelement <2 x float> %tmp1, float 2.0, i32 1107 108 %tmp2 = getelementptr float, ptr addrspace(3) %inptr, i32 26109 store <2 x float> %data, ptr addrspace(3) %tmp2, align 4110 111 %vaddr1 = getelementptr float, ptr addrspace(3) %inptr, i32 26112 %v1 = load float, ptr addrspace(3) %vaddr1, align 4113 114 %sum = fadd float %v0, %v1115 store float %sum, ptr addrspace(1) %out, align 4116 ret void117}118 119attributes #0 = { "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }120